coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/apollolake: Add SGX support
by Pratikkumar V Prajapati (Code Review) 29 Aug '17

29 Aug '17

Pratikkumar V Prajapati has uploaded a new patch set (#2). ( https://review.coreboot.org/21276 ) Change subject: soc/intel/apollolake: Add SGX support ...................................................................... soc/intel/apollolake: Add SGX support - Call into commmon SGX code to configure core PRMRR and follow other SGX init seqeuence. - Report correct cbmem top with PRMRR enabled - Enable SOC_INTEL_COMMON_BLOCK_SGX for both APL/GLK, so that build does not break. - Enable SOC_INTEL_COMMON_BLOCK_CPU_MPINIT for GLK, as MP init needs to be completed before calling into fsp-s for SGX. Change-Id: I9331cf5b2cbc86431e2749b84a55f77f7f3c5960 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/cpu.c A src/soc/intel/apollolake/include/soc/msr.h M src/soc/intel/apollolake/memmap.c 5 files changed, 61 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/21276/2 -- To view, visit https://review.coreboot.org/21276 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9331cf5b2cbc86431e2749b84a55f77f7f3c5960 Gerrit-Change-Number: 21276 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Add SGX support
by Pratikkumar V Prajapati (Code Review) 29 Aug '17

29 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21276 Change subject: soc/intel/apollolake: Add SGX support ...................................................................... soc/intel/apollolake: Add SGX support - Call into commmon SGX code to configure core PRMRR and follow other SGX init seqeuence. - Report correct cbmem top with PRMRR enabled - Enable SOC_INTEL_COMMON_BLOCK_SGX for both APL/GLK, so that build does not break. - Enable SOC_INTEL_COMMON_BLOCK_CPU_MPINIT for GLK, as MP init needs to be completed before calling into fsp-s for SGX. Change-Id: I9331cf5b2cbc86431e2749b84a55f77f7f3c5960 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c 4 files changed, 38 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/21276/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 5ff328b..7e13abf 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -7,6 +7,7 @@ bool default n select SOC_INTEL_APOLLOLAKE + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT help Intel GLK support @@ -77,6 +78,7 @@ select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS + select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XDCI diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index e860daa..9e2b310 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -98,6 +98,7 @@ ramstage-y += gpio_apl.c endif +CPPFLAGS_common += -I$(src)/soc/intel/apollolake CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include ifeq ($(CONFIG_SOC_INTEL_GLK),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 98cd23a..7b041c6 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015-2017 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * @@ -32,6 +32,7 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> +#include <intelblocks/sgx.h> #include <intelblocks/smm.h> #include <reg_script.h> #include <romstage_handoff.h> @@ -62,6 +63,12 @@ void soc_core_init(device_t cpu) { + /* Clear out pending MCEs */ + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + mca_configure(); + /* Set core MSRs */ reg_script_run(core_msr_script); /* @@ -70,6 +77,9 @@ * implemented in microcode. */ enable_pm_timer_emulation(); + + /* Configure Core PRMRR for SGX. */ + prmrr_core_configure(); } #if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) @@ -213,6 +223,13 @@ * the microcode on all cores before releasing them from reset. That means that * the BSP and all APs will come up with the same microcode revision. */ + +static void post_mp_init(void) +{ + smm_southbridge_enable(); + mp_run_on_all_cpus(sgx_configure, 2000); +} + static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, @@ -220,7 +237,7 @@ .get_microcode_info = get_microcode_info, .pre_mp_smm_init = smm_southbridge_clear_state, .relocation_handler = relocation_handler, - .post_mp_init = smm_southbridge_enable, + .post_mp_init = post_mp_init, }; void soc_init_cpus(struct bus *cpu_bus) diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index c54423c..87546f6 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2017 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -26,8 +26,10 @@ #include <arch/io.h> #include <assert.h> #include <cbmem.h> +#include <chip.h> #include <device/pci.h> #include <fsp/memmap.h> +#include <fsp/util.h> #include <soc/systemagent.h> #include <soc/pci_devs.h> @@ -45,7 +47,19 @@ void *cbmem_top(void) { - return (void *)smm_region_start(); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + assert(dev != NULL); + const config_t *config = dev->chip_info; + void *smm_start = (void *)smm_region_start(); + void *tolum; + tolum = smm_start; + + /* FSP allocates 2x PRMRR Size Memory for alignment */ + if (config->sgx_enable) + tolum = smm_start - ((config->PrmrrSize) << 1); + + printk(BIOS_SPEW, "cbmem_top = 0x%p\n", tolum); + return tolum; } void smm_region(void **start, size_t *size) -- To view, visit https://review.coreboot.org/21276 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9331cf5b2cbc86431e2749b84a55f77f7f3c5960 Gerrit-Change-Number: 21276 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/common/sgx: provide weak implementation of cpu_lock_sgx_mem...
by Pratikkumar V Prajapati (Code Review) 29 Aug '17

29 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21275 Change subject: soc/intel/common/sgx: provide weak implementation of cpu_lock_sgx_memory() ...................................................................... soc/intel/common/sgx: provide weak implementation of cpu_lock_sgx_memory() SOC/CPU specific provides the actual implementation if its needed. Not all SOC/CPU needs to perform this init sequence. Change-Id: I9212e99488905d245983accc8a49a94061b22119 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/common/block/sgx/sgx.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/21275/1 diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index a199a83..7480d4b 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -167,6 +167,12 @@ return 0; } +/* SOC/CPU specific provides the actual implementation if its needed */ +__attribute__((weak)) void cpu_lock_sgx_memory(void) +{ + /* Do nothing*/ +} + void sgx_configure(void) { device_t dev = SA_DEV_ROOT; -- To view, visit https://review.coreboot.org/21275 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9212e99488905d245983accc8a49a94061b22119 Gerrit-Change-Number: 21275 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Add PrmrrSize and SGX enable config
by Pratikkumar V Prajapati (Code Review) 29 Aug '17

29 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21274 Change subject: soc/intel/apollolake: Add PrmrrSize and SGX enable config ...................................................................... soc/intel/apollolake: Add PrmrrSize and SGX enable config Add PrmrrSize and sgx_enable config option. PrmrrSize gets configured in romstage so that FSP can allocate memory for SGX. Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21274/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 33e2dad..750f53a 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -117,6 +117,15 @@ /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; + + /* PRMRR size setting with three options + * 0x02000000 - 32MiB + * 0x04000000 - 64MiB + * 0x08000000 - 128MiB */ + uint32_t PrmrrSize; + + /* Enable SGX feature */ + uint8_t sgx_enable; }; typedef struct soc_intel_apollolake_config config_t; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2017d84..44e781e 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -319,13 +319,25 @@ } } +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + m_cfg->PrmrrSize = config->PrmrrSize; +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + assert(dev != NULL); + const config_t *config = dev->chip_info; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; struct region_device rdev; check_full_retrain(mupd); fill_console_params(mupd); + + soc_memory_init_params(m_cfg, config); + mainboard_memory_init_params(mupd); /* Do NOT let FSP do any GPIO pad configuration */ -- To view, visit https://review.coreboot.org/21274 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e Gerrit-Change-Number: 21274 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add PMC pci drivers
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21251 ) Change subject: soc/intel/cannonlake: Add PMC pci drivers ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14795/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59495/ : SUCCESS -- To view, visit https://review.coreboot.org/21251 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Gerrit-Change-Number: 21251 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 19:56:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add PMC pci drivers
by Lijian Zhao (Code Review) 29 Aug '17

29 Aug '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21251 Change subject: soc/intel/cannonlake: Add PMC pci drivers ...................................................................... soc/intel/cannonlake: Add PMC pci drivers Add PMC pci driver on top of PMC common code, also include pmc init code reference from skylake. Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/include/soc/pmc.h A src/soc/intel/cannonlake/pmc.c 5 files changed, 212 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/21251/3 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 0c05057..68995a0 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -19,6 +19,7 @@ bootblock-y += spi.c bootblock-$(CONFIG_UART_DEBUG) += uart.c +romstage-y += gpio.c romstage-y += gspi.c romstage-y += memmap.c romstage-y += pmutil.c @@ -29,7 +30,9 @@ ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += gspi.c +ramstage-y += gpio.c ramstage-y += memmap.c +ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += spi.c diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 48305fe..de910b7 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -62,8 +62,10 @@ int dptf_enable; /* Deep SX enable for both AC and DC */ - int deep_s3_enable; - int deep_s5_enable; + int deep_s3_enable_ac; + int deep_s3_enable_dc; + int deep_s5_enable_ac; + int deep_s5_enable_dc; /* Deep Sx Configuration * DSX_EN_WAKE_PIN - Enable WAKE# pin diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 68b137d..a3d7863 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -96,3 +96,20 @@ *num_communities = ARRAY_SIZE(cnl_communities); return cnl_communities; } + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { GPP_A, GPP_A}, + { GPP_B, GPP_B}, + { GPP_C, GPP_C}, + { GPP_D, GPP_D}, + { GPP_E, GPP_E}, + { GPP_F, GPP_F}, + { GPP_G, GPP_G}, + { GPP_H, GPP_H}, + { GPD, GPD}, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index b8e49c2..655ffce 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -105,6 +105,7 @@ #define DSX_EN_WAKE_PIN (1 << 2) #define DSX_EN_AC_PRESENT_PIN (1 << 1) #define DSX_EN_LAN_WAKE_PIN (1 << 0) +#define DSX_CFG_MASK (0x1f << 0) #define PMSYNC_TPR_CFG 0x18C4 #define PCH2CPU_TPR_CFG_LOCK (1 << 31) diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c new file mode 100644 index 0000000..dc0f069 --- /dev/null +++ b/src/soc/intel/cannonlake/pmc.c @@ -0,0 +1,187 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <chip.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <cpu/cpu.h> +#include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> +#include <pc80/mc146818rtc.h> +#include <reg_script.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <cpu/x86/smm.h> +#include <soc/pcr_ids.h> +#include <soc/ramstage.h> +#include <vboot/vbnv.h> +#include <vboot/vbnv_layout.h> + +static void pch_pmc_add_mmio_resources(device_t dev) +{ + struct resource *res; + + /* Memory-mmapped I/O registers. */ + res = new_resource(dev, PWRMBASE); + res->base = PCH_PWRM_BASE_ADDRESS; + res->size = PCH_PWRM_BASE_SIZE; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; +} + +static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index) +{ + struct resource *res; + res = new_resource(dev, index); + res->base = base; + res->size = size; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void pch_pmc_add_io_resources(device_t dev) +{ + /* PMBASE */ + pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); +} + +static void pch_pmc_read_resources(device_t dev) +{ + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add non-standard MMIO resources. */ + pch_pmc_add_mmio_resources(dev); + + /* Add IO resources. */ + pch_pmc_add_io_resources(dev); +} + +static void pch_set_acpi_mode(void) +{ + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); + printk(BIOS_DEBUG, "done.\n"); + } +} + +static void pch_rtc_init(void) +{ + uint8_t reg8; + int rtc_failed; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_B); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + write8(pmcbase + GEN_PMCON_B, reg8); + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); + } + + /* Ensure the date is set including century byte. */ + cmos_check_update_date(); + + if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) + init_vbnv_cmos(rtc_failed); + else + cmos_init(rtc_failed); +} + +static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + printk(BIOS_DEBUG, "%sabling Deep S%c\n", + enable ? "En" : "Dis", sx + '0'); + reg = read32(pmcbase + offset); + if (enable) + reg |= mask; + else + reg &= ~mask; + write32(pmcbase + offset, reg); +} + +static void config_deep_s5(int on_ac, int on_dc) +{ + /* Treat S4 the same as S5. */ + config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); + config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); + config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); + config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); +} + +static void config_deep_s3(int on_ac, int on_dc) +{ + config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); + config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); +} + +static void config_deep_sx(uint32_t deepsx_config) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg = read32(pmcbase + DSX_CFG); + reg &= ~DSX_CFG_MASK; + reg |= deepsx_config; + write32(pmcbase + DSX_CFG, reg); +} + +static void pmc_init(struct device *dev) +{ + config_t *config = dev->chip_info; + + pch_rtc_init(); + + /* Initialize power management */ + pmc_gpe_init(); + + pch_set_acpi_mode(); + + config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); + config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); + config_deep_sx(config->deep_sx_config); +} + +static struct device_operations device_ops = { + .read_resources = &pch_pmc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .init = &pmc_init, + .scan_bus = &scan_lpc_bus, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_CNL_PMC, + 0 +}; + +static const struct pci_driver pch_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/21251 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Gerrit-Change-Number: 21251 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/soraka: Camera PMIC run time power control
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20741 ) Change subject: mb/google/soraka: Camera PMIC run time power control ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59491/ : SUCCESS -- To view, visit https://review.coreboot.org/20741 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0 Gerrit-Change-Number: 20741 Gerrit-PatchSet: 10 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lakshmi G Prasad <lakshmi.g.prasad(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 29 Aug 2017 19:12:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: acpigen: Add stop gpio control to power resource
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21249 ) Change subject: acpigen: Add stop gpio control to power resource ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14792/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59488/ : SUCCESS -- To view, visit https://review.coreboot.org/21249 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f Gerrit-Change-Number: 21249 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 19:09:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/soraka: Add stop gpio control to touchscreen device
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21250 ) Change subject: mainboard/google/soraka: Add stop gpio control to touchscreen device ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14793/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59489/ : SUCCESS -- To view, visit https://review.coreboot.org/21250 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia260eb444081dbe1646c90e82c2725661e7306bc Gerrit-Change-Number: 21250 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 19:08:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/soraka: Tune I2C params (hcnt, lcnt, hold time)
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21242 ) Change subject: mainboard/google/soraka: Tune I2C params (hcnt, lcnt, hold time) ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14790/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59486/ : SUCCESS -- To view, visit https://review.coreboot.org/21242 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3e12c75eb7e82a83aa6a6bcfcc11c12f83f2d3d4 Gerrit-Change-Number: 21242 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 19:05:22 +0000 Gerrit-HasComments: No

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