coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Improve IGD detection
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20909 ) Change subject: nb/intel/sandybridge/raminit: Improve IGD detection ...................................................................... Patch Set 3: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58392/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13803/ : SUCCESS -- To view, visit https://review.coreboot.org/20909 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4bace296ead8220c930a49686f62e94d93da7f39 Gerrit-Change-Number: 20909 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 16:39:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]ec/lenovo/h8: Add nvram option to set mute button behavior
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20944 ) Change subject: [WIP]ec/lenovo/h8: Add nvram option to set mute button behavior ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58393/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13804/ : SUCCESS -- To view, visit https://review.coreboot.org/20944 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic7979d5868e0df0c02d96e238ee879c1f1fec359 Gerrit-Change-Number: 20944 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 16:29:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: libpayload/libpci: Add a constant for PCI class memory other
by Martin Roth (Code Review) 10 Aug '17

10 Aug '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/20930 ) Change subject: libpayload/libpci: Add a constant for PCI class memory other ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/20930 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I71e902c4ec843608c1518fe1e8b90fbcf98a13d1 Gerrit-Change-Number: 20930 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 16:22:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: i2c: Move to Linux like `struct i2c_msg`
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20542 ) Change subject: i2c: Move to Linux like `struct i2c_msg` ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58391/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13801/ : SUCCESS -- To view, visit https://review.coreboot.org/20542 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9 Gerrit-Change-Number: 20542 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 16:21:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]ec/lenovo/h8: Add nvram option to set mute button behavior
by Arthur Heymans (Code Review) 10 Aug '17

10 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20944 Change subject: [WIP]ec/lenovo/h8: Add nvram option to set mute button behavior ...................................................................... [WIP]ec/lenovo/h8: Add nvram option to set mute button behavior The mute button can behave in several ways: as a hardware mute of which the OS is not aware or as a regular key that generates scancodes. Do we want all modes configurable in nvram? mode1 is a bit weird and when supported I think mode3 is better than mode0. TODO: hook up this parameter nvram of all thinkpads... Change-Id: Ic7979d5868e0df0c02d96e238ee879c1f1fec359 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/ec/lenovo/h8/h8.c M src/mainboard/lenovo/x200/cmos.layout 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/20944/1 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 5ea4a2c..f734155 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -128,6 +128,35 @@ ec_clr_bit(0x3a, 0); } + +enum mute_key_mode { + /* + * Mute button asserts EC (HW) mute, volume buttons unmute + * This means the mute button can mute without the OS or + * the firmware knowing. + */ + MUTE_KEY_MODE_EC_ASSERT = 0, + /* + *If the EC is in mute (e.g. bit0 0x3a) then all volume keys works + * as scancodes for mute, pressing volume buttons for a long time + * changes the volume. In non EC mute mode all buttons simply generate + * scancode. + */ + MUTE_KEY_MODE_SCAN_ALL_MUTE = 1, + /* All volume buttons generate scancodes. */ + MUTE_KEY_MODE_SCAN_ONLY = 2, + /* Only on later thinkpads. The mute button toggles EC mute. */ + MUTE_KEY_MODE_TOGGLE = 3, +}; + +static void h8_set_mute_key_mode(enum mute_key_mode mode) +{ + if (mode & 1) + ec_set_bit(0x03, 5); + if (mode & 2) + ec_set_bit(0x03, 6); +} + void h8_enable_event(int event) { if (event < 0 || event > 127) @@ -318,6 +347,10 @@ h8_set_audio_mute(0); + if (get_option(&val, "mute_key_mode") != CB_SUCCESS) + val = 0; + h8_set_mute_key_mode(val); + #if !IS_ENABLED(CONFIG_H8_DOCK_EARLY_INIT) h8_mainboard_init_dock(); #endif diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index f3cfe70..65056df 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -71,6 +71,7 @@ 426 1 e 1 power_management_beeps 427 1 e 1 low_battery_beep 428 1 e 1 uwb +429 2 e 12 mute_key_mode # coreboot config options: bootloader 432 512 s 0 boot_devices @@ -132,6 +133,8 @@ 11 10 160M 11 11 224M 11 12 352M +12 0 Hardware +12 2 Scancode # ----------------------------------------------------------------- checksums -- To view, visit https://review.coreboot.org/20944 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic7979d5868e0df0c02d96e238ee879c1f1fec359 Gerrit-Change-Number: 20944 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/sandybridge/earlyinit: Add Kconfig for PCIe Gen3
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20929 ) Change subject: nb/intel/sandybridge/earlyinit: Add Kconfig for PCIe Gen3 ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58380/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13802/ : SUCCESS -- To view, visit https://review.coreboot.org/20929 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07b66cb353a3e572183ee00c79e8f240cf79107e Gerrit-Change-Number: 20929 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 16:11:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add Kconfig option for fuses
by Martin Roth (Code Review) 10 Aug '17

10 Aug '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/20907 ) Change subject: nb/intel/sandybridge/raminit: Add Kconfig option for fuses ...................................................................... nb/intel/sandybridge/raminit: Add Kconfig option for fuses Add a new Kconfig option to ignore memory fuses that limit the maximum DRAM frequency to be used. The option is disabled by default and should only enabled by experienced users as it might decrease system stability or prevent a successful RAM training. Remove conflicting devicetree settings. Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/20907 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Nicola Corna <nicola(a)corna.info> --- M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c 12 files changed, 15 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Nicola Corna: Looks good to me, but someone else must approve diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 542b06a..3e1f308 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -15,9 +15,6 @@ register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 3b4e6ab..934c589 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -18,9 +18,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B device lapic 0 on end diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 366d36f..d1a9bfb 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -17,9 +17,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B device lapic 0 on end diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index d112ad4..2fe895a 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -34,9 +34,6 @@ end end - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index ccee86a..6846879 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -17,9 +17,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 6df2644..c76ccc9 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -18,9 +18,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B device lapic 0 on end diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index b784898..b43c999 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -18,9 +18,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index ce74d3f..e76f68a 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -15,9 +15,6 @@ register "gpu_panel_power_up_delay" = "300" register "gpu_pch_backlight" = "0x11551155" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 62ad3b0..2bac65d 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -18,9 +18,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a1b0662..7a96a77 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -18,9 +18,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" - device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 2d13f28..7c954fb 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -44,6 +44,18 @@ Select if you want to use coreboot implementation of raminit rather than System Agent/MRC.bin. You should answer Y. +config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES + bool "Ignore vendor programmed fuses that limit max. DRAM frequency" + default n + depends on USE_NATIVE_RAMINIT + help + Ignore the mainboard's vendor programmed fuses that might limit the + maximum DRAM frequency. By selecting this option the fuses will be + ignored and the only limits on DRAM frequency are set by RAM's SPD and + hard fuses in southbridge's clockgen. + Disabled by default as it might causes system instability. + Handle with care! + config CBFS_SIZE hex default 0x100000 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c6ff551..3e69f4d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -402,6 +402,9 @@ /* If this is zero, it just means devicetree.cb didn't set it */ if (!cfg || cfg->max_mem_clock_mhz == 0) { + if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) + return TCK_1333MHZ; + rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { -- To view, visit https://review.coreboot.org/20907 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Gerrit-Change-Number: 20907 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/i82801jx: Remove dead code
by Martin Roth (Code Review) 10 Aug '17

10 Aug '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/20906 ) Change subject: sb/intel/i82801jx: Remove dead code ...................................................................... sb/intel/i82801jx: Remove dead code Setting up default BARs and DMI init code is done in northbridge code. Change-Id: I6cfa3018ca7f5ef351415c4ec6e178ade353f7a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/20906 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- D src/southbridge/intel/i82801jx/dmi_setup.c D src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/i82801jx.h 3 files changed, 0 insertions(+), 203 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/intel/i82801jx/dmi_setup.c b/src/southbridge/intel/i82801jx/dmi_setup.c deleted file mode 100644 index 83633a4..0000000 --- a/src/southbridge/intel/i82801jx/dmi_setup.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_def.h> -#include <console/console.h> -#include <northbridge/intel/gm45/gm45.h> -#include "i82801jx.h" - -/* VC1 Port Arbitration Table */ -static const u8 vc1_pat[] = { - 0x0f, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x0f, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0xf0, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0f, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0xf0, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x0f, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x0f, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0xf0, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0f, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0xf0, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, -}; -void i82801jx_dmi_setup(void) -{ - int i; - u32 reg32; - - RCBA32(RCBA_V1CAP) = (RCBA32(RCBA_V1CAP) & ~(0x7f<<16)) | (0x12<<16); - - RCBA32(0x0088) = 0x00109000; - RCBA16(0x01fc) = 0x060b; - RCBA32(0x01f4) = 0x86000040; - RCBA8 (0x0220) = 0x45; - RCBA32(0x2024) &= ~(1 << 7); - - - /* VC1 setup for isochronous transfers: */ - - /* Set VC1 virtual channel id to 1. */ - RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 24)) | (0x1 << 24); - /* Enable TC7 traffic on VC1. */ - RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7f << 1)) | (1 << 7); - /* Disable TC7-TC1 traffic on VC0. */ - RCBA32(RCBA_V0CTL) &= ~(0x7f << 1); - /* TC7-TC1 traffic on PCIe root ports will be disabled in pci driver. */ - - /* Set table type to time-based WRR. */ - RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 17)) | (0x4 << 17); - /* Program port arbitration table. */ - for (i = 0; i < sizeof(vc1_pat); ++i) - RCBA8(RCBA_PAT + i) = vc1_pat[i]; - /* Load port arbitration table. */ - RCBA32(RCBA_V1CTL) |= (1 << 16); - - /* Enable VC1. */ - RCBA32(RCBA_V1CTL) |= (1 << 31); - - - /* Setup RCRB: */ - - /* Set component id to 2 for southbridge, northbridge has id 1. */ - RCBA8(RCBA_ESD + 2) = 2; - /* Set target port number and target component id of the northbridge. */ - RCBA8(RCBA_ULD + 3) = 1; - RCBA8(RCBA_ULD + 2) = 1; - /* Set target rcrb base address, i.e. DMIBAR. */ - RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR; - - /* Enable ASPM. */ - if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) { - reg32 = RCBA32(RCBA_DMC); - /* Enable mobile specific power saving (set this first). */ - reg32 = (reg32 & ~(3 << 10)) | (1 << 10); - RCBA32(RCBA_DMC) = reg32; - /* Enable DMI power savings. */ - reg32 |= (1 << 19); - RCBA32(RCBA_DMC) = reg32; - /* Advertise L0s and L1. */ - RCBA32(RCBA_LCAP) |= (3 << 10); - /* Enable L0s and L1. */ - RCBA32(RCBA_LCTL) |= (3 << 0); - } else { - /* Enable DMI power savings. */ - RCBA32(RCBA_DMC) |= (1 << 19); - /* Advertise L0s only. */ - RCBA32(RCBA_LCAP) = (RCBA32(RCBA_LCAP) & ~(3<<10)) | (1<<10); - /* Enable L0s only. */ - RCBA32(RCBA_LCTL) = (RCBA32(RCBA_LCTL) & ~(3<< 0)) | (1<< 0); - } -} - -/* Should be called after VC1 has been enabled on both sides. */ -void i82801jx_dmi_poll_vc1(void) -{ - int timeout; - - timeout = 0x7ffff; - printk(BIOS_DEBUG, "ICH10 waits for VC1 negotiation... "); - while ((RCBA32(RCBA_V1STS) & (1 << 1)) && --timeout) {} - if (!timeout) - printk(BIOS_DEBUG, "timeout!\n"); - else - printk(BIOS_DEBUG, "done.\n"); - - /* Check for x2 DMI link. */ - if (((RCBA16(RCBA_LSTS) >> 4) & 0x3f) == 2) { - printk(BIOS_DEBUG, "x2 DMI link detected.\n"); - RCBA32(0x2024) = (RCBA32(0x2024) & ~(7 << 21)) | (3 << 21); - RCBA16(0x20c4) |= (1 << 15); - RCBA16(0x20e4) |= (1 << 15); - /* TODO: Maybe we have to save and - restore these settings across S3. */ - } - - timeout = 0x7ffff; - printk(BIOS_DEBUG, "ICH10 waits for port arbitration table update... "); - while ((RCBA32(RCBA_V1STS) & (1 << 0)) && --timeout) {} - if (!timeout) - printk(BIOS_DEBUG, "timeout!\n"); - else - printk(BIOS_DEBUG, "done.\n"); -} diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c deleted file mode 100644 index e2ac852..0000000 --- a/src/southbridge/intel/i82801jx/early_init.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include "i82801jx.h" - -void i82801jx_early_init(void) -{ - const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - - /* Set up RCBA. */ - pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - /* Set up PMBASE. */ - pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); - /* Enable PMBASE. */ - pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); - - /* Set up GPIOBASE. */ - pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); - /* Enable GPIO. */ - pci_write_config8(d31f0, D31F0_GPIO_CNTL, - pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); - - /* Reset watchdog. */ - outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ - outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */ - - /* Enable upper 128bytes of CMOS. */ - RCBA32(0x3400) = (1 << 2); - - /* Initialize power management initialization - register early as it affects reboot behavior. */ - /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6 - and 0xe (required if ME is disabled but present), bit 31 locks it. - The other bits are 'must write'. */ - u8 reg8 = pci_read_config8(d31f0, 0xac); - reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); - pci_write_config8(d31f0, 0xac, reg8); - - /* TODO: If RTC power failed, reset RTC state machine - (set, then reset RTC 0x0b bit7) */ - - /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) - before they get cleared. */ -} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index fe55157..9b0f955 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -229,9 +229,6 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -void i82801jx_early_init(void); -void i82801jx_dmi_setup(void); -void i82801jx_dmi_poll_vc1(void); int southbridge_detect_s3_resume(void); #endif -- To view, visit https://review.coreboot.org/20906 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I6cfa3018ca7f5ef351415c4ec6e178ade353f7a7 Gerrit-Change-Number: 20906 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common/uart: Add support for enabling UART debug controller...
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20835 ) Change subject: soc/intel/common/uart: Add support for enabling UART debug controller on resume ...................................................................... Patch Set 14: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58388/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13799/ : SUCCESS -- To view, visit https://review.coreboot.org/20835 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 Gerrit-Change-Number: 20835 Gerrit-PatchSet: 14 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 15:58:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Provide option to use Common MP Init
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20895 ) Change subject: soc/intel/apollolake: Provide option to use Common MP Init ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58390/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13800/ : SUCCESS -- To view, visit https://review.coreboot.org/20895 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I35d012785000d3f3bfcc34138cda9cd4591559f6 Gerrit-Change-Number: 20895 Gerrit-PatchSet: 4 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 15:57:34 +0000 Gerrit-HasComments: No

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