coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/cannonlake: Initialize struct member to 0
by Subrata Banik (Code Review) 10 Aug '17

10 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20941 Change subject: soc/intel/cannonlake: Initialize struct member to 0 ...................................................................... soc/intel/cannonlake: Initialize struct member to 0 As per GCC 7.1 compiler struct reset_reply is considered as uninitialized inside send_heci_reset_message function. Change-Id: I01b95d31bfb1d2e9af1704a28dacb9cfd1cdcb50 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/reset.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/20941/1 diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index 93714d3..0789b17 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -65,6 +65,7 @@ return -1; reply_size = sizeof(reply); + memset(&reply, 0, reply_size); heci_receive(&reply, &reply_size); /* get reply result from HECI MSG */ if (reply.result != 0) { -- To view, visit https://review.coreboot.org/20941 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I01b95d31bfb1d2e9af1704a28dacb9cfd1cdcb50 Gerrit-Change-Number: 20941 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode
by Subrata Banik (Code Review) 10 Aug '17

10 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20940 Change subject: soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode ...................................................................... soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode Need to perform a dummy read in order to activate LPSS UART's 16550 8-bit compatibility mode. TEST=Able to get serial log in both 32 bit and 8 bit mode through LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and CONFIG_DRIVERS_UART_8250MEM selection. Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/uart.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/20940/1 diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 6f5fb6d..7481c24 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -25,6 +25,12 @@ #include <soc/pcr_ids.h> #include <soc/iomap.h> +/* Serial IO UART controller legacy mode */ +#define PCR_SERIAL_IO_GPPRVRW7 0x618 +#define PCR_SIO_PCH_LEGACY_UART0 (1 << 0) +#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1) +#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2) + /* Clock divider parameters for 115200 baud rate */ #define CLK_M_VAL 0x30 #define CLK_N_VAL 0xc35 @@ -57,6 +63,19 @@ base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); uart_common_init(p->dev, base, CLK_M_VAL, CLK_N_VAL); + + /* Put UART2 in byte access mode for 16550 compatibility */ + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) { + pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, + PCR_SIO_PCH_LEGACY_UART2); + + /* + * Dummy read after setting any of GPPRVRW7. + * Required for UART 16550 8-bit Legacy mode to become active + */ + lpss_clk_read(base); + } + gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads)); } -- To view, visit https://review.coreboot.org/20940 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48 Gerrit-Change-Number: 20940 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Add proper support to enable UART2 in 16550 mode
by Subrata Banik (Code Review) 10 Aug '17

10 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20939 Change subject: soc/intel/skylake: Add proper support to enable UART2 in 16550 mode ...................................................................... soc/intel/skylake: Add proper support to enable UART2 in 16550 mode Need to perform a dummy read in order to activate LPSS UART's 16550 8-bit compatibility mode. TEST=Able to get serial log in both 32 bit and 8 bit mode through LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and CONFIG_DRIVERS_UART_8250MEM selection. Change-Id: I5f23fef4522743efd49167afb04d56032e16e417 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/bootblock/uart.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20939/1 diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c index 26b81c0..36fac36 100644 --- a/src/soc/intel/skylake/bootblock/uart.c +++ b/src/soc/intel/skylake/bootblock/uart.c @@ -48,9 +48,16 @@ uart_common_init(PCH_DEV_UART2, base, CLK_M_VAL, CLK_N_VAL); /* Put UART2 in byte access mode for 16550 compatibility */ - if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) { pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, PCR_SIO_PCH_LEGACY_UART2); + /* + * Dummy read after setting any of GPPRVRW7. + * Required for UART 16550 8-bit Legacy mode to become active + */ + lpss_clk_read(base); + } + gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } -- To view, visit https://review.coreboot.org/20939 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5f23fef4522743efd49167afb04d56032e16e417 Gerrit-Change-Number: 20939 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: common/block/lpss: Add CLK read function into LPSS common
by Subrata Banik (Code Review) 10 Aug '17

10 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20938 Change subject: common/block/lpss: Add CLK read function into LPSS common ...................................................................... common/block/lpss: Add CLK read function into LPSS common This patch add new API to read LPSS CLK register along with avoid multiple time write inside lpss_clk_update function. Change-Id: I420919ad9154c4cf426bc232c5eb59d95fd698d2 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/lpss/lpss.c 2 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/20938/1 diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index 03a4714..b2fb6c7 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -27,4 +27,7 @@ */ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); +/* Read LPSS CLK register */ +uint32_t lpss_clk_read(uintptr_t base); + #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 146fdab..da41903 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -54,7 +54,16 @@ addr += LPSS_CLOCK_CTL_REG; clk_sel = LPSS_CLOCK_DIV_N(clk_n_val) | LPSS_CLOCK_DIV_M(clk_m_val); + clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; - write32(addr, clk_sel | LPSS_CNT_CLK_UPDATE); - write32(addr, clk_sel | LPSS_CNT_CLOCK_EN); + write32(addr, clk_sel); +} + +uint32_t lpss_clk_read(uintptr_t base) +{ + uint8_t *addr = (void *)base; + + addr += LPSS_CLOCK_CTL_REG; + + return read32(addr); } -- To view, visit https://review.coreboot.org/20938 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I420919ad9154c4cf426bc232c5eb59d95fd698d2 Gerrit-Change-Number: 20938 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: nb/intel/sandybridge/gma: Fix S3 resume
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20289 ) Change subject: nb/intel/sandybridge/gma: Fix S3 resume ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58369/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13780/ : SUCCESS -- To view, visit https://review.coreboot.org/20289 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifad145c86c2e8f019c507f97c889b70b7aa49882 Gerrit-Change-Number: 20289 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 08:41:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge/gma: Fix platforms without NGI
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20925 ) Change subject: nb/intel/sandybridge/gma: Fix platforms without NGI ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58370/ : SUCCESS -- To view, visit https://review.coreboot.org/20925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife9e7f6e61339b201bd3ff42c50f197605a56e00 Gerrit-Change-Number: 20925 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Morgan <xamboni(a)protonmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 08:38:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: autoport/bd82x6x.go: Improve gpio.c generation
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19508 ) Change subject: autoport/bd82x6x.go: Improve gpio.c generation ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58368/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13779/ : SUCCESS -- To view, visit https://review.coreboot.org/19508 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 Gerrit-Change-Number: 19508 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 08:35:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: autoport: Add GPL boilerplate header to not empty .c files
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19510 ) Change subject: autoport: Add GPL boilerplate header to not empty .c files ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58367/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13778/ : SUCCESS -- To view, visit https://review.coreboot.org/19510 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d6b48762b1249bb0becb178a30e1396bf6978fc Gerrit-Change-Number: 19510 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 08:26:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8470p
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18985 ) Change subject: mainboard/hp: Add HP Elitebook 8470p ...................................................................... Patch Set 19: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58363/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13774/ : SUCCESS -- To view, visit https://review.coreboot.org/18985 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icbc051e2272b8ea73627940db15a56901d737472 Gerrit-Change-Number: 18985 Gerrit-PatchSet: 19 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 08:09:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec: add support for KBC1126 in HP laptops
by build bot (Jenkins) (Code Review) 10 Aug '17

10 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19072 ) Change subject: ec: add support for KBC1126 in HP laptops ...................................................................... Patch Set 20: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58364/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13775/ : SUCCESS -- To view, visit https://review.coreboot.org/19072 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b16eb7e26303eda740f52d667dedb7cc04b4ef0 Gerrit-Change-Number: 19072 Gerrit-PatchSet: 20 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 08:07:37 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017