coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/skylake: Configure FSP to skip ME MBP step
by Subrata Banik (Code Review) 11 Aug '17

11 Aug '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/20951 ) Change subject: soc/intel/skylake: Configure FSP to skip ME MBP step ...................................................................... Patch Set 1: > (1 comment) I'm not sure if its right way to skip MBP HOB creation and continue rest of ME further communication. i remember in SKL time, i had some doubt and somebody from ME team had given me some explanation why we still need MBP hob although we are not using this in chrome case. I need to look into this. -- To view, visit https://review.coreboot.org/20951 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Gerrit-Change-Number: 20951 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 08:19:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: 440BX boards: Drop more unused #includes from romstage
by build bot (Jenkins) (Code Review) 11 Aug '17

11 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20952 ) Change subject: 440BX boards: Drop more unused #includes from romstage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58417/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13825/ : SUCCESS -- To view, visit https://review.coreboot.org/20952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I102a4f6e492eb607b7f88d4c6e15072a8b7fdc46 Gerrit-Change-Number: 20952 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 01:11:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: 440BX boards: Use combined RAM init routine
by build bot (Jenkins) (Code Review) 11 Aug '17

11 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20868 ) Change subject: 440BX boards: Use combined RAM init routine ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58416/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13824/ : SUCCESS -- To view, visit https://review.coreboot.org/20868 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I699db882189f99018d4a6fdcb00f9438b2a7a1bc Gerrit-Change-Number: 20868 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 01:03:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Configure FSP to skip ME MBP step
by Duncan Laurie (Code Review) 11 Aug '17

11 Aug '17

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/20951 ) Change subject: soc/intel/skylake: Configure FSP to skip ME MBP step ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/20951/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/20951/1//COMMIT_MSG@13 PS1, Line 13: boot with FSP debug enabled binary and ensure that the : output indicates this step is being skipped: : Skipping MBP data due to SkipMbpHob set! > Does this also help with the boot time? I thought it should, but I am not seeing a notable improvement. -- To view, visit https://review.coreboot.org/20951 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Gerrit-Change-Number: 20951 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 01:02:09 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: 440BX boards: Drop more unused #includes from romstage
by Keith Hui (Code Review) 11 Aug '17

11 Aug '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/20952 Change subject: 440BX boards: Drop more unused #includes from romstage ...................................................................... 440BX boards: Drop more unused #includes from romstage Romstages of many 440BX boards included headers that are redundant. Remove them as part of a bigger cleanup effort. This finishes off what began in https://review.coreboot.org/20693. Change-Id: I102a4f6e492eb607b7f88d4c6e15072a8b7fdc46 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/azza/pt-6ibd/romstage.c M src/mainboard/compaq/deskpro_en_sff_p600/romstage.c M src/mainboard/msi/ms6119/romstage.c M src/mainboard/msi/ms6156/romstage.c M src/mainboard/soyo/sy-6ba-plus-iii/romstage.c 5 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/20952/1 diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index c4cfbec..61a2767 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 7a59b1b..c93dc20 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -14,15 +14,11 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <device/pci_def.h> -#include <arch/io.h> #include <device/pnp_def.h> -#include <stdlib.h> #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <delay.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index 7791e91..809f1f6 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index cf39f52..37200e5 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 770a7cb..be79c75 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/20952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I102a4f6e492eb607b7f88d4c6e15072a8b7fdc46 Gerrit-Change-Number: 20952 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: libpayload: add *SECS_PER_SEC macros to stddef.h
by build bot (Jenkins) (Code Review) 11 Aug '17

11 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20882 ) Change subject: libpayload: add *SECS_PER_SEC macros to stddef.h ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58415/ : SUCCESS -- To view, visit https://review.coreboot.org/20882 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I489dc2d1ff55d137936acec74ac875dc7fbc1713 Gerrit-Change-Number: 20882 Gerrit-PatchSet: 6 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 00:20:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Configure FSP to skip ME MBP step
by Furquan Shaikh (Code Review) 11 Aug '17

11 Aug '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/20951 ) Change subject: soc/intel/skylake: Configure FSP to skip ME MBP step ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/20951/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/20951/1//COMMIT_MSG@13 PS1, Line 13: boot with FSP debug enabled binary and ensure that the : output indicates this step is being skipped: : Skipping MBP data due to SkipMbpHob set! Does this also help with the boot time? -- To view, visit https://review.coreboot.org/20951 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Gerrit-Change-Number: 20951 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 00:04:41 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Configure FSP to skip ME MBP step
by build bot (Jenkins) (Code Review) 11 Aug '17

11 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20951 ) Change subject: soc/intel/skylake: Configure FSP to skip ME MBP step ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58414/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13823/ : SUCCESS -- To view, visit https://review.coreboot.org/20951 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Gerrit-Change-Number: 20951 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 23:42:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Configure FSP to skip ME MBP step
by Duncan Laurie (Code Review) 11 Aug '17

11 Aug '17

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/20951 Change subject: soc/intel/skylake: Configure FSP to skip ME MBP step ...................................................................... soc/intel/skylake: Configure FSP to skip ME MBP step We do not need or use the Management Engine MBP HOB so that step can be skipped when FSP initializes the ME. BUG=b:64479422 TEST=boot with FSP debug enabled binary and ensure that the output indicates this step is being skipped: Skipping MBP data due to SkipMbpHob set! Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/skylake/romstage/romstage_fsp20.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/20951/1 diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index e439d734..c43bdc3 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -222,6 +222,9 @@ soc_memory_init_params(m_cfg, config); + /* Skip creating Management Engine MBP HOB */ + m_t_cfg->SkipMbpHob = 0x01; + /* Enable DMI Virtual Channel for ME */ m_t_cfg->DmiVcm = 0x01; -- To view, visit https://review.coreboot.org/20951 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Gerrit-Change-Number: 20951 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/apollolake: Use common ACPI for apollolake
by build bot (Jenkins) (Code Review) 11 Aug '17

11 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20949 ) Change subject: soc/intel/apollolake: Use common ACPI for apollolake ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58413/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13822/ : SUCCESS -- To view, visit https://review.coreboot.org/20949 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I10e3fb74133dd499e9e74d95a909d33daaf098ec Gerrit-Change-Number: 20949 Gerrit-PatchSet: 3 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Aug 2017 22:56:49 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017