coreboot-gerrit July 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: google/fizz: Override PL2 and SysPL2 values
by build bot (Jenkins) (Code Review) 05 Jul '17

05 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20420 ) Change subject: google/fizz: Override PL2 and SysPL2 values ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56590/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12165/ : SUCCESS -- To view, visit https://review.coreboot.org/20420 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b Gerrit-Change-Number: 20420 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Jul 2017 20:43:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Set PsysPL2 MSR
by build bot (Jenkins) (Code Review) 05 Jul '17

05 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20418 ) Change subject: soc/intel/skylake: Set PsysPL2 MSR ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56589/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12163/ : SUCCESS -- To view, visit https://review.coreboot.org/20418 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Gerrit-Change-Number: 20418 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Jul 2017 20:39:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: Enable wake-on-usb attach/detach
by build bot (Jenkins) (Code Review) 05 Jul '17

05 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20421 ) Change subject: google/fizz: Enable wake-on-usb attach/detach ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56591/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12164/ : SUCCESS -- To view, visit https://review.coreboot.org/20421 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I214d6557998bdaf1d327c2a45532461b95d56a96 Gerrit-Change-Number: 20421 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Jul 2017 20:39:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add report_platform.c
by build bot (Jenkins) (Code Review) 05 Jul '17

05 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20068 ) Change subject: soc/intel/cannonlake: Add report_platform.c ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56588/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12162/ : SUCCESS -- To view, visit https://review.coreboot.org/20068 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I12d1c9dd9f0518c133de465a4db72a0664a94eef Gerrit-Change-Number: 20068 Gerrit-PatchSet: 8 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Jul 2017 18:52:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add bootblock PCH
by build bot (Jenkins) (Code Review) 05 Jul '17

05 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20067 ) Change subject: soc/intel/cannonlake: Add bootblock PCH ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56587/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12161/ : SUCCESS -- To view, visit https://review.coreboot.org/20067 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3694e099e78c2989f7192c550cbba098e5df2032 Gerrit-Change-Number: 20067 Gerrit-PatchSet: 7 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Jul 2017 18:47:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge/peg: Add PEG code
by build bot (Jenkins) (Code Review) 05 Jul '17

05 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20472 ) Change subject: nb/intel/sandybridge/peg: Add PEG code ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56586/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/12160/ : SUCCESS -- To view, visit https://review.coreboot.org/20472 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I80a106b1f969103206f24dc5c4b268503acfa81f Gerrit-Change-Number: 20472 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Jul 2017 18:17:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge/peg: Add PEG code
by Patrick Rudolph (Code Review) 05 Jul '17

05 Jul '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20472 Change subject: nb/intel/sandybridge/peg: Add PEG code ...................................................................... nb/intel/sandybridge/peg: Add PEG code * Add ACPI code for PEG. * Add PCIe driver for PEG. Change-Id: I80a106b1f969103206f24dc5c4b268503acfa81f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/Makefile.inc A src/northbridge/intel/sandybridge/acpi/peg.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl A src/northbridge/intel/sandybridge/pcie.c 4 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/20472/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 846d31b..a2ab06d 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += ram_calc.c ramstage-y += northbridge.c +ramstage-y += pcie.c ramstage-y += gma.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl new file mode 100644 index 0000000..18e3ff2 --- /dev/null +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + // PCI Interrupt Routing. + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + }) + } + } + + Device (DEV0) { + Name(_ADR, 0x00000000) + } +} diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 609106f..301ee8a 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -16,6 +16,7 @@ #include "../sandybridge.h" #include "hostbridge.asl" +#include "peg.asl" /* PCI Device Resource Consumption */ Device (PDRC) diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c new file mode 100644 index 0000000..ba8da43 --- /dev/null +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <southbridge/intel/common/pciehp.h> +#include "sandybridge.h" + +static void pcie_disable(device_t dev) +{ + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + + dev->enabled = 0; +} + +static const char *pcie_acpi_name(device_t dev) +{ + ASSERT(dev); + ASSERT(dev->bus); + + if (dev->bus->secondary == 0 && + PCI_SLOT(dev->path.pci.devfn) == 0x01 && + PCI_FUNC(dev->path.pci.devfn) == 0x00) + return "PEGP"; + + ASSERT(dev->bus->dev); + ASSERT(dev->bus->dev->bus); + + if (dev->bus->dev->bus->secondary == 0 && + PCI_SLOT(dev->bus->dev->path.pci.devfn) == 0x01 && + PCI_FUNC(dev->bus->dev->path.pci.devfn) == 0x00 && + PCI_SLOT(dev->path.pci.devfn) == 0x00 && + PCI_FUNC(dev->path.pci.devfn) == 0x00) + return "DEV0"; + + return NULL; +} + + +static void +pcie_set_subsystem(device_t dev, unsigned int vendor, unsigned int device) +{ + /* NOTE: This is not the default position! */ + if (!vendor || !device) + pci_write_config32(dev, 0x94, + pci_read_config32(dev, 0)); + else + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations pci_ops = { + .set_subsystem = pcie_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .disable = pcie_disable, + .ops_pci = &pci_ops, + .acpi_name = pcie_acpi_name, +}; + +static const unsigned short pci_device_ids[] = { 0x0101, 0x0105, 0x0109, 0x010d, + 0x0151, 0x0155, 0x0159, 0x015d, + 0 }; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/20472 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I80a106b1f969103206f24dc5c4b268503acfa81f Gerrit-Change-Number: 20472 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/lenovo/*/devicetree: Add BDC detection support
by build bot (Jenkins) (Code Review) 05 Jul '17

05 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19810 ) Change subject: mb/lenovo/*/devicetree: Add BDC detection support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56585/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12158/ : SUCCESS -- To view, visit https://review.coreboot.org/19810 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9 Gerrit-Change-Number: 19810 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Jul 2017 16:44:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8: Add BDC detection support
by build bot (Jenkins) (Code Review) 05 Jul '17

05 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19809 ) Change subject: ec/lenovo/h8: Add BDC detection support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56584/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12159/ : SUCCESS -- To view, visit https://review.coreboot.org/19809 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I506de2eca4b820e6d82de6b2c48a5440462e1db5 Gerrit-Change-Number: 19809 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Jul 2017 16:42:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8: Add panic method
by build bot (Jenkins) (Code Review) 05 Jul '17

05 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19695 ) Change subject: ec/lenovo/h8: Add panic method ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56583/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12157/ : SUCCESS -- To view, visit https://review.coreboot.org/19695 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8 Gerrit-Change-Number: 19695 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Jul 2017 16:25:49 +0000 Gerrit-HasComments: No

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coreboot-gerrit July 2017