coreboot-gerrit June 2017

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Change in coreboot[master]: mb/foxconn/g41s-k: add new mainboard
by build bot (Jenkins) (Code Review) 03 Jun '17

03 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20027 ) Change subject: mb/foxconn/g41s-k: add new mainboard ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10547/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54847/ : SUCCESS -- To view, visit https://review.coreboot.org/20027 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda Gerrit-Change-Number: 20027 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Jun 2017 22:49:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/ite/it8728f: remove unused header
by build bot (Jenkins) (Code Review) 03 Jun '17

03 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20025 ) Change subject: superio/ite/it8728f: remove unused header ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10545/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54845/ : SUCCESS -- To view, visit https://review.coreboot.org/20025 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifcbf95ffd6d13cae4e6864e0320ce6ce1cf3ae4d Gerrit-Change-Number: 20025 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Jun 2017 22:38:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/acpi: extend generic ACPI PnP device
by build bot (Jenkins) (Code Review) 03 Jun '17

03 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20024 ) Change subject: superio/acpi: extend generic ACPI PnP device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10544/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54844/ : SUCCESS -- To view, visit https://review.coreboot.org/20024 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idad03f3881e0fbf2135562316d177972f931afec Gerrit-Change-Number: 20024 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Jun 2017 22:36:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/foxconn/g41s-k: add new mainboard
by Samuel Holland (Code Review) 03 Jun '17

03 Jun '17

Samuel Holland has uploaded this change for review. ( https://review.coreboot.org/20027 Change subject: mb/foxconn/g41s-k: add new mainboard ...................................................................... mb/foxconn/g41s-k: add new mainboard This mainboard is based on the Intel G41 chipset, ICH7 southbridge, and the IT8720F Super I/O. It has: * One DDR2 slot * One PCI-E x16 PEG slot, and one PCI-E x1 slot from the southbridge * Realtek ALC888 HD Audio * Realtek R8168 Gigabit LAN * COM header (SP1), IrDA header (SP2), CIR header, TPM header (no LPT) * Two SATA ports (no PATA) TODO: power management, test front panel audio and PS/2 Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- A src/mainboard/foxconn/Kconfig A src/mainboard/foxconn/Kconfig.name A src/mainboard/foxconn/g41s-k/Kconfig A src/mainboard/foxconn/g41s-k/Kconfig.name A src/mainboard/foxconn/g41s-k/Makefile.inc A src/mainboard/foxconn/g41s-k/acpi/ec.asl A src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl A src/mainboard/foxconn/g41s-k/acpi/platform.asl A src/mainboard/foxconn/g41s-k/acpi/superio.asl A src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl A src/mainboard/foxconn/g41s-k/acpi_tables.c A src/mainboard/foxconn/g41s-k/board_info.txt A src/mainboard/foxconn/g41s-k/cmos.default A src/mainboard/foxconn/g41s-k/cmos.layout A src/mainboard/foxconn/g41s-k/cstates.c A src/mainboard/foxconn/g41s-k/devicetree.cb A src/mainboard/foxconn/g41s-k/dsdt.asl A src/mainboard/foxconn/g41s-k/gpio.c A src/mainboard/foxconn/g41s-k/hda_verb.c A src/mainboard/foxconn/g41s-k/romstage.c 20 files changed, 982 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/20027/1 diff --git a/src/mainboard/foxconn/Kconfig b/src/mainboard/foxconn/Kconfig new file mode 100644 index 0000000..056805c --- /dev/null +++ b/src/mainboard/foxconn/Kconfig @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if VENDOR_FOXCONN + +choice + prompt "Mainboard model" + +source "src/mainboard/foxconn/*/Kconfig.name" + +endchoice + +source "src/mainboard/foxconn/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Foxconn" + +endif # VENDOR_FOXCONN diff --git a/src/mainboard/foxconn/Kconfig.name b/src/mainboard/foxconn/Kconfig.name new file mode 100644 index 0000000..2c3afd2 --- /dev/null +++ b/src/mainboard/foxconn/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_FOXCONN + bool "Foxconn" diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig new file mode 100644 index 0000000..8c8f259 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/Kconfig @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +## Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_FOXCONN_G41S_K + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_ITE_IT8720F + select BOARD_ROMSIZE_KB_1024 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_EDID + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_NATIVE_VGA_INIT + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE + select REALTEK_8168_RESET + +config MAINBOARD_DIR + string + default "foxconn/g41s-k" + +config MAINBOARD_PART_NUMBER + string + default "G41S-K" + +config MAX_CPUS + int + default 4 + +endif # BOARD_FOXCONN_G41S_K diff --git a/src/mainboard/foxconn/g41s-k/Kconfig.name b/src/mainboard/foxconn/g41s-k/Kconfig.name new file mode 100644 index 0000000..1c618e8 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_FOXCONN_G41S_K + bool "G41S-K" diff --git a/src/mainboard/foxconn/g41s-k/Makefile.inc b/src/mainboard/foxconn/g41s-k/Makefile.inc new file mode 100644 index 0000000..f3d7e76 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += cstates.c +romstage-y += gpio.c diff --git a/src/mainboard/foxconn/g41s-k/acpi/ec.asl b/src/mainboard/foxconn/g41s-k/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..9d10d81 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 0x10}, + Package() { 0x0000ffff, 1, 0, 0x11}, + Package() { 0x0000ffff, 2, 0, 0x12}, + Package() { 0x0000ffff, 3, 0, 0x13}, + + Package() { 0x0001ffff, 0, 0, 0x11}, + Package() { 0x0001ffff, 1, 0, 0x12}, + Package() { 0x0001ffff, 2, 0, 0x13}, + Package() { 0x0001ffff, 3, 0, 0x10}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + }) +} diff --git a/src/mainboard/foxconn/g41s-k/acpi/platform.asl b/src/mainboard/foxconn/g41s-k/acpi/platform.asl new file mode 100644 index 0000000..bda0df7 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/foxconn/g41s-k/acpi/superio.asl b/src/mainboard/foxconn/g41s-k/acpi/superio.asl new file mode 100644 index 0000000..3811c2f --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/superio.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8720F_SHOW_SP1 +#undef IT8720F_SHOW_SP2 +#undef IT8720F_SHOW_EC +#undef IT8720F_SHOW_KBCK +#undef IT8720F_SHOW_KBCM +#undef IT8720F_SHOW_GPIO +#undef IT8720F_SHOW_CIR +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8720F_SHOW_SP1 1 +#define IT8720F_SHOW_SP2 1 +#define IT8720F_SHOW_EC 1 +#define IT8720F_SHOW_KBCK 1 +#define IT8720F_SHOW_KBCM 1 +#define IT8720F_SHOW_GPIO 1 +#define IT8720F_SHOW_CIR 1 +#include <superio/ite/it8720f/acpi/superio.asl> diff --git a/src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000..8c8afcb --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* PEG 0:01.0 */ + Package() { 0x0001ffff, 0, 0, 0x10 }, + Package() { 0x0001ffff, 1, 0, 0x11 }, + Package() { 0x0001ffff, 2, 0, 0x12 }, + Package() { 0x0001ffff, 3, 0, 0x13 }, + /* Internal GFX 0:02.0 */ + Package() { 0x0002ffff, 0, 0, 0x10 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 0x10 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 0x10 }, + Package() { 0x001cffff, 1, 0, 0x11 }, + Package() { 0x001cffff, 2, 0, 0x12 }, + Package() { 0x001cffff, 3, 0, 0x13 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 0x17 }, + Package() { 0x001dffff, 1, 0, 0x13 }, + Package() { 0x001dffff, 2, 0, 0x12 }, + Package() { 0x001dffff, 3, 0, 0x10 }, + /* PCI Bridge 0x1e.0 */ + Package() { 0x001effff, 0, 0, 0x11 }, + Package() { 0x001effff, 1, 0, 0x14 }, + /* PATA/SATA/SMBUS 0:1f.x */ + Package() { 0x001fffff, 0, 0, 0x12 }, + Package() { 0x001fffff, 1, 0, 0x13 }, + }) + } Else { + Return (Package() { + /* PEG 0:01.0 */ + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* Internal GFX 0:02.0 */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCI Bridge 0x1e.0 */ + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + /* PATA/SATA/SMBUS 0:1f.x */ + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c new file mode 100644 index 0000000..d9935e9 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi_tables.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->cmap = 1; /* COM 1 port */ + gnvs->cmap = 1; /* COM 2 port */ + gnvs->lptp = 0; /* LPT port */ + gnvs->fdcp = 0; /* Floppy Disk Controller */ +} diff --git a/src/mainboard/foxconn/g41s-k/board_info.txt b/src/mainboard/foxconn/g41s-k/board_info.txt new file mode 100644 index 0000000..cad23bf --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us00004… +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2009 diff --git a/src/mainboard/foxconn/g41s-k/cmos.default b/src/mainboard/foxconn/g41s-k/cmos.default new file mode 100644 index 0000000..177af21 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +gfx_uma_size=64M diff --git a/src/mainboard/foxconn/g41s-k/cmos.layout b/src/mainboard/foxconn/g41s-k/cmos.layout new file mode 100644 index 0000000..c67cf73 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/cmos.layout @@ -0,0 +1,114 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: cpu +#424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#435 549 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +1024 144 r 0 recv_enable_results +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/foxconn/g41s-k/cstates.c b/src/mainboard/foxconn/g41s-k/cstates.c new file mode 100644 index 0000000..4568479 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/cstates.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb new file mode 100644 index 0000000..fae89e6 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -0,0 +1,188 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +## Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +## Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + subsystemid 0x105b 0x0dda inherit + device pci 0.0 on # Host Bridge + subsystemid 0x105b 0x0dda + end + device pci 1.0 on end # PEG + device pci 2.0 on # Integrated graphics controller + subsystemid 0x105b 0x0dda + end + device pci 2.1 off end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0a" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0a" + register "pirqd_routing" = "0x05" + register "pirqe_routing" = "0x0a" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0a" + register "pirqh_routing" = "0x03" + + register "gpe0_en" = "0x00000441" + register "alt_gp_smi_en" = "0x0000" + + register "ide_enable_primary" = "0x0" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" # AHCI does not work + register "sata_ports_implemented" = "0x3" + + device pci 1b.0 on # Audio + subsystemid 0x105b 0x0dda + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2 (NIC) + device pci 00.0 on # PCI 10ec:8168 + subsystemid 0x105b 0x0dda + end + end + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1d.0 on # USB + subsystemid 0x105b 0x0dda + end + device pci 1d.1 on # USB + subsystemid 0x105b 0x0dda + end + device pci 1d.2 on # USB + subsystemid 0x105b 0x0dda + end + device pci 1d.3 on # USB + subsystemid 0x105b 0x0dda + end + device pci 1d.7 on # USB + subsystemid 0x105b 0x0dda + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + subsystemid 0x105b 0x0dda + chip superio/ite/it8720f # Super I/O + register "TMPIN1" = "THERMAL_DIODE" + register "TMPIN2" = "THERMAL_RESISTOR" + register "TMPIN3" = "THERMAL_MODE_DISABLED" + + register "ec.vin_mask" = "VIN_ALL" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # System fan + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "25" + register "FAN1.smart.tmp_start" = "30" + register "FAN1.smart.tmp_full" = "65" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "10" + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # CPU fan + register "FAN2.smart.tmpin" = "1" + register "FAN2.smart.tmp_off" = "25" + register "FAN2.smart.tmp_start" = "30" + register "FAN2.smart.tmp_full" = "65" + register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.smoothing" = "1" + register "FAN2.smart.pwm_start" = "20" + register "FAN2.smart.slope" = "10" + register "FAN3.mode" = "FAN_MODE_OFF" # Not connected + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 0x04 + irq 0xf0 = 0x00 + irq 0xf1 = 0x50 + end + device pnp 2e.2 on # COM2 (IR) + io 0x60 = 0x2f8 + irq 0x70 = 0x03 + irq 0xf0 = 0x10 # IrDA SIR mode + irq 0xf1 = 0x50 + end + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment controller + io 0x60 = 0xa10 + io 0x62 = 0xa00 + irq 0x70 = 0x00 + irq 0xf0 = 0x80 + irq 0xf1 = 0x00 + irq 0xf2 = 0x0a + irq 0xf3 = 0x00 + irq 0xf4 = 0x80 + irq 0xf5 = 0x00 + irq 0xf6 = 0x00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + io 0x62 = 0x064 + irq 0x70 = 0x01 + irq 0xf0 = 0x00 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 0x0c + irq 0xf0 = 0x00 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x000 + io 0x62 = 0xa20 + io 0x64 = 0xa30 + irq 0xf0 = 0x00 + irq 0xf1 = 0x00 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0x22 + irq 0xf7 = 0x00 + irq 0xf8 = 0x00 + irq 0xf9 = 0x00 + irq 0xfa = 0x00 + irq 0xfb = 0x00 + irq 0xfd = 0x00 + irq 0xfe = 0x00 + end + device pnp 2e.a on # CIR + io 0x60 = 0x3e0 + irq 0x70 = 0x0a + irq 0xf0 = 0x00 + end + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on # SATA + subsystemid 0x105b 0x0dda + end + device pci 1f.3 on # SMbus + subsystemid 0x105b 0x0dda + end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl new file mode 100644 index 0000000..e11eb39 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801gx/i82801gx.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/foxconn/g41s-k/gpio.c b/src/mainboard/foxconn/g41s-k/gpio.c new file mode 100644 index 0000000..6162898 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/gpio.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/foxconn/g41s-k/hda_verb.c b/src/mainboard/foxconn/g41s-k/hda_verb.c new file mode 100644 index 0000000..45943b8 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/hda_verb.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, /* Vendor ID */ + 0x105b0dda, /* Subsystem ID */ + 0x0000000e, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x01441130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c new file mode 100644 index 0000000..389c153 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <northbridge/intel/x4x/iomap.h> +#include <northbridge/intel/x4x/x4x.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8720f/it8720f.h> +#include <lib.h> +#include <timestamp.h> + +#define LPC_DEV PCI_DEV(0, 0x1f, 0) +#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) + +static void mb_lpc_setup(void) +{ + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Setup GPIOs on Super IO. */ + ite_reg_write(GPIO_DEV, 0x25, 0x01); + ite_reg_write(GPIO_DEV, 0x26, 0x04); + ite_reg_write(GPIO_DEV, 0x27, 0x00); + ite_reg_write(GPIO_DEV, 0x28, 0x40); + ite_reg_write(GPIO_DEV, 0x29, 0x01); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0x74, 0x00); + ite_reg_write(GPIO_DEV, 0xb1, 0x04); + ite_reg_write(GPIO_DEV, 0xb8, 0x20); + ite_reg_write(GPIO_DEV, 0xbb, 0x01); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc3, 0x01); + ite_reg_write(GPIO_DEV, 0xcb, 0x01); + ite_reg_write(GPIO_DEV, 0xf5, 0x28); + ite_reg_write(GPIO_DEV, 0xf6, 0x12); + + /* IRQ routing */ + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x3241; + RCBA16(D29IR) = 0x0237; + + /* Enable IOAPIC */ + RCBA8(OIC) = 0x03; + RCBA8(OIC); + + RCBA32(GCS) |= (1 << 5); + RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | + FD_ACMOD | FD_ACAUD | FD_PATA | 1; + RCBA32(CG) = 0x00000001; +} + +static void ich7_enable_lpc(void) +{ + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | + COMB_LPC_EN | COMA_LPC_EN); + + /* Decode 64 bytes at 0x00a0 to LPC for EC and GPIO. */ + pci_write_config32(LPC_DEV, 0x84, 0x003c0a01); +} + +void mainboard_romstage_entry(unsigned long bist) +{ + // ch0 ch1 + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; + u8 s3_resume; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; + + /* Set southbridge and Super I/O GPIOs. */ + ich7_enable_lpc(); + mb_lpc_setup(); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); + +} -- To view, visit https://review.coreboot.org/20027 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda Gerrit-Change-Number: 20027 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org>

1 0

Change in coreboot[master]: superio/ite/it8720f: add new IT8720F Super I/O
by Samuel Holland (Code Review) 03 Jun '17

03 Jun '17

Samuel Holland has uploaded this change for review. ( https://review.coreboot.org/20026 Change subject: superio/ite/it8720f: add new IT8720F Super I/O ...................................................................... superio/ite/it8720f: add new IT8720F Super I/O This device is extremely similar to the IT8718F, so support is based on existing support for the IT8718F and the IT8783E/F (for ACPI). It will be used on Foxconn boards. The board using this chip does not have a floppy or parallel port, so those controllers are untested. All other interfaces appear to work. Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- M src/superio/ite/Makefile.inc M src/superio/ite/common/env_ctrl.c A src/superio/ite/it8720f/Kconfig A src/superio/ite/it8720f/Makefile.inc A src/superio/ite/it8720f/acpi/superio.asl A src/superio/ite/it8720f/chip.h A src/superio/ite/it8720f/it8720f.h A src/superio/ite/it8720f/superio.c 8 files changed, 409 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/20026/1 diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index fa3775a..f27a333 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -23,6 +23,7 @@ subdirs-y += it8712f subdirs-y += it8716f subdirs-y += it8718f +subdirs-y += it8720f subdirs-y += it8721f subdirs-y += it8728f subdirs-y += it8772f diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index b3312e6..1e313ce 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -98,7 +98,7 @@ * Set up External Temperature to read via thermal diode/resistor * into TMPINx register */ -static void enable_tmpin(const u16 base, const int tmpin, +static void enable_tmpin(const u16 base, const u8 tmpin, const enum ite_ec_thermal_mode mode) { u8 reg; diff --git a/src/superio/ite/it8720f/Kconfig b/src/superio/ite/it8720f/Kconfig new file mode 100644 index 0000000..00bb591 --- /dev/null +++ b/src/superio/ite/it8720f/Kconfig @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8720F + bool + select SUPERIO_ITE_COMMON_ROMSTAGE + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 diff --git a/src/superio/ite/it8720f/Makefile.inc b/src/superio/ite/it8720f/Makefile.inc new file mode 100644 index 0000000..f8459d7 --- /dev/null +++ b/src/superio/ite/it8720f/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8720F) += superio.c diff --git a/src/superio/ite/it8720f/acpi/superio.asl b/src/superio/ite/it8720f/acpi/superio.asl new file mode 100644 index 0000000..1e94655 --- /dev/null +++ b/src/superio/ite/it8720f/acpi/superio.asl @@ -0,0 +1,211 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013, 2016 secunet Security Networks AG + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the IT8720F SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x0 FDC Not implemented + * 0x1 SP1 Implemented, untested + * 0x2 SP2 Implemented, untested + * 0x3 PP Not implemented + * 0x4 EC Implemented, untested + * 0x5 KBCK Implemented, untested + * 0x6 KBCM Implemented, untested + * 0x7 GPIO Implemented, untested + * 0xa CIR Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * IT8720F_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * IT8720F_SHOW_SP2 If defined, Serial Port 2 will be exposed. + * IT8720F_SHOW_EC If defined, the Environment Controller will be exposed. + * IT8720F_SHOW_KBCK If defined, the Keyboard Controller will be exposed. + * IT8720F_SHOW_KBCM If defined, PS/2 mouse support will be exposed. + * IT8720F_SHOW_GPIO If defined, GPIO support will be exposed. + * IT8720F_SHOW_CIR If defined, Consumer IR support will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME IT8720F +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define CONFIGURE_CONTROL CCTL + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("ITE IT8720F Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + CONFIGURE_CONTROL, 8, /* Global configure control */ + + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x01 + #define PNP_ENTER_MAGIC_3RD 0x55 +#if SUPERIO_PNP_BASE == 0x2e + #define PNP_ENTER_MAGIC_4TH 0x55 +#else + #define PNP_ENTER_MAGIC_4TH 0xaa +#endif + #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL + #define PNP_EXIT_SPECIAL_VAL 0x02 + #include <superio/acpi/pnp_config.asl> + +#ifdef IT8720F_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef IT8720F_SHOW_SP2 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef IT8720F_SHOW_EC + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 4 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x04 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> +#endif + +#ifdef IT8720F_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 +#ifdef IT8720F_SHOW_PS2M + #define SUPERIO_KBC_PS2LDN 6 +#endif + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef IT8720F_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 7 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x08 + #define SUPERIO_PNP_IO2 0x08, 0x08 + #include <superio/acpi/pnp_generic.asl> +#endif + +#ifdef IT8720F_SHOW_CIR + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_HID "ITE8704" + #define SUPERIO_PNP_LDN 10 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> +#endif +} diff --git a/src/superio/ite/it8720f/chip.h b/src/superio/ite/it8720f/chip.h new file mode 100644 index 0000000..182bd48 --- /dev/null +++ b/src/superio/ite/it8720f/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8720F_CHIP_H +#define SUPERIO_ITE_IT8720F_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8720f_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8720F_CHIP_H */ diff --git a/src/superio/ite/it8720f/it8720f.h b/src/superio/ite/it8720f/it8720f.h new file mode 100644 index 0000000..55b2294 --- /dev/null +++ b/src/superio/ite/it8720f/it8720f.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8720F_H +#define SUPERIO_ITE_IT8720F_H + +/* Logical Device Numbers (LDN). */ +#define IT8720F_FDC 0x00 /* Floppy */ +#define IT8720F_SP1 0x01 /* Serial port 1 */ +#define IT8720F_SP2 0x02 /* Serial port 2 */ +#define IT8720F_PP 0x03 /* Parallel port */ +#define IT8720F_EC 0x04 /* Environment controller */ +#define IT8720F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8720F_KBCM 0x06 /* PS/2 mouse */ +#define IT8720F_GPIO 0x07 /* GPIO (including SPI flash interface) */ +#define IT8720F_CIR 0x0a /* Consumer IR */ + +#endif /* SUPERIO_ITE_IT8720F_H */ diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c new file mode 100644 index 0000000..74ffefa --- /dev/null +++ b/src/superio/ite/it8720f/superio.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2017 Samuel Holland <samuel(a)sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <superio/ite/common/env_ctrl.h> +#include <superio/conf_mode.h> + +#include "chip.h" +#include "it8720f.h" + +static void it8720f_init(struct device *dev) +{ + const struct superio_ite_it8720f_config *conf; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8720F_EC: + conf = dev->chip_info; + res = find_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8720F_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + default: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = it8720f_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, IT8720F_FDC, + PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1, + {0x0ff8, 0}, }, + { &ops, IT8720F_SP1, + PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1, + {0x0ff8, 0}, }, + { &ops, IT8720F_SP2, + PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1, + {0x0ff8, 0}, }, + { &ops, IT8720F_PP, + PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0, + {0x0ff8, 0}, {0x0ffc, 0}, }, + { &ops, IT8720F_EC, + PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | + PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6, + {0x0ff8, 0}, {0x0ffc, 0}, }, + { &ops, IT8720F_KBCK, + PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + {0x0fff, 0}, {0x0fff, 0}, }, + { &ops, IT8720F_KBCM, + PNP_IRQ0 | PNP_MSC0, }, + { &ops, IT8720F_GPIO, + PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | + PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 | + PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCD | PNP_MSCE, + {0x0ff8, 0}, {0x0ff8, 0}, {0x0ff8, 0}, }, + { &ops, IT8720F_CIR, + PNP_IO0 | PNP_IRQ0 | PNP_MSC0, + {0x0ff8, 0}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8720f_ops = { + CHIP_NAME("ITE IT8720F Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/20026 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a Gerrit-Change-Number: 20026 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org>

1 0

Change in coreboot[master]: superio/ite/it8728f: remove unused header
by Samuel Holland (Code Review) 03 Jun '17

03 Jun '17

Samuel Holland has uploaded this change for review. ( https://review.coreboot.org/20025 Change subject: superio/ite/it8728f: remove unused header ...................................................................... superio/ite/it8728f: remove unused header Change-Id: Ifcbf95ffd6d13cae4e6864e0320ce6ce1cf3ae4d Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- D src/superio/ite/it8728f/it8728f_internal.h M src/superio/ite/it8728f/superio.c 2 files changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/20025/1 diff --git a/src/superio/ite/it8728f/it8728f_internal.h b/src/superio/ite/it8728f/it8728f_internal.h deleted file mode 100644 index 6be8c5a..0000000 --- a/src/superio/ite/it8728f/it8728f_internal.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_ITE_IT8728F_INTERNAL_H -#define SUPERIO_ITE_IT8728F_INTERNAL_H - -#include <device/device.h> - -void it8728f_hwm_ec_init(struct device *dev); - -#endif /* SUPERIO_ITE_IT8728F_INTERNAL_H */ diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index b8c5b22..7f43880 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -25,7 +25,6 @@ #include "chip.h" #include "it8728f.h" -#include "it8728f_internal.h" static void it8728f_init(struct device *dev) { -- To view, visit https://review.coreboot.org/20025 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifcbf95ffd6d13cae4e6864e0320ce6ce1cf3ae4d Gerrit-Change-Number: 20025 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org>

1 0

Change in coreboot[master]: superio/acpi: extend generic ACPI PnP device
by Samuel Holland (Code Review) 03 Jun '17

03 Jun '17

Samuel Holland has uploaded this change for review. ( https://review.coreboot.org/20024 Change subject: superio/acpi: extend generic ACPI PnP device ...................................................................... superio/acpi: extend generic ACPI PnP device Some Super I/O PnP devices are detected by string matching the HID. Allow providing a custom HID to override the default generic one. Some Super I/O logical devices have three I/O port ranges, such as the GPIO on the IT8720F. Allow specifying a third I/O range. While here, fix a typo in the I/O range description. Change-Id: Idad03f3881e0fbf2135562316d177972f931afec Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- M src/superio/acpi/pnp.asl M src/superio/acpi/pnp_generic.asl 2 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/20024/1 diff --git a/src/superio/acpi/pnp.asl b/src/superio/acpi/pnp.asl index b00e490..114dfe9 100644 --- a/src/superio/acpi/pnp.asl +++ b/src/superio/acpi/pnp.asl @@ -34,6 +34,8 @@ #define PNP_IO0_LOW_BYTE IO0L #define PNP_IO1_HIGH_BYTE IO1H #define PNP_IO1_LOW_BYTE IO1L +#define PNP_IO2_HIGH_BYTE IO2H +#define PNP_IO2_LOW_BYTE IO2L #define PNP_IRQ0 IRQ0 #define PNP_IRQ1 IRQ1 #define PNP_DMA0 DMA0 diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index 8f8d137..c878827 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -21,6 +21,7 @@ * Controlled by the following preprocessor defines: * * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_PNP_HID The EisaId string that identifies this device (optional) * SUPERIO_PNP_LDN The logical device number on the super i/o * chip for this device (required) * SUPERIO_PNP_DDN A string literal that identifies the dos device @@ -32,10 +33,13 @@ * SUPERIO_PNP_PM_LDN The logical device number to access the PM_REG * bit (required if SUPERIO_PNP_PM_REG is defined) * SUPERIO_PNP_IO0 The alignment and length of the first PnP i/o - * resource (comma seperated, e.g. `0x02, 0x08`, + * resource (comma separated, e.g. `0x02, 0x08`, * optional) * SUPERIO_PNP_IO1 The alignment and length of the second PnP i/o - * resource (comma seperated, e.g. `0x02, 0x08`, + * resource (comma separated, e.g. `0x02, 0x08`, + * optional) + * SUPERIO_PNP_IO2 The alignment and length of the third PnP i/o + * resource (comma separated, e.g. `0x02, 0x08`, * optional) * SUPERIO_PNP_IRQ0 If defined, the first PnP IRQ register is enabled * SUPERIO_PNP_IRQ1 If defined, the second PnP IRQ register is enabled @@ -53,7 +57,11 @@ #endif Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) { + #ifdef SUPERIO_PNP_HID + Name (_HID, EisaId (SUPERIO_PNP_HID)) + #else Name (_HID, EisaId ("PNP0c02")) /* TODO: Better fitting EisaId? */ + #endif Name (_UID, SUPERIO_UID(PN, SUPERIO_PNP_LDN)) #ifdef SUPERIO_PNP_DDN Name (_DDN, SUPERIO_PNP_DDN) @@ -96,6 +104,9 @@ #ifdef SUPERIO_PNP_IO1 IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1) #endif +#ifdef SUPERIO_PNP_IO2 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO2, IO2) +#endif #ifdef SUPERIO_PNP_IRQ0 IRQNoFlags (IR0) {} #endif @@ -112,6 +123,9 @@ #endif #ifdef SUPERIO_PNP_IO1 PNP_READ_IO(PNP_IO1, CRS, IO1) +#endif +#ifdef SUPERIO_PNP_IO2 + PNP_READ_IO(PNP_IO2, CRS, IO2) #endif #ifdef SUPERIO_PNP_IRQ0 PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) @@ -135,6 +149,9 @@ #ifdef SUPERIO_PNP_IO1 IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1) #endif +#ifdef SUPERIO_PNP_IO2 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO2, IO2) +#endif #ifdef SUPERIO_PNP_IRQ0 IRQNoFlags (IR0) {} #endif @@ -152,6 +169,9 @@ #ifdef SUPERIO_PNP_IO1 PNP_WRITE_IO(PNP_IO1, Arg0, IO1) #endif +#ifdef SUPERIO_PNP_IO2 + PNP_WRITE_IO(PNP_IO2, Arg0, IO2) +#endif #ifdef SUPERIO_PNP_IRQ0 PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) #endif -- To view, visit https://review.coreboot.org/20024 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idad03f3881e0fbf2135562316d177972f931afec Gerrit-Change-Number: 20024 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org>

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Change in coreboot[master]: mb/google/poppy: Update camera sensor
by build bot (Jenkins) (Code Review) 03 Jun '17

03 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20021 ) Change subject: mb/google/poppy: Update camera sensor ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54843/ : SUCCESS -- To view, visit https://review.coreboot.org/20021 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35 Gerrit-Change-Number: 20021 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Jun 2017 20:07:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/soraka: Update UF camera i2c address
by build bot (Jenkins) (Code Review) 03 Jun '17

03 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20023 ) Change subject: mb/google/soraka: Update UF camera i2c address ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10543/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54842/ : SUCCESS -- To view, visit https://review.coreboot.org/20023 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b Gerrit-Change-Number: 20023 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Jun 2017 20:02:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Update camera sensor
by build bot (Jenkins) (Code Review) 03 Jun '17

03 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20021 ) Change subject: mb/google/poppy: Update camera sensor ...................................................................... Patch Set 6: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54841/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/10542/ : SUCCESS -- To view, visit https://review.coreboot.org/20021 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35 Gerrit-Change-Number: 20021 Gerrit-PatchSet: 6 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Jun 2017 19:57:42 +0000 Gerrit-HasComments: No

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