coreboot-gerrit June 2017

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Change in coreboot[master]: util/lint: Add check to make sure 'coreboot' is lowercase
by build bot (Jenkins) (Code Review) 04 Jun '17

04 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20032 ) Change subject: util/lint: Add check to make sure 'coreboot' is lowercase ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10552/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54852/ : SUCCESS -- To view, visit https://review.coreboot.org/20032 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b52342488dacc56ef6083db5503507af35d41ac Gerrit-Change-Number: 20032 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Jun 2017 03:36:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: payloads: change coreboot to lowercase
by build bot (Jenkins) (Code Review) 04 Jun '17

04 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20028 ) Change subject: payloads: change coreboot to lowercase ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10548/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54848/ : SUCCESS -- To view, visit https://review.coreboot.org/20028 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd Gerrit-Change-Number: 20028 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Jun 2017 03:32:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/lint: Add check to make sure 'coreboot' is lowercase
by Martin Roth (Code Review) 04 Jun '17

04 Jun '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/20032 ) Change subject: util/lint: Add check to make sure 'coreboot' is lowercase ...................................................................... Patch Set 1: Inspired by https://github.com/osresearch/heads/issues/71 -- To view, visit https://review.coreboot.org/20032 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b52342488dacc56ef6083db5503507af35d41ac Gerrit-Change-Number: 20032 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sun, 04 Jun 2017 03:30:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/lint: Add check to make sure 'coreboot' is lowercase
by Martin Roth (Code Review) 04 Jun '17

04 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20032 Change subject: util/lint: Add check to make sure 'coreboot' is lowercase ...................................................................... util/lint: Add check to make sure 'coreboot' is lowercase - Excludes certain phrases which can't be changed. - Checks last commit message if code is in a repo. Change-Id: I6b52342488dacc56ef6083db5503507af35d41ac Signed-off-by: Martin Roth <martinroth(a)google.com> --- A util/lint/lint-stable-021-coreboot-lowercase 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/20032/1 diff --git a/util/lint/lint-stable-021-coreboot-lowercase b/util/lint/lint-stable-021-coreboot-lowercase new file mode 100755 index 0000000..0df70b8 --- /dev/null +++ b/util/lint/lint-stable-021-coreboot-lowercase @@ -0,0 +1,33 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: Verify that the word 'coreboot' is lowercase + +LC_ALL=C export LC_ALL + +EXCLUDE='^3rdparty/\|util/crossgcc/xgcc\|Binary file\|coreboot\|COREBOOT\|CorebootPayload\|CorebootModule\|minnowboard.org/…' + +# Use git grep if the code is in a git repo, otherwise use grep. +if [ -n "$(command -v git)" ] && [ -d .git ]; then + GREP_FILES="git grep -in" + + # Check last commit message + if [ -n "$(git log -n 1 | grep -i 'coreboot' | grep -v "$EXCLUDE" )" ]; then + echo "'coreboot' should be lowercase in commit message" + fi +else + GREP_FILES="grep -rin" +fi + +${GREP_FILES} "coreboot" | grep -v "$EXCLUDE"; -- To view, visit https://review.coreboot.org/20032 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6b52342488dacc56ef6083db5503507af35d41ac Gerrit-Change-Number: 20032 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: util: change coreboot to lowercase
by Martin Roth (Code Review) 04 Jun '17

04 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20030 Change subject: util: change coreboot to lowercase ...................................................................... util: change coreboot to lowercase The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I0a024d82d331c0794fe087e440b4e1924129a13c Signed-off-by: Martin Roth <martinroth(a)google.com> --- M util/cbfstool/cbfs-mkstage.c M util/hugo/config.toml M util/nvramtool/cmos_ops.c M util/nvramtool/lbtable.c M util/optionlist/README M util/optionlist/kconfig2wiki 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/20030/1 diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 53d3edb..85c3e4f 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -313,7 +313,7 @@ outheader.data = output->data; outheader.size = 0; - /* Coreboot expects entry point to be physical address. Thus, adjust the + /* coreboot expects entry point to be physical address. Thus, adjust the * entry point accordingly. */ fill_cbfs_stage(&outheader, algo, ehdr->e_entry + virt_to_phys, diff --git a/util/hugo/config.toml b/util/hugo/config.toml index d29a20d..e58c4b3 100644 --- a/util/hugo/config.toml +++ b/util/hugo/config.toml @@ -6,7 +6,7 @@ canonifyurls = true [params] - provider = "Coreboot" + provider = "coreboot" repo_url = "https://review.coreboot.org/cgit/coreboot.git" logo = "images/coreboot.svg" favicon = "images/favicon.png" diff --git a/util/nvramtool/cmos_ops.c b/util/nvramtool/cmos_ops.c index 6f616a0..969586c 100644 --- a/util/nvramtool/cmos_ops.c +++ b/util/nvramtool/cmos_ops.c @@ -227,7 +227,7 @@ set_iopl(0); if (computed != actual) { - fprintf(stderr, "%s: Warning: Coreboot CMOS checksum is bad.\n", + fprintf(stderr, "%s: Warning: coreboot CMOS checksum is bad.\n", prog_name); fprintf(stderr, "Computed checksum: 0x%x. Stored checksum: 0x%x\n", computed, actual); diff --git a/util/nvramtool/lbtable.c b/util/nvramtool/lbtable.c index 5db61c5..81ac203 100644 --- a/util/nvramtool/lbtable.c +++ b/util/nvramtool/lbtable.c @@ -325,7 +325,7 @@ const struct lb_record *lbrec; p = ((const char *)lbtable) + lbtable->header_bytes; - printf("Coreboot table at physical address 0x%lx:\n" + printf("coreboot table at physical address 0x%lx:\n" " signature: 0x%x (ASCII: %c%c%c%c)\n" " header_bytes: 0x%x (decimal: %d)\n" " header_checksum: 0x%x (decimal: %d)\n" diff --git a/util/optionlist/README b/util/optionlist/README index 616633a..d55546d 100644 --- a/util/optionlist/README +++ b/util/optionlist/README @@ -1 +1 @@ -This script creates the page http://www.coreboot.org/Coreboot_Options +This script creates the page http://www.coreboot.org/coreboot_Options diff --git a/util/optionlist/kconfig2wiki b/util/optionlist/kconfig2wiki index a587a9c..9c4ee7c 100755 --- a/util/optionlist/kconfig2wiki +++ b/util/optionlist/kconfig2wiki @@ -1,7 +1,7 @@ #!/usr/bin/env python # # kconfig2wiki - Kconfig to MediaWiki converter for -# http://www.coreboot.org/Coreboot_Options +# http://www.coreboot.org/coreboot_Options # # Copyright (C) 2010 coresystems GmbH # based on http://landley.net/kdocs/make/menuconfig2html.py -- To view, visit https://review.coreboot.org/20030 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0a024d82d331c0794fe087e440b4e1924129a13c Gerrit-Change-Number: 20030 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: Documentation: change coreboot to lowercase
by Martin Roth (Code Review) 04 Jun '17

04 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20031 Change subject: Documentation: change coreboot to lowercase ...................................................................... Documentation: change coreboot to lowercase The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Unfortunately, some external websites and projects are spelling coreboot with an uppercase C, so references to those pages can't be changed without breaking the link. Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f Signed-off-by: Martin Roth <martinroth(a)google.com> --- M Documentation/AMD-S3.txt M Documentation/Intel/SoC/soc.html M Documentation/Makefile M Documentation/acpi/gpio.md M Documentation/cbfs.txt R Documentation/corebootBuildingGuide.tex 6 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/20031/1 diff --git a/Documentation/AMD-S3.txt b/Documentation/AMD-S3.txt index 48d4c8f..bfabcbe 100644 --- a/Documentation/AMD-S3.txt +++ b/Documentation/AMD-S3.txt @@ -13,7 +13,7 @@ /_/ \_\_| |_|_____/ |_____/ |____/ - S3 in Coreboot (V 1.2) + S3 in coreboot (V 1.2) ---------------------------------------- Zheng Bao <zheng.bao(a)amd.com> @@ -78,7 +78,7 @@ Here is the address Map for S3 Resume. Assumingly the total memory is 1GB. 00000000 --- 00100000 BIOS Reserved area. 00100000 --- 00200000 Free -00200000 --- 01000000 Coreboot ramstage area. +00200000 --- 01000000 coreboot ramstage area. 01000000 --- 2e160000 Free 2e160000 --- 2e170000 ACPI table 2e170000 --- 2ef70000 OSRAM @@ -99,7 +99,7 @@ Provided by Southbridge vendor code. Early is called before PCI enumeration, and Late is called after that. -Lifecycle of booting, sleeping and waking Coreboot and Ubuntu +Lifecycle of booting, sleeping and waking coreboot and Ubuntu ============================================================= 1. Cold boot. For a system with S3 feature, the BIOS needs to save some data to @@ -130,7 +130,7 @@ As we mentioned, Firmware detects the SLP_TYPx to find out if the board wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called as they are during cold boot. AmdInitResume and AmdS3LateRestore are -called only during resume. For whole ramstage, Coreboot goes through +called only during resume. For whole ramstage, coreboot goes through almost the same way as cold boot, other than not calling the AmdInitMid, AmdInitLate and AmdS3Save, and restoring all the MTRRs. At last step of coreboot stage, coreboot finds out the wakeup vector in FADT, @@ -141,13 +141,13 @@ hooks. If we are more lucky, all the scripts can go through. More chances that the 99video hangs or fails to get the display back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in -Coreboot/Kconfig. That needs more troubleshooting. +coreboot/Kconfig. That needs more troubleshooting. Reference ========= [1] ACPI40a, http://www.acpi.info/spec40a.htm -[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ -[3] Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c -[4] Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c -[5] Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c +[2] coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ +[3] coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c +[4] coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c +[5] coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 8f1d75c..1b49683 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -588,7 +588,7 @@ </p> <table border="1"> <tr bgcolor="#c0ffc0"> - <td>Coreboot Field</td> + <td>coreboot Field</td> <td>EDK2 Field</td> <td>gUefiAcpiBoardInfoGuid</td> <td>Use</li> diff --git a/Documentation/Makefile b/Documentation/Makefile index 96b66a9..ecfbdb4 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -7,7 +7,7 @@ FIGS=codeflow.pdf hypertransport.pdf -all: CorebootPortingGuide.pdf Kconfig.pdf +all: corebootPortingGuide.pdf Kconfig.pdf SVG2PDF=$(shell which svg2pdf) INKSCAPE=$(shell which inkscape) @@ -31,13 +31,13 @@ convert $< $@ endif -CorebootPortingGuide.toc: $(FIGS) CorebootBuildingGuide.tex +corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex # 2 times to make sure we have a current toc. - $(PDFLATEX) CorebootBuildingGuide.tex - $(PDFLATEX) CorebootBuildingGuide.tex + $(PDFLATEX) corebootBuildingGuide.tex + $(PDFLATEX) corebootBuildingGuide.tex -CorebootPortingGuide.pdf: $(FIGS) CorebootBuildingGuide.tex CorebootPortingGuide.toc - $(PDFLATEX) CorebootBuildingGuide.tex +corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc + $(PDFLATEX) corebootBuildingGuide.tex Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex $(PDFLATEX) $< @@ -67,4 +67,4 @@ rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex distclean: clean - rm -f CorebootPortingGuide.pdf Kconfig.pdf + rm -f corebootPortingGuide.pdf Kconfig.pdf diff --git a/Documentation/acpi/gpio.md b/Documentation/acpi/gpio.md index 2fb2d1d..344e2ee 100644 --- a/Documentation/acpi/gpio.md +++ b/Documentation/acpi/gpio.md @@ -157,7 +157,7 @@ These are reference implementations and the platforms are free to -implement these functions in any way they like. Coreboot driver can +implement these functions in any way they like. coreboot driver can then simply call into these functions to generate ACPI AML code to get/set/clear any GPIO. In order to decide whether GPIO operations are required, driver code can rely either on some config option or read diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt index 7ecc901..a190da1 100644 --- a/Documentation/cbfs.txt +++ b/Documentation/cbfs.txt @@ -19,7 +19,7 @@ that it remains true to the original idea. Below is the beginnings of an architecture document - I did it in text form, but if met with aclaim, it should be wikified. This presents what I call CBFS - the -next generation LAR for next generation Coreboot. Its easier to +next generation LAR for next generation coreboot. Its easier to describe what it is by describing what changed: A header has been added somewhere in the bootblock similar to Carl @@ -73,7 +73,7 @@ Jordan -Coreboot CBFS Specification +coreboot CBFS Specification Jordan Crouse <jordan(a)cosmicpenguin.net> = Introduction = @@ -163,7 +163,7 @@ 'version' is a version number for CBFS header. cbfs_header structure may be different if version is not matched. -'romsize' is the size of the ROM in bytes. Coreboot will subtract 'size' from +'romsize' is the size of the ROM in bytes. coreboot will subtract 'size' from 0xFFFFFFFF to locate the beginning of the ROM in memory. 'bootblocksize' is the size of bootblock reserved in firmware image. diff --git a/Documentation/CorebootBuildingGuide.tex b/Documentation/corebootBuildingGuide.tex similarity index 98% rename from Documentation/CorebootBuildingGuide.tex rename to Documentation/corebootBuildingGuide.tex index eb4dfd2..7e68375 100644 --- a/Documentation/CorebootBuildingGuide.tex +++ b/Documentation/corebootBuildingGuide.tex @@ -23,7 +23,7 @@ colorlinks=false, % pdfpagemode=None, % PDF-Viewer starts without TOC % pdfstartview=FitH, - pdftitle={Coreboot Porting Guide}, + pdftitle={coreboot Porting Guide}, pdfauthor={Zheng Bao}, pdfsubject={coreboot configuration and build process}, pdfkeywords={coreboot, AMD, configuration, Build} @@ -32,7 +32,7 @@ \setlength{\parindent}{0pt} \setlength{\hoffset}{0pt} -\title{Coreboot from Scratch} +\title{coreboot from Scratch} \author{Stefan Reinauer $<$stepan(a)coresystems.de$>$\and Zheng Bao $<$zheng.bao(a)amd.com$>$} \date{Dec 4th, 2013} @@ -46,7 +46,7 @@ \newpage -\section{What is Coreboot} +\section{What is coreboot} coreboot aims to replace the normal BIOS found on x86, AMD64, PPC, Alpha, and other machines with a Linux kernel that can boot Linux from a cold start. The startup code of an average coreboot port is about 500 lines of @@ -60,7 +60,7 @@ Systems can be booted with coreboot, including embedded systems, Desktop PCs and Servers. -This document is used to build, modify, and port the CoreBoot code +This document is used to build, modify, and port the coreboot code base on the AMD platform. @@ -108,10 +108,10 @@ \end{itemize} % -% Getting Coreboot +% Getting coreboot % -\section{Getting Coreboot} +\section{Getting coreboot} The latest coreboot sources are available via GIT. For users who doesn't need to change and commit the code: { \small @@ -140,8 +140,8 @@ % \section{Building the toolchain} -Coreboot recommends and guarantees the toolchain integrated with Coreboot. -Linux distributions usually modify their compilers in ways incompatible with Coreboot. +coreboot recommends and guarantees the toolchain integrated with coreboot. +Linux distributions usually modify their compilers in ways incompatible with coreboot. { \small \begin{verbatim} @@ -236,11 +236,11 @@ If you are lucky, you can get toolchains located in util/crossgcc/xgcc. % -% Build Coreboot +% Build coreboot % -\section{Building Coreboot} -\subsection{Build main module of Coreboot} +\section{Building coreboot} +\subsection{Build main module of coreboot} { \small \begin{verbatim} $ cd coreboot -- To view, visit https://review.coreboot.org/20031 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f Gerrit-Change-Number: 20031 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: src: change coreboot to lowercase
by Martin Roth (Code Review) 04 Jun '17

04 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20029 Change subject: src: change coreboot to lowercase ...................................................................... src: change coreboot to lowercase The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/arch/riscv/sbi.S M src/arch/riscv/trap_handler.c M src/cpu/amd/car/cache_as_ram.inc M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/quadcore/quadcore_id.c M src/drivers/aspeed/common/ast_dp501.c M src/drivers/aspeed/common/ast_dram_tables.h M src/drivers/intel/fsp1_1/cache_as_ram.inc M src/drivers/intel/fsp1_1/raminit.c M src/drivers/xgi/common/XGI_main.h M src/drivers/xgi/common/vb_init.c M src/drivers/xgi/common/vb_setmode.c M src/drivers/xgi/common/vb_util.c M src/ec/quanta/ene_kb3940q/acpi/ec.asl M src/include/console/post_codes.h M src/include/memrange.h M src/include/types.h M src/lib/selfboot.c M src/mainboard/amd/inagua/broadcom.c M src/mainboard/pcengines/alix2d/romstage.c M src/northbridge/via/vx900/early_vx900.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/nvs.h M src/soc/samsung/exynos5250/alternate_cbfs.c M src/soc/samsung/exynos5420/alternate_cbfs.c M src/soc/samsung/exynos5420/smp.c M src/southbridge/intel/common/firmware/Makefile.inc M src/vendorcode/amd/cimx/sb700/SBCMN.c M src/vendorcode/amd/cimx/sb700/SBPort.c 35 files changed, 37 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/20029/1 diff --git a/src/arch/riscv/sbi.S b/src/arch/riscv/sbi.S index 0ff7c3b..608afc3 100644 --- a/src/arch/riscv/sbi.S +++ b/src/arch/riscv/sbi.S @@ -58,7 +58,7 @@ .align 4 /* -1984: int sbi_console_getchar(void); */ - li a0, -1 /* failure: Coreboot doesn't support console input */ + li a0, -1 /* failure: coreboot doesn't support console input */ jr ra .align 4 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 4dd3d5b..ca4954f 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -180,7 +180,7 @@ break; default: printk(BIOS_EMERG, "======================================\n"); - printk(BIOS_EMERG, "Coreboot: Unknown machine interrupt: 0x%llx\n", + printk(BIOS_EMERG, "coreboot: Unknown machine interrupt: 0x%llx\n", cause); printk(BIOS_EMERG, "======================================\n"); print_trap_information(tf); @@ -222,7 +222,7 @@ break; default: printk(BIOS_EMERG, "================================\n"); - printk(BIOS_EMERG, "Coreboot: can not handle a trap:\n"); + printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); printk(BIOS_EMERG, "================================\n"); print_trap_information(tf); break; diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 5305603..47031a6 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -45,7 +45,7 @@ * xmm2: Fam10h comparison value * xmm3: Fam15h comparison value * xmm4: Backup EBX - * xmm5: Coreboot init detect + * xmm5: coreboot init detect */ /* Save the BIST result. */ diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 8fe708c..1262718 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -60,7 +60,7 @@ by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required if the warm reset is issued by coreboot to update NbFid. So it is required or not ? How can I tell who issued warm reset ? - Coreboot transitions to P0 instead, which is not recommended, and does + coreboot transitions to P0 instead, which is not recommended, and does not follow 2.4.2.15.2 to do so. 9.- TODO Requires information on current delivery capability diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index cd83906..9892c12 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -105,7 +105,7 @@ } } if (fam15h && dual_node) { - /* Coreboot expects each separate processor die to be on a different nodeid. + /* coreboot expects each separate processor die to be on a different nodeid. * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed... */ uint32_t f5x84; @@ -123,7 +123,7 @@ id.coreid = id.coreid - core_count; } } else if (rev_gte_d && dual_node) { - /* Coreboot expects each separate processor die to be on a different nodeid. + /* coreboot expects each separate processor die to be on a different nodeid. * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed... */ uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | ((f3xe8 & 0x00003000) >> 12)) + 1; diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c index 448899e..46b76f5 100644 --- a/src/drivers/aspeed/common/ast_dp501.c +++ b/src/drivers/aspeed/common/ast_dp501.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * File taken from the Linux ast driver (v3.18.5) - * Coreboot-specific includes added at top and/or contents modified + * coreboot-specific includes added at top and/or contents modified * as needed to function within the coreboot environment. * * This program is free software; you can redistribute it and/or modify diff --git a/src/drivers/aspeed/common/ast_dram_tables.h b/src/drivers/aspeed/common/ast_dram_tables.h index fbef1e9..1d46ca6 100644 --- a/src/drivers/aspeed/common/ast_dram_tables.h +++ b/src/drivers/aspeed/common/ast_dram_tables.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * File taken from the Linux ast driver (v3.18.5) - * Coreboot-specific includes added at top and/or contents modified + * coreboot-specific includes added at top and/or contents modified * as needed to function within the coreboot environment. * * This program is free software; you can redistribute it and/or modify diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6611fa1..fc66208 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -137,7 +137,7 @@ /* Save FSP_INFO_HEADER location in ebx */ mov %ebp, %ebx - /* Coreboot assumes stack/heap region will be zero */ + /* coreboot assumes stack/heap region will be zero */ cld movl %ecx, %edi neg %ecx diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 6e2efcf..5b6ec9e 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -277,7 +277,7 @@ /* Verify the FSP 1.1 HOB interface */ if (fsp_verification_failure) - die("ERROR - Coreboot's requirements not met by FSP binary!\n"); + die("ERROR - coreboot's requirements not met by FSP binary!\n"); /* Display the memory configuration */ report_memory_config(); diff --git a/src/drivers/xgi/common/XGI_main.h b/src/drivers/xgi/common/XGI_main.h index 39d7ec8..52421e9 100644 --- a/src/drivers/xgi/common/XGI_main.h +++ b/src/drivers/xgi/common/XGI_main.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * File taken from the Linux xgifb driver (v3.18.5) - * Coreboot-specific includes added at top + * coreboot-specific includes added at top * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index 4070e4e..bc66bda 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -4,7 +4,7 @@ * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * File taken from the Linux xgifb driver (v3.18.5) - * Coreboot-specific includes added at top + * coreboot-specific includes added at top * XGINew_SetDRAMSize_340 slightly modified for coreboot text mode * * This program is free software; you can redistribute it and/or modify diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c index 0143076..1678b75 100644 --- a/src/drivers/xgi/common/vb_setmode.c +++ b/src/drivers/xgi/common/vb_setmode.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * File taken from the Linux xgifb driver (v3.18.5) - * Coreboot-specific includes added at top + * coreboot-specific includes added at top * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/xgi/common/vb_util.c b/src/drivers/xgi/common/vb_util.c index 19c29a1..f71ad56 100644 --- a/src/drivers/xgi/common/vb_util.c +++ b/src/drivers/xgi/common/vb_util.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * File taken from the Linux xgifb driver (v3.18.5) - * Coreboot-specific includes added at top + * coreboot-specific includes added at top * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 251b450..70f1366 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -63,7 +63,7 @@ BTBD, 1, // Battery Malfunction ; 70h.3 ACMD, 1, // ACPI Mode ; 70h.4 , 1, // Reserved ; 70h.5 - SSBS, 1, // 1=Standard BIOS, 0=Coreboot ; 70h.6 + SSBS, 1, // 1=Standard BIOS, 0=coreboot ; 70h.6 PSTH, 1, // Passive Thermal Policy ; 70h.7 BST0, 8, // Battery Status ; 71h // Bit0 : Discharging diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index f08796c..1368aa8 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -329,7 +329,7 @@ /** * \brief Elfload fail or die() called * - * Coreboot was not able to load the payload, no payload was detected + * coreboot was not able to load the payload, no payload was detected * or die() was called. * \n * If this code appears before entering ramstage, then most likely diff --git a/src/include/memrange.h b/src/include/memrange.h index bf6b8e4..46a992a 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -21,7 +21,7 @@ * is exposed so that a memranges can be used on the stack if needed. */ struct memranges { struct range_entry *entries; - /* Coreboot doesn't have a free() function. Therefore, keep a cache of + /* coreboot doesn't have a free() function. Therefore, keep a cache of * free'd entries. */ struct range_entry *free_list; }; diff --git a/src/include/types.h b/src/include/types.h index a4d8224..df09473 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -26,7 +26,7 @@ #define BIT(x) (1ul << (x)) /** - * Coreboot error codes + * coreboot error codes * * When building functions that return a status or an error code, use cb_err as * the return type. When failure reason needs to be communicated by the return diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index ef1b986..160e8f5 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -73,7 +73,7 @@ * * Benefits: * - Nearly arbitrary standalone executables can be loaded. - * - Coreboot is preserved, so it can be returned to. + * - coreboot is preserved, so it can be returned to. * - The implementation is still relatively simple, * and much simpler than the general case implemented in kexec. */ diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c index 640f639..9f140a2 100644 --- a/src/mainboard/amd/inagua/broadcom.c +++ b/src/mainboard/amd/inagua/broadcom.c @@ -26,7 +26,7 @@ #include <types.h> #include <console/console.h> -#include <device/device.h> //Coreboot device access +#include <device/device.h> //coreboot device access #include <device/pci.h> #include <delay.h> #include <endian.h> diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index ab96dd2..c7bf9ef 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -105,7 +105,7 @@ * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it * may be used here, but not after PCI Init. * Note: Prior to a certain release, Linux used a hardwired 0x6100 in the - * leds-alix2.c driver. Coreboot dynamically assigns this space, + * leds-alix2.c driver. coreboot dynamically assigns this space, * so the driver does not work anymore. * Good workaround: use the newer driver * Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100 diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index b350ffd..54a30af 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -102,7 +102,7 @@ * \brief Disables 'shadowing' of system ROM * * Disable unnecessary shadowing of the ROM in the first 1MB of address space. - * Coreboot runs in 32-bit mode from the start. Shadowing only gets in the way. + * coreboot runs in 32-bit mode from the start. Shadowing only gets in the way. * This function frees the entire 640k-1M range for DRAM. VGA may still use * the 640k-768k range, if enabled later. */ diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index bdba305..1548c30 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -33,7 +33,7 @@ LIDS, 8, // 0x02 - LID State PWRS, 8, // 0x03 - AC Power State DPTE, 8, // 0x04 - Enable DPTF - CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console + CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index GPEI, 64, // 0x11 - 0x18 - GPE Wake Source NHLA, 64, // 0x19 - 0x20 - NHLT Address diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index f9cc49d..e0b223f 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -33,7 +33,7 @@ uint8_t lids; /* 0x02 - LID State */ uint8_t pwrs; /* 0x03 - AC Power State */ uint8_t dpte; /* 0x04 - Enable DPTF */ - uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */ + uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index fcc80d4..b3b3a4f 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -55,7 +55,7 @@ LIDS, 8, // 0x16 - LID State PWRS, 8, // 0x17 - AC Power State CMEM, 32, // 0x18 - 0x1b - CBMEM TOC - CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console + CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 202c56a..55d6c8b 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -46,7 +46,7 @@ u8 lids; /* 0x16 - LID State */ u8 pwrs; /* 0x17 - AC Power State */ u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ - u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */ + u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ u8 unused[208]; diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index ab3c63c..d06269f 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -57,7 +57,7 @@ LIDS, 8, // 0x16 - LID State PWRS, 8, // 0x17 - AC Power State CMEM, 32, // 0x18 - 0x1b - CBMEM TOC - CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console + CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit DPTE, 8, // 0x30 - Enable DPTF diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 61975c6..ab06948 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -182,7 +182,7 @@ * To disable Heci, the Psf needs to be left unlocked * by FSP after end of post sequence. Based on the devicetree * setting, we set the appropriate PsfUnlock policy in Fsp, - * do the changes and then lock it back in Coreboot + * do the changes and then lock it back in coreboot * */ if (config->HeciEnabled == 0) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0572413..45dea06 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -226,7 +226,7 @@ if (conf->speed_shift_enable) { /* * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - is supported or not. Coreboot needs to configure MSR 0x1AA + is supported or not. coreboot needs to configure MSR 0x1AA which is then reflected in the CPUID register. */ msr = rdmsr(MSR_MISC_PWR_MGMT); diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index cb3b2c6..f72616f 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -47,7 +47,7 @@ u8 lids; /* 0x16 - LID State */ u8 pwrs; /* 0x17 - AC Power State */ u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ - u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */ + u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ u8 dpte; /* 0x30 - Enable DPTF */ diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index a3431e2..0687d47 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -26,7 +26,7 @@ #include <symbols.h> /* This allows USB A-A firmware upload from a compatible host in four parts: - * The first two are the bare BL1 and the Coreboot boot block, which are just + * The first two are the bare BL1 and the coreboot boot block, which are just * written to their respective loading addresses. These transfers are initiated * by the IROM / BL1, so this code has nothing to do with them. * diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index 3a40154..183c371 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -27,7 +27,7 @@ #include <symbols.h> /* This allows USB A-A firmware upload from a compatible host in four parts: - * The first two are the bare BL1 and the Coreboot boot block, which are just + * The first two are the bare BL1 and the coreboot boot block, which are just * written to their respective loading addresses. These transfers are initiated * by the IROM / BL1, so this code has nothing to do with them. * diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 7731857..7086da8 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -182,7 +182,7 @@ if (cpu_state & CORE_STATE_RESET) { /* For Reset, U-Boot jumps to its starting address; - * on Coreboot, seems ok to ignore for now. */ + * on coreboot, seems ok to ignore for now. */ } wait_and_jump(&exynos_cpu_states->hotplug_address); /* never returns. */ diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 7cdbdec..d6e6296 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -41,7 +41,7 @@ add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) printf "\n** WARNING **\n" - printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" + printf "coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" printf "flash ROM! Make sure that you only write valid flash regions.\n\n" printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c index 7d5b4f4..ca2ec78 100644 --- a/src/vendorcode/amd/cimx/sb700/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb700/SBCMN.c @@ -145,7 +145,7 @@ RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4); - #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot. + #if 0 //KZ [083011]-It's used wrong BIOS SIZE for coreboot. //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before //changing it. ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar); diff --git a/src/vendorcode/amd/cimx/sb700/SBPort.c b/src/vendorcode/amd/cimx/sb700/SBPort.c index 6c5740b..d148481 100644 --- a/src/vendorcode/amd/cimx/sb700/SBPort.c +++ b/src/vendorcode/amd/cimx/sb700/SBPort.c @@ -222,7 +222,7 @@ if (dbVar0 > 4) { dbVar0 = 0; } - //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0); + //KZ [061811]-It's used wrong BIOS SIZE for coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0); if (pConfig->Spi33Mhz) //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios -- To view, visit https://review.coreboot.org/20029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Gerrit-Change-Number: 20029 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: payloads: change coreboot to lowercase
by Martin Roth (Code Review) 04 Jun '17

04 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20028 Change subject: payloads: change coreboot to lowercase ...................................................................... payloads: change coreboot to lowercase The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd Signed-off-by: Martin Roth <martinroth(a)google.com> --- M payloads/bayou/lzma.c M payloads/coreinfo/bootlog_module.c M payloads/coreinfo/coreboot_module.c M payloads/coreinfo/timestamps_module.c M payloads/external/SeaBIOS/Kconfig M payloads/libpayload/arch/arm64/main.c M payloads/libpayload/libc/malloc.c 7 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20028/1 diff --git a/payloads/bayou/lzma.c b/payloads/bayou/lzma.c index a7a8717..14bd921 100644 --- a/payloads/bayou/lzma.c +++ b/payloads/bayou/lzma.c @@ -1,6 +1,6 @@ /* -Coreboot interface to memory-saving variant of LZMA decoder +coreboot interface to memory-saving variant of LZMA decoder (C)opyright 2006 Carl-Daniel Hailfinger Released under the GNU GPL v2 or later diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c index b3f0dee..8a9e7a3 100644 --- a/payloads/coreinfo/bootlog_module.c +++ b/payloads/coreinfo/bootlog_module.c @@ -170,7 +170,7 @@ static int bootlog_module_redraw(WINDOW *win) { - print_module_title(win, "Coreboot Bootlog"); + print_module_title(win, "coreboot Bootlog"); if (!g_buf) { return -1; diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 0b6cca8..adf8f14 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -42,10 +42,10 @@ int row = 2; int i; - print_module_title(win, "Coreboot Tables"); + print_module_title(win, "coreboot Tables"); if (tables_good) { - mvwprintw(win, row++, 1, "No Coreboot tables were found"); + mvwprintw(win, row++, 1, "No coreboot tables were found"); return 0; } @@ -249,7 +249,7 @@ } struct coreinfo_module coreboot_module = { - .name = "Coreboot", + .name = "coreboot", .init = coreboot_module_init, .redraw = coreboot_module_redraw, }; diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c index eedb3c9..020fcc6 100644 --- a/payloads/coreinfo/timestamps_module.c +++ b/payloads/coreinfo/timestamps_module.c @@ -228,7 +228,7 @@ static int timestamps_module_redraw(WINDOW *win) { - print_module_title(win, "Coreboot Timestamps"); + print_module_title(win, "coreboot Timestamps"); if (!g_buf) return -1; diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index b0fb1a5..dc04f37 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -57,7 +57,7 @@ depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT bool help - Coreboot can initialize the GPU of some mainboards. + coreboot can initialize the GPU of some mainboards. After initializing the GPU, the information about it can be passed to the payload. Provide an option rom that implements this legacy VGA BIOS compatibility requirement. diff --git a/payloads/libpayload/arch/arm64/main.c b/payloads/libpayload/arch/arm64/main.c index e616956..aa2292f 100644 --- a/payloads/libpayload/arch/arm64/main.c +++ b/payloads/libpayload/arch/arm64/main.c @@ -64,7 +64,7 @@ mmu_presysinfo_memory_used(start, end - start); /* - * Memory range 2: Coreboot tables + * Memory range 2: coreboot tables * * Maximum size is assumed 2 pages in case it crosses the GRANULE_SIZE * boundary diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index b7ac1a7..595af63 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -94,7 +94,7 @@ } /* - * DMA memory might not be zeroed by Coreboot on stage loading, so make + * DMA memory might not be zeroed by coreboot on stage loading, so make * sure we clear the magic cookie from last boot. */ *(hdrtype_t *)start = 0; -- To view, visit https://review.coreboot.org/20028 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd Gerrit-Change-Number: 20028 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mb/google/soraka: Update UF camera i2c address
by Furquan Shaikh (Code Review) 04 Jun '17

04 Jun '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/20023 ) Change subject: mb/google/soraka: Update UF camera i2c address ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/20023 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b Gerrit-Change-Number: 20023 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Jun 2017 00:56:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/ite/it8720f: add new IT8720F Super I/O
by build bot (Jenkins) (Code Review) 03 Jun '17

03 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20026 ) Change subject: superio/ite/it8720f: add new IT8720F Super I/O ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10546/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54846/ : SUCCESS -- To view, visit https://review.coreboot.org/20026 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a Gerrit-Change-Number: 20026 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Jun 2017 22:55:29 +0000 Gerrit-HasComments: No

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