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Change in coreboot[master]: util/blobtool: add spec files for DDR3 SPDs
by Martin Roth (Code Review) 07 Jun '17

07 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20094 Change subject: util/blobtool: add spec files for DDR3 SPDs ...................................................................... util/blobtool: add spec files for DDR3 SPDs Because of how blobtool works, we need different files for the 128 and 256 byte versions. Change-Id: I9a3a532515eaeeb65ae05ce4f7a37c88500c6193 Signed-off-by: Martin Roth <martinroth(a)google.com> --- A util/blobtool/ddr3_unregistered_spd_128.spec A util/blobtool/ddr3_unregistered_spd_256.spec 2 files changed, 467 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/20094/1 diff --git a/util/blobtool/ddr3_unregistered_spd_128.spec b/util/blobtool/ddr3_unregistered_spd_128.spec new file mode 100644 index 0000000..3bf027a --- /dev/null +++ b/util/blobtool/ddr3_unregistered_spd_128.spec @@ -0,0 +1,226 @@ +# Applies to unbuffered DIMM types +# UDIMM, SO-DIMM, Micro-DIMM, Micro-UDIMM, +# 72b-SO-UDIMM, 16b-SO-UDIMM, 32b-SO-UDIMM + + +# 4_01_02_11R24.pdf +# +# JEDEC Standard No. 21-C +# Page 4.1.2.11 - 1 +# Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules +# DDR3 SPD +# Document Release 6 +# UDIMM Revision 1.3 +# RDIMM Revision 1.3 +# CDIMM Revision 1.3 +# LRDIMM Revision 1.2 + +{ + # Byte 0: Number of Bytes Used / Number of Bytes in SPD Device / + # CRC Coverage + "SPD_Bytes_Used" : 4, + "SPD_Bytes_Total" : 3, + "CRC_Coverage" : 1, + + # Byte 1: SPD Revision + "SPD_Revision" : 8, + + # Byte 2: Key Byte / DRAM Device Type + "DRAM_Device_Type" : 8, + + # Byte 3: Key Byte / Module Type + "Module_Type" : 4, + "Byte_3_reserved" : 4, + + # Byte 4: SDRAM Density and Banks + "SDRAM_Capacity" : 4, + "Bank_Address_Bits" : 3, + "Byte_4_reserved" : 1, + + # Byte 5: SDRAM Addressing + "Column_Address_Bits" : 3, + "Row_Address_Bits" : 3, + "Byte_5_reserved" : 2, + + # Byte 6: Module Nominal Voltage, VDD + "NOT_1.5_V_Operable" : 1, + "1.35_V_Operable" : 1, + "1.25_V_Operable" : 1, + "Byte_6_reserved" : 5, + + # Byte 7: Module Organization + "SDRAM_Device_Width" : 3, + "Number_of_Ranks" : 3, + "Byte_7_reserved" : 2, + + # Byte 8: Module Memory Bus Width + "Primary_Bus_Width" : 3, + "Bus_Width_Extension" : 3, + "Byte_8_reserved" : 2, + + # Byte 9: Fine Timebase (FTB) Dividend / Divisor + "Fine_Timebase_Divisor" : 4, + "Fine_Timebase_Dividend" : 4, + + # Bytes 10 / 11: Medium Timebase (MTB) Dividend / Divisor + "Medium_Timebase_Dividend" : 8, + "Medium_Timebase_Divisor" : 8, + + # Byte 12: SDRAM Minimum Cycle Time (t CK min) + "Minimum_SDRAM_Cycle_Time" : 8, + + # Byte 13: Reserved + "Byte_13_Reserved" : 8, + + # Bytes 14 / 15: CAS Latencies Supported + "CL_4_Supported" : 1, + "CL_5_Supported" : 1, + "CL_6_Supported" : 1, + "CL_7_Supported" : 1, + "CL_8_Supported" : 1, + "CL_9_Supported" : 1, + "CL_10_Supported" : 1, + "CL_11_Supported" : 1, + + "CL_12_Supported" : 1, + "CL_13_Supported" : 1, + "CL_14_Supported" : 1, + "CL_15_Supported" : 1, + "CL_16_Supported" : 1, + "CL_17_Supported" : 1, + "CL_18_Supported" : 1, + "Byte_15_Reserved" : 1, + + # Byte 16: Minimum CAS Latency Time (tAAmin) + "tAAmin" : 8, + + # Byte 17: Minimum Write Recovery Time (tWRmin) + "tWRmin" : 8, + + # Byte 18: Minimum RAS to CAS Delay Time (tRCDmin) + "tRCDmin" : 8, + + # Byte 19: Minimum Row Active to Row Active Delay Time (tRRDmin) + "tRRDmin" : 8, + + # Byte 20: Minimum Row Precharge Delay Time (tRPmin) + "tRPmin" : 8, + + # Bytes 21 - 23: Minimum Active to Precharge Delay Time (tRASmin) + # / Minimum Active to Active/Refresh Delay Time + # (tRCmin) + "tRASmin_Most_Significant Nibble" : 4, + "tRCmin_Most_Significant Nibble" : 4, + "tRASmin_LSB" : 8, + "tRCmin_LSB" : 8, + + # Bytes 24 - 25: Minimum Refresh Recovery Delay Time (tRFCmin) + "tRFCmin LSB" : 8, + "tRFCmin MSB" : 8, + + # Byte 26: Minimum Internal Write to Read Command Delay Time + "tWTRmin" : 8, + + # Byte 27: Minimum Internal Read to Precharge Command Delay Time + # (tRTPmin) + "tRTPmin" : 8, + + # Byte 28 - 29: Minimum Four Activate Window Delay Time + # (tFAWmin) + "tFAWmin Most Significant Nibble" : 4, + "Byte_28_Reserved" : 4, + "tFAWmin Most Significant Byte" : 8, + + # Byte 30: SDRAM Optional Features + "RQZ_Div_6_Supported" : 1, + "RQZ_Div_7_Supported" : 1, + "Byte_30_Reserved" : 5, + "DLL_Off_Mode_Supported" : 1, + + # Byte 31: SDRAM Thermal and Refresh + # Options + "Extended_Temp_range_supported" : 1, + "Extended_Temp_Refresh_1x_Refresh" : 1, + "Auto_Self_Refresh_Supported" : 1, + "On-Die_Thermal_Sensor" : 1, + "Byte_31_Reserved" : 3, + "Partial_Array_Self_Refresh_Supported" : 1, + + # Byte 32: Module Thermal Sensor + "Thermal_Sensor_Accuracy" : 7, + "Thermal_Sensor_incorporated" : 1, + + # Byte 33: SDRAM Device Type + "Signal_Loading" : 2, + "Byte_33_Reserved" : 2, + "Die_Count" : 3, + "SDRAM_Device_Type" : 1, + + # Byte 34: Fine Offset for SDRAM Minimum + # Cycle Time (tCKmin) + "tCKmin_Fine_Offset" : 8, + + #Byte 35: Fine Offset for Minimum CAS Latency Time (tAAmin) + "tAAmin_Fine_Offset" : 8, + + # Byte 36: Fine Offset for Minimum RAS to CAS Delay Time + # (tRCDmin) + "tRCDmin_Fine_Offset" : 8, + + #Byte 37: Fine Offset for Minimum Row Precharge Delay Time + # (tRPmin) + "tRPmin_Fine_Offset" : 8, + + # Byte 38: Fine Offset for Minimum Active to Active/Refresh + # Delay Time (tRCmin) + "tRCmin_Fine_Offset" : 8, + + # Bytes 39 / 40: Reserved + "Byte_39_Reserved" : 8, + "Byte_40_Reserved" : 8, + + # Byte 41: SDRAM Maximum Active Count (MAC) Value + "Maximum_Activate_Count" : 4, + "Maximum_Activate_Window" : 2, + "Byte_41_Reserved" : 2, + + # Bytes 42 - 59: Reserved + "Reserved_bytes_42_to_59_" [18] : 8, + +# Module-Specific Section: Bytes 60 - 116 for Unbuffered DIMMS + + # Byte 60 (Unbuffered): Raw Card Extension, Module Nominal Height + "Module_Nominal_Height" : 5, + "Raw_Card_Estension" : 3, + + # Byte 61 (Unbuffered): Module Maximum Thickness + "Module_Thickness_Front" : 4, + "Module_Thickness_Back" : 4, + + # Byte 62 (Unbuffered): Reference Raw Card Used + "Reference_Raw_Card" : 5, + "Reference_Raw_Card_Revision" : 2, + "Reference_Raw_Card_Extension" : 1, + + # Byte 63: Address Mapping from Edge Connector to DRAM + "Rank_1_Mapping_Mirrored" : 1, + "Byte_63_Reserved" : 7, + + # Bytes 64 -116 (Unbuffered): Reserved + "Module_Specific_Byte_Reserved_"[53] : 8, + + # Bytes 117 - 118: Module ID: Module Manufacturers JEDEC ID Code + "Module_Manufacturer_JEDEC_ID_Code" : 16, + + # Byte 119: Module ID: Module Manufacturing Location + "Module_Manufacturing_Location" : 8, + + # Bytes 120 - 121: Module ID: Module Manufacturing Date + "Module_Manufacturing_Date" : 16, + + # Bytes 122 - 125: Module ID: Module Serial Number + "Module_Serial_Number" : 32, + + # Bytes 126 - 127: Cyclical Redundancy Code + "Module_CRC" : 16 +} diff --git a/util/blobtool/ddr3_unregistered_spd_256.spec b/util/blobtool/ddr3_unregistered_spd_256.spec new file mode 100644 index 0000000..d9cf51e --- /dev/null +++ b/util/blobtool/ddr3_unregistered_spd_256.spec @@ -0,0 +1,241 @@ +# Applies to unbuffered DIMM types +# UDIMM, SO-DIMM, Micro-DIMM, Micro-UDIMM, +# 72b-SO-UDIMM, 16b-SO-UDIMM, 32b-SO-UDIMM + + +# 4_01_02_11R24.pdf +# +# JEDEC Standard No. 21-C +# Page 4.1.2.11 - 1 +# Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules +# DDR3 SPD +# Document Release 6 +# UDIMM Revision 1.3 +# RDIMM Revision 1.3 +# CDIMM Revision 1.3 +# LRDIMM Revision 1.2 + +{ + # Byte 0: Number of Bytes Used / Number of Bytes in SPD Device / + # CRC Coverage + "SPD_Bytes_Used" : 4, + "SPD_Bytes_Total" : 3, + "CRC_Coverage" : 1, + + # Byte 1: SPD Revision + "SPD_Revision" : 8, + + # Byte 2: Key Byte / DRAM Device Type + "DRAM_Device_Type" : 8, + + # Byte 3: Key Byte / Module Type + "Module_Type" : 4, + "Byte_3_reserved" : 4, + + # Byte 4: SDRAM Density and Banks + "SDRAM_Capacity" : 4, + "Bank_Address_Bits" : 3, + "Byte_4_reserved" : 1, + + # Byte 5: SDRAM Addressing + "Column_Address_Bits" : 3, + "Row_Address_Bits" : 3, + "Byte_5_reserved" : 2, + + # Byte 6: Module Nominal Voltage, VDD + "NOT_1.5_V_Operable" : 1, + "1.35_V_Operable" : 1, + "1.25_V_Operable" : 1, + "Byte_6_reserved" : 5, + + # Byte 7: Module Organization + "SDRAM_Device_Width" : 3, + "Number_of_Ranks" : 3, + "Byte_7_reserved" : 2, + + # Byte 8: Module Memory Bus Width + "Primary_Bus_Width" : 3, + "Bus_Width_Extension" : 3, + "Byte_8_reserved" : 2, + + # Byte 9: Fine Timebase (FTB) Dividend / Divisor + "Fine_Timebase_Divisor" : 4, + "Fine_Timebase_Dividend" : 4, + + # Bytes 10 / 11: Medium Timebase (MTB) Dividend / Divisor + "Medium_Timebase_Dividend" : 8, + "Medium_Timebase_Divisor" : 8, + + # Byte 12: SDRAM Minimum Cycle Time (t CK min) + "Minimum_SDRAM_Cycle_Time" : 8, + + # Byte 13: Reserved + "Byte_13_Reserved" : 8, + + # Bytes 14 / 15: CAS Latencies Supported + "CL_4_Supported" : 1, + "CL_5_Supported" : 1, + "CL_6_Supported" : 1, + "CL_7_Supported" : 1, + "CL_8_Supported" : 1, + "CL_9_Supported" : 1, + "CL_10_Supported" : 1, + "CL_11_Supported" : 1, + + "CL_12_Supported" : 1, + "CL_13_Supported" : 1, + "CL_14_Supported" : 1, + "CL_15_Supported" : 1, + "CL_16_Supported" : 1, + "CL_17_Supported" : 1, + "CL_18_Supported" : 1, + "Byte_15_Reserved" : 1, + + # Byte 16: Minimum CAS Latency Time (tAAmin) + "tAAmin" : 8, + + # Byte 17: Minimum Write Recovery Time (tWRmin) + "tWRmin" : 8, + + # Byte 18: Minimum RAS to CAS Delay Time (tRCDmin) + "tRCDmin" : 8, + + # Byte 19: Minimum Row Active to Row Active Delay Time (tRRDmin) + "tRRDmin" : 8, + + # Byte 20: Minimum Row Precharge Delay Time (tRPmin) + "tRPmin" : 8, + + # Bytes 21 - 23: Minimum Active to Precharge Delay Time (tRASmin) + # / Minimum Active to Active/Refresh Delay Time + # (tRCmin) + "tRASmin_Most_Significant Nibble" : 4, + "tRCmin_Most_Significant Nibble" : 4, + "tRASmin_LSB" : 8, + "tRCmin_LSB" : 8, + + # Bytes 24 - 25: Minimum Refresh Recovery Delay Time (tRFCmin) + "tRFCmin LSB" : 8, + "tRFCmin MSB" : 8, + + # Byte 26: Minimum Internal Write to Read Command Delay Time + "tWTRmin" : 8, + + # Byte 27: Minimum Internal Read to Precharge Command Delay Time + # (tRTPmin) + "tRTPmin" : 8, + + # Byte 28 - 29: Minimum Four Activate Window Delay Time + # (tFAWmin) + "tFAWmin Most Significant Nibble" : 4, + "Byte_28_Reserved" : 4, + "tFAWmin Most Significant Byte" : 8, + + # Byte 30: SDRAM Optional Features + "RQZ_Div_6_Supported" : 1, + "RQZ_Div_7_Supported" : 1, + "Byte_30_Reserved" : 5, + "DLL_Off_Mode_Supported" : 1, + + # Byte 31: SDRAM Thermal and Refresh + # Options + "Extended_Temp_range_supported" : 1, + "Extended_Temp_Refresh_1x_Refresh" : 1, + "Auto_Self_Refresh_Supported" : 1, + "On-Die_Thermal_Sensor" : 1, + "Byte_31_Reserved" : 3, + "Partial_Array_Self_Refresh_Supported" : 1, + + # Byte 32: Module Thermal Sensor + "Thermal_Sensor_Accuracy" : 7, + "Thermal_Sensor_incorporated" : 1, + + # Byte 33: SDRAM Device Type + "Signal_Loading" : 2, + "Byte_33_Reserved" : 2, + "Die_Count" : 3, + "SDRAM_Device_Type" : 1, + + # Byte 34: Fine Offset for SDRAM Minimum + # Cycle Time (tCKmin) + "tCKmin_Fine_Offset" : 8, + + #Byte 35: Fine Offset for Minimum CAS Latency Time (tAAmin) + "tAAmin_Fine_Offset" : 8, + + # Byte 36: Fine Offset for Minimum RAS to CAS Delay Time + # (tRCDmin) + "tRCDmin_Fine_Offset" : 8, + + #Byte 37: Fine Offset for Minimum Row Precharge Delay Time + # (tRPmin) + "tRPmin_Fine_Offset" : 8, + + # Byte 38: Fine Offset for Minimum Active to Active/Refresh + # Delay Time (tRCmin) + "tRCmin_Fine_Offset" : 8, + + # Bytes 39 / 40: Reserved + "Byte_39_Reserved" : 8, + "Byte_40_Reserved" : 8, + + # Byte 41: SDRAM Maximum Active Count (MAC) Value + "Maximum_Activate_Count" : 4, + "Maximum_Activate_Window" : 2, + "Byte_41_Reserved" : 2, + + # Bytes 42 - 59: Reserved + "Reserved_bytes_42_to_59_" [18] : 8, + +# Module-Specific Section: Bytes 60 - 116 for Unbuffered DIMMS + + # Byte 60 (Unbuffered): Raw Card Extension, Module Nominal Height + "Module_Nominal_Height" : 5, + "Raw_Card_Estension" : 3, + + # Byte 61 (Unbuffered): Module Maximum Thickness + "Module_Thickness_Front" : 4, + "Module_Thickness_Back" : 4, + + # Byte 62 (Unbuffered): Reference Raw Card Used + "Reference_Raw_Card" : 5, + "Reference_Raw_Card_Revision" : 2, + "Reference_Raw_Card_Extension" : 1, + + # Byte 63: Address Mapping from Edge Connector to DRAM + "Rank_1_Mapping_Mirrored" : 1, + "Byte_63_Reserved" : 7, + + # Bytes 64 -116 (Unbuffered): Reserved + "Module_Specific_Byte_Reserved_"[53] : 8, + + # Bytes 117 - 118: Module ID: Module Manufacturers JEDEC ID Code + "Module_Manufacturer_JEDEC_ID_Code" : 16, + + # Byte 119: Module ID: Module Manufacturing Location + "Module_Manufacturing_Location" : 8, + + # Bytes 120 - 121: Module ID: Module Manufacturing Date + "Module_Manufacturing_Date" : 16, + + # Bytes 122 - 125: Module ID: Module Serial Number + "Module_Serial_Number" : 32, + + # Bytes 126 - 127: Cyclical Redundancy Code + "Module_CRC" : 16, + + # Bytes 128 - 145: Module Part Number + "Module_Part_Number"[18] : 8, + + # Bytes 146 - 147: Module Revision Code + "Module_Revision_Code" : 16, + + # Bytes 148 - 149: DRAM Manufacturers JEDEC ID Code + "DRAM_Manufacturer_JEDEC_ID_Code" : 16, + + # Bytes 150 - 175: Manufacturers Specific Data + "Manufacturer_Specific_Data_byte_" [26] : 8, + + # Bytes 176 - 255: Open for customer use + "Customer_use_byte_" [80] : 8 +} -- To view, visit https://review.coreboot.org/20094 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9a3a532515eaeeb65ae05ce4f7a37c88500c6193 Gerrit-Change-Number: 20094 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: google/parrot: use a GNVS variable to specify trackpad inter...
by Matt DeVillier (Code Review) 07 Jun '17

07 Jun '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/20093 Change subject: google/parrot: use a GNVS variable to specify trackpad interrupt ...................................................................... google/parrot: use a GNVS variable to specify trackpad interrupt Use a GNVS variable to store the trackpad interrupt, in order to support both SNB and IVB variants from a single build. Change-Id: I53df35fff41f52a7d142aea9b1b590c65195bcfd Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/parrot/acpi/mainboard.asl M src/mainboard/google/parrot/acpi_tables.c 2 files changed, 38 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/20093/1 diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 98208e0..91623024 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -47,7 +47,7 @@ } Device (TPAD) - { + { Name (_ADR, 0x0) Name (_UID, 1) @@ -58,25 +58,35 @@ // Trackpad Wake is GPIO12, wake from S3 Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) - Name(_CRS, ResourceTemplate() - { - - // PIRQA -> GSI16 - Interrupt (ResourceConsumer, Level, ActiveLow) - { - BOARD_TRACKPAD_IRQ_DVT - } - - // PIRQE -> GSI20 - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ_PVT - } - - // SMBUS Address 0x67 - VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } - }) - } + Name (DCRS, ResourceTemplate () + { + // PIRQA -> GSI16 + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) + { + BOARD_TRACKPAD_IRQ_DVT, + } + // SMBUS Address 0x67 + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } + }) + Name (PCRS, ResourceTemplate () + { + // PIRQE -> GSI20 + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) + { + BOARD_TRACKPAD_IRQ_PVT, + } + // SMBUS Address 0x67 + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } + }) + Method (_CRS, 0, NotSerialized) + { + If (\TPIQ == 16){ + Return (DCRS) + } Else { + Return (PCRS) + } + } + } Device (MB) { Name(_HID, EisaId("PNP0C01")) // System Board diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 81008a5..6eb3e41 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -31,6 +31,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" +#include "onboard.h" static void acpi_update_thermal_table(global_nvs_t *gnvs) { @@ -59,4 +60,11 @@ // the lid is open by default. gnvs->lids = 1; + + //set trackpad IRQ + if (parrot_rev() < 0x2) { /* DVT vs PVT */ + gnvs->tpiq = BOARD_TRACKPAD_IRQ_DVT; + } else { + gnvs->tpiq = BOARD_TRACKPAD_IRQ_PVT; + } } -- To view, visit https://review.coreboot.org/20093 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I53df35fff41f52a7d142aea9b1b590c65195bcfd Gerrit-Change-Number: 20093 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: southbridge/bd82x6x - add GNVS var for trackpad IRQ
by Matt DeVillier (Code Review) 07 Jun '17

07 Jun '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/20092 Change subject: southbridge/bd82x6x - add GNVS var for trackpad IRQ ...................................................................... southbridge/bd82x6x - add GNVS var for trackpad IRQ Add a GNVS variable to store trackpad IRQ for google/parrot, so that both SNB and IVB variants can be built with the same config Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/nvs.h 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/20092/1 diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index ad02716..f0a0fb6 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -175,6 +175,7 @@ ALFP, 8, // 0xf2 - active lfp IMON, 8, // 0xf3 - current graphics turbo imon value MMIO, 8, // 0xf4 - 64bit mmio support + TPIQ, 8, // 0xf5 - trakcpad IRQ value /* ChromeOS specific */ Offset (0x100), diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 8775335..e71feda 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -145,7 +145,8 @@ u8 alfp; /* 0xf2 - active lfp */ u8 imon; /* 0xf3 - current graphics turbo imon value */ u8 mmio; /* 0xf4 - 64bit mmio support */ - u8 rsvd13[11]; /* 0xf5 - rsvd */ + u8 tpiq; /* 0xf5 - trackpad IRQ value */ + u8 rsvd13[10]; /* 0xf6 - rsvd */ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/20092 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3 Gerrit-Change-Number: 20092 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: haswell: add CBMEM_MEMINFO table when initing RAM
by Martin Roth (Code Review) 07 Jun '17

07 Jun '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19958 ) Change subject: haswell: add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/ramin… File src/northbridge/intel/haswell/raminit.c: https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/ramin… PS2, Line 203: 0x18 MEMORY_TYPE_DDR is implemented in include/smbios.h https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/ramin… PS2, Line 210: 122 Adding a include/spd_ddr3.h file similar to the spd_ddr2.h file for these fields would be nice. https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/ramin… PS2, Line 218: //SPD_SODIMM Should we detect this, or will this code only be for laptops? https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/ramin… PS2, Line 218: 3 Is this an SPD field or a SMBIOS field? Use a #define? -- To view, visit https://review.coreboot.org/19958 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Gerrit-Change-Number: 19958 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 18:02:08 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: util/lint/kconfig_lint: update help checking
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19851 ) Change subject: util/lint/kconfig_lint: update help checking ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10790/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55110/ : SUCCESS -- To view, visit https://review.coreboot.org/19851 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibf868c83e2a128ceb6c4d3da7f2cf7dc237054e6 Gerrit-Change-Number: 19851 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ronald Minnich <rminnich(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 17:31:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drvs/intel/wifi/wifi: Fix regression
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20082 ) Change subject: drvs/intel/wifi/wifi: Fix regression ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/55109/ : SUCCESS -- To view, visit https://review.coreboot.org/20082 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f Gerrit-Change-Number: 20082 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 14:51:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drvs/intel/wifi/wifi: Fix regression
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20082 ) Change subject: drvs/intel/wifi/wifi: Fix regression ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55108/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/10789/ : SUCCESS -- To view, visit https://review.coreboot.org/20082 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f Gerrit-Change-Number: 20082 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 14:47:17 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge: Fill in acpi_name
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20085 ) Change subject: nb/intel/sandybridge: Fill in acpi_name ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10788/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55107/ : SUCCESS -- To view, visit https://review.coreboot.org/20085 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9 Gerrit-Change-Number: 20085 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 14:46:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Fill in acpi_name
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20086 ) Change subject: sb/intel/bd82x6x: Fill in acpi_name ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10787/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55106/ : SUCCESS -- To view, visit https://review.coreboot.org/20086 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6 Gerrit-Change-Number: 20086 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 14:44:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: rx6110sa: Add more chip configuration options to chip
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20084 ) Change subject: rx6110sa: Add more chip configuration options to chip ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10786/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55105/ : SUCCESS -- To view, visit https://review.coreboot.org/20084 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b Gerrit-Change-Number: 20084 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 14:20:24 +0000 Gerrit-HasComments: No

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