coreboot-gerrit June 2017

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Change in coreboot[master]: mainboard/google/poppy: Add support for ELAN device
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20040 ) Change subject: mainboard/google/poppy: Add support for ELAN device ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10810/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55130/ : SUCCESS -- To view, visit https://review.coreboot.org/20040 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c Gerrit-Change-Number: 20040 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 20:47:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: spi: Remove unused/unnecessary spi_init function definitions
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20039 ) Change subject: spi: Remove unused/unnecessary spi_init function definitions ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10809/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55129/ : SUCCESS -- To view, visit https://review.coreboot.org/20039 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430 Gerrit-Change-Number: 20039 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 20:46:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/foxconn/g41s-k: add new mainboard
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20027 ) Change subject: mb/foxconn/g41s-k: add new mainboard ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10807/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55127/ : SUCCESS -- To view, visit https://review.coreboot.org/20027 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda Gerrit-Change-Number: 20027 Gerrit-PatchSet: 4 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 20:29:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src/cpu/amd/pi Fix checkpatch warnings and errors
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20098 ) Change subject: src/cpu/amd/pi Fix checkpatch warnings and errors ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10808/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55128/ : SUCCESS -- To view, visit https://review.coreboot.org/20098 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4 Gerrit-Change-Number: 20098 Gerrit-PatchSet: 1 Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 20:26:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/ite/it8728f: remove unused header
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20025 ) Change subject: superio/ite/it8728f: remove unused header ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10804/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55124/ : SUCCESS -- To view, visit https://review.coreboot.org/20025 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifcbf95ffd6d13cae4e6864e0320ce6ce1cf3ae4d Gerrit-Change-Number: 20025 Gerrit-PatchSet: 3 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 20:26:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/ite/it8720f: add new IT8720F Super I/O
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20026 ) Change subject: superio/ite/it8720f: add new IT8720F Super I/O ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10806/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55126/ : SUCCESS -- To view, visit https://review.coreboot.org/20026 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a Gerrit-Change-Number: 20026 Gerrit-PatchSet: 3 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 20:23:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src/cpu/amd/pi Fix checkpatch warnings and errors
by Evelyn Huang (Code Review) 07 Jun '17

07 Jun '17

Evelyn Huang has uploaded this change for review. ( https://review.coreboot.org/20098 Change subject: src/cpu/amd/pi Fix checkpatch warnings and errors ...................................................................... src/cpu/amd/pi Fix checkpatch warnings and errors Fix remaining space prohibited between function name and open parenthesis, line over 80 characteres, unnecessary braces for single statement blocks, space required before open brace errors and warnings in subdirectories of src/cpu/amd/pi Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4 Signed-off-by: Evelyn Huang <evhuang(a)google.com> --- M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/00670F00/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/cpu/amd/pi/00730F01/model_16_init.c 5 files changed, 69 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/20098/1 diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 20353a0..276f064 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -25,7 +25,7 @@ AMD_CONFIG_PARAMS StdHeader; /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); @@ -33,29 +33,32 @@ * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * set to non-posted regions. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + /* last address before processor local APIC at FEE00000 */ + PciData = 0x00FEDF00; + /* set NP (non-posted) bit */ + PciData |= 1 << 7; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + /* lowest NP address is HPET at FED00000 */ + PciData = (0xFED00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -68,24 +71,26 @@ AMD_CONFIG_PARAMS StdHeader; /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + * Set the MMIO Configuration Base Address and + * Bus Range onto MMIO configuration base + * Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | + (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); /* For serial port */ PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index c31dec8..bce276d 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -40,11 +40,11 @@ u32 Bar3Addr; u64 Tmp64; /* Get Bar3 Addr */ - Bar3Addr = PspLibPciReadPspConfig (0x20); + Bar3Addr = PspLibPciReadPspConfig(0x20); Tmp64 = Bar3Addr; printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); - LibAmdMsrWrite (0xC00110A2, &Tmp64, NULL); - LibAmdMsrRead (0xC00110A2, &Tmp64, NULL); + LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL); + LibAmdMsrRead(0xC00110A2, &Tmp64, NULL); } static void model_15_init(device_t dev) @@ -58,7 +58,7 @@ u32 siblings; #endif - disable_cache (); + disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -67,12 +67,12 @@ // BSP: make a0000-bffff UC, c0000-fffff WB msr.lo = msr.hi = 0; - wrmsr (0x259, msr); + wrmsr(0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); + wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; @@ -85,9 +85,8 @@ /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < 6; i++) wrmsr(MCI_STATUS + (i * 4), msr); - } /* Enable the local CPU APICs */ diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index e7d7ba5..2571c69 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -47,7 +47,7 @@ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; @@ -73,8 +73,8 @@ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \ - (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | + (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); /* For serial port */ @@ -85,11 +85,11 @@ /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 674e5c1..696641c 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -25,7 +25,7 @@ AMD_CONFIG_PARAMS StdHeader; /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); @@ -33,29 +33,32 @@ * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * set to non-posted regions. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + /* last address before processor local APIC at FEE00000 */ + PciData = 0x00FEDF00; + /* set NP (non-posted) bit */ + PciData |= 1 << 7; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + /* lowest NP address is HPET at FED00000 */ + PciData = (0xFED00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -68,15 +71,17 @@ AMD_CONFIG_PARAMS StdHeader; /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + * Set the MMIO Configuration Base Address and + * Bus Range onto MMIO configuration base + * Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | + (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); /* For serial port */ PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* PSP */ @@ -86,11 +91,11 @@ /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 294814f..e14746f 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -41,21 +41,23 @@ u32 siblings; #endif - disable_cache (); + disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + /* BSP: make a0000-bffff UC, c0000-fffff WB, + * same as OntarioApMtrrSettingsList for APs + */ msr.lo = msr.hi = 0; - wrmsr (0x259, msr); + wrmsr(0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); + wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; @@ -68,9 +70,8 @@ /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < 6; i++) wrmsr(MCI_STATUS + (i * 4), msr); - } /* Enable the local CPU APICs */ -- To view, visit https://review.coreboot.org/20098 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4 Gerrit-Change-Number: 20098 Gerrit-PatchSet: 1 Gerrit-Owner: Evelyn Huang <evhuang(a)google.com>

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Change in coreboot[master]: superio/acpi: allow custom HID on generic device
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20076 ) Change subject: superio/acpi: allow custom HID on generic device ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10803/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55123/ : SUCCESS -- To view, visit https://review.coreboot.org/20076 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7793b7d53c9d94667675f9dee63358521ac8c4be Gerrit-Change-Number: 20076 Gerrit-PatchSet: 2 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 20:16:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/acpi: allow 3 I/O ranges on generic device
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20024 ) Change subject: superio/acpi: allow 3 I/O ranges on generic device ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10802/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55122/ : SUCCESS -- To view, visit https://review.coreboot.org/20024 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idad03f3881e0fbf2135562316d177972f931afec Gerrit-Change-Number: 20024 Gerrit-PatchSet: 3 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 20:16:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/ite/common: fix prototype to match others
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20077 ) Change subject: superio/ite/common: fix prototype to match others ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10805/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55125/ : SUCCESS -- To view, visit https://review.coreboot.org/20077 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id4a079d868c5c806c769b5559833566e8a6a8a71 Gerrit-Change-Number: 20077 Gerrit-PatchSet: 2 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 20:15:35 +0000 Gerrit-HasComments: No

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