coreboot-gerrit June 2017

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Change in coreboot[master]: src/cpu/amd/pi/00630F01 Fix checkpatch warnings and errors
by Evelyn Huang (Code Review) 07 Jun '17

07 Jun '17

Evelyn Huang has uploaded this change for review. ( https://review.coreboot.org/20096 Change subject: src/cpu/amd/pi/00630F01 Fix checkpatch warnings and errors ...................................................................... src/cpu/amd/pi/00630F01 Fix checkpatch warnings and errors Fixed space prohibited between function name and open parenthesis, line over 8- characteres, unnecessary braces for single statement blocks, space required before open brace errors and warnings Change-Id: I66f1a8640ec5c9d8a1dd039088598f40e8d30f95 Signed-off-by: Evelyn Huang <evhuang(a)google.com> --- M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00630F01/model_15_init.c 2 files changed, 34 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/20096/1 diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 3be3690..43a7e7c 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -25,7 +25,7 @@ AMD_CONFIG_PARAMS StdHeader; /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); @@ -33,29 +33,33 @@ * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * set to non-posted regions. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + /* last address before processor local APIC at FEE00000 */ + PciData = 0x00FEDF00; + /* set NP (non-posted) bit */ + PciData |= 1 << 7; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + /* lowest NP address is HPET at FED00000 */ + PciData = (0xFED00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + /* last address before non-posted range */ + PciData = 0x00FECF00; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -66,19 +70,21 @@ AMD_CONFIG_PARAMS StdHeader; /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + * Set the MMIO Configuration Base Address + * and Bus Range onto MMIO configuration base + * Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | + (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 925c60c..c2f2e9d 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -43,21 +43,24 @@ u32 siblings; #endif - disable_cache (); + disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + /* + * BSP: make a0000-bffff UC, c0000-fffff WB, + * same as OntarioApMtrrSettingsList for APs + */ msr.lo = msr.hi = 0; - wrmsr (0x259, msr); + wrmsr(0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); + wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; @@ -70,10 +73,8 @@ /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < 6; i++) wrmsr(MCI_STATUS + (i * 4), msr); - } - /* Enable the local CPU APICs */ setup_lapic(); -- To view, visit https://review.coreboot.org/20096 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I66f1a8640ec5c9d8a1dd039088598f40e8d30f95 Gerrit-Change-Number: 20096 Gerrit-PatchSet: 1 Gerrit-Owner: Evelyn Huang <evhuang(a)google.com>

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Change in coreboot[master]: southbridge/bd82x6x - add GNVS var for trackpad IRQ
by Patrick Rudolph (Code Review) 07 Jun '17

07 Jun '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/20092 ) Change subject: southbridge/bd82x6x - add GNVS var for trackpad IRQ ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/20092 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3 Gerrit-Change-Number: 20092 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 19:00:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/parrot: use a GNVS variable to specify trackpad inter...
by Patrick Rudolph (Code Review) 07 Jun '17

07 Jun '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/20093 ) Change subject: google/parrot: use a GNVS variable to specify trackpad interrupt ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/20093/1/src/mainboard/google/parrot/acpi/ma… File src/mainboard/google/parrot/acpi/mainboard.asl: https://review.coreboot.org/#/c/20093/1/src/mainboard/google/parrot/acpi/ma… PS1, Line 61: Name Please use tabs -- To view, visit https://review.coreboot.org/20093 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53df35fff41f52a7d142aea9b1b590c65195bcfd Gerrit-Change-Number: 20093 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 18:59:00 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: device/pnp: simplify pnp_get_ioresource
by Samuel Holland (Code Review) 07 Jun '17

07 Jun '17

Samuel Holland has uploaded this change for review. ( https://review.coreboot.org/20095 Change subject: device/pnp: simplify pnp_get_ioresource ...................................................................... device/pnp: simplify pnp_get_ioresource This also fixes the limit for single I/O ports: - PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 + PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit fff flags c0000100 index 60 - PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 + PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit fff flags c0000100 index 62 Change-Id: Ia99b785dcd9cf56fb236ad7ade54656851f88a5e Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- M src/device/pnp_device.c 1 file changed, 14 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/20095/1 diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index e7839de..5f69a76 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -194,7 +194,7 @@ static void pnp_get_ioresource(device_t dev, u8 index, u16 mask) { struct resource *resource; - unsigned moving, gran, step; + u16 gran, limit; if (!mask) { printk(BIOS_ERR, "ERROR: device %s index %d has no mask.\n", @@ -205,40 +205,26 @@ resource = new_resource(dev, index); /* Initilize the resource. */ - resource->limit = 0xffff; resource->flags |= IORESOURCE_IO; - /* Get the resource size... */ + /* Get the resource limit (all writiable bits set to one). */ + limit = mask; + limit |= limit >> 1; + limit |= limit >> 2; + limit |= limit >> 4; + limit |= limit >> 8; - moving = mask; - gran = 15; - step = 1 << gran; - - /* Find the first bit that moves. */ - while ((moving & step) == 0) { - gran--; - step >>= 1; - } - - /* Now find the first bit that does not move. */ - while ((moving & step) != 0) { - gran--; - step >>= 1; - } - - /* - * Of the moving bits the last bit in the first group, - * tells us the size of this resource. - */ - if ((moving & step) == 0) { - gran++; - step <<= 1; + /* Get the resource granularity (unwritable bits at the low end). */ + gran = 0; + while ((mask & 1) == 0) { + gran += 1; + mask >>= 1; } /* Set the resource size and alignment. */ - resource->gran = gran; resource->align = gran; - resource->limit = mask | (step - 1); + resource->gran = gran; + resource->limit = limit; resource->size = 1 << gran; } -- To view, visit https://review.coreboot.org/20095 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia99b785dcd9cf56fb236ad7ade54656851f88a5e Gerrit-Change-Number: 20095 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org>

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Change in coreboot[master]: device/pnp: remove struct io_info
by Samuel Holland (Code Review) 07 Jun '17

07 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20078 to look at the new patch set (#4). Change subject: device/pnp: remove struct io_info ...................................................................... device/pnp: remove struct io_info The 'set' field was not used anywhere. Replace the struct with a simple integer representing the mask. initializer updates performed with: sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \ src/ec/*/*/ec.c sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \ src/ec/*/*/ec_lpc.c \ src/superio/*/*/superio.c \ src/superio/smsc/fdc37n972/fdc37n972.c \ src/superio/smsc/sio10n268/sio10n268.c \ src/superio/via/vt1211/vt1211.c src/ec/kontron/it8516e/ec.c was manually updated. The previous value for IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and had a zero bit in the middle of the mask. Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9 Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- M src/device/pnp_device.c M src/ec/compal/ene932/ec.c M src/ec/google/chromeec/ec_lpc.c M src/ec/kontron/it8516e/ec.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c M src/ec/roda/it8518/ec.c M src/include/device/pnp.h M src/superio/fintek/f71805f/superio.c M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f71872/superio.c M src/superio/fintek/f81216h/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/superio.c M src/superio/intel/i3100/superio.c M src/superio/intel/i8900/superio.c M src/superio/ite/it8671f/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8716f/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8720f/superio.c M src/superio/ite/it8721f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/superio.c M src/superio/nsc/pc87309/superio.c M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/dme1737/superio.c M src/superio/smsc/fdc37n972/fdc37n972.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47b272/superio.c M src/superio/smsc/lpc47b397/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch4037/superio.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/sio10n268/sio10n268.c M src/superio/smsc/smscsuperio/superio.c M src/superio/via/vt1211/vt1211.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83697hf/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c 67 files changed, 378 insertions(+), 382 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/20078/4 -- To view, visit https://review.coreboot.org/20078 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9 Gerrit-Change-Number: 20078 Gerrit-PatchSet: 4 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: purism/librem13v2: Don't disable PM timer
by Martin Roth (Code Review) 07 Jun '17

07 Jun '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19938 ) Change subject: purism/librem13v2: Don't disable PM timer ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/19938 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c65cb9d3e6a10baea4cc1e2d9e94c36fe419561 Gerrit-Change-Number: 19938 Gerrit-PatchSet: 4 Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 18:42:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: purism/librem13v2: Add GPIO pad configuration
by Martin Roth (Code Review) 07 Jun '17

07 Jun '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19934 ) Change subject: purism/librem13v2: Add GPIO pad configuration ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/19934 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f Gerrit-Change-Number: 19934 Gerrit-PatchSet: 3 Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 18:27:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/blobtool: add spec files for DDR3 SPDs
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20094 ) Change subject: util/blobtool: add spec files for DDR3 SPDs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10793/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55113/ : SUCCESS -- To view, visit https://review.coreboot.org/20094 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a3a532515eaeeb65ae05ce4f7a37c88500c6193 Gerrit-Change-Number: 20094 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 18:20:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/parrot: use a GNVS variable to specify trackpad inter...
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20093 ) Change subject: google/parrot: use a GNVS variable to specify trackpad interrupt ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10792/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55112/ : SUCCESS -- To view, visit https://review.coreboot.org/20093 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53df35fff41f52a7d142aea9b1b590c65195bcfd Gerrit-Change-Number: 20093 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 18:13:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: southbridge/bd82x6x - add GNVS var for trackpad IRQ
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20092 ) Change subject: southbridge/bd82x6x - add GNVS var for trackpad IRQ ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10791/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55111/ : SUCCESS -- To view, visit https://review.coreboot.org/20092 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3 Gerrit-Change-Number: 20092 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 18:11:11 +0000 Gerrit-HasComments: No

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coreboot-gerrit June 2017