coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: lib/spd_bin: make SMBus SPD addresses an input
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19915 ) Change subject: lib/spd_bin: make SMBus SPD addresses an input ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10112/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54388/ : SUCCESS -- To view, visit https://review.coreboot.org/19915 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: fixed the memory on ch1 is not detected
by Kane Chen (Code Review) 25 May '17

25 May '17

Kane Chen has abandoned this change. ( https://review.coreboot.org/19914 ) Change subject: google/fizz: fixed the memory on ch1 is not detected ...................................................................... Abandoned Thanks Aaron, I think I can abandon this change -- To view, visit https://review.coreboot.org/19914 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: abandon Gerrit-Change-Id: Ia235b75870360d464839aa3b66045b421fd72ddf Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/eve: Update VR config settings
by Duncan Laurie (Code Review) 25 May '17

25 May '17

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/19826 ) Change subject: mainboard/google/eve: Update VR config settings ...................................................................... mainboard/google/eve: Update VR config settings Update Psi2Threshold, IccMax, AcLoadline, DcLoadline VR config settings as per board design. BUG=b:38415991 BRANCH=none TEST=Build and boot eve. Change-Id: I274245821f68fb3151e5563ea0c75eaa1ad32c08 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-on: https://review.coreboot.org/19826 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/eve/devicetree.cb 1 file changed, 13 insertions(+), 13 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Duncan Laurie: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index a7388b9..487dda3 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -68,7 +68,7 @@ #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | @@ -76,13 +76,13 @@ #| ImonOffset | 0 | 0 | 0 | 0 | #| IccMax | 4A | 24A | 24A | 24A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 17.9 | 5.9 | 5.7 | 5.7 | - #| DcLoadline | 14 | 4.7 | 4.2 | 4.2 | + #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 | + #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, @@ -90,14 +90,14 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(4), .voltage_limit = 1520, - .ac_loadline = 1790, - .dc_loadline = 1400, + .ac_loadline = 1490, + .dc_loadline = 1420, }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, @@ -105,14 +105,14 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, - .ac_loadline = 590, - .dc_loadline = 470, + .ac_loadline = 500, + .dc_loadline = 486, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, @@ -127,7 +127,7 @@ register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, @@ -135,8 +135,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, - .ac_loadline = 570, - .dc_loadline = 420, + .ac_loadline = 457, + .dc_loadline = 430, }" # Enable Root port 1 with SRCCLKREQ1# -- To view, visit https://review.coreboot.org/19826 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I274245821f68fb3151e5563ea0c75eaa1ad32c08 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/eve: Update VR config settings
by Duncan Laurie (Code Review) 25 May '17

25 May '17

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/19826 ) Change subject: mainboard/google/eve: Update VR config settings ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/19826 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I274245821f68fb3151e5563ea0c75eaa1ad32c08 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: fixed the memory on ch1 is not detected
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19914 ) Change subject: google/fizz: fixed the memory on ch1 is not detected ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10111/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54387/ : SUCCESS -- To view, visit https://review.coreboot.org/19914 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia235b75870360d464839aa3b66045b421fd72ddf Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: fixed the memory on ch1 is not detected
by Kane Chen (Code Review) 25 May '17

25 May '17

Kane Chen has uploaded a new change for review. ( https://review.coreboot.org/19914 ) Change subject: google/fizz: fixed the memory on ch1 is not detected ...................................................................... google/fizz: fixed the memory on ch1 is not detected The spd address of sodimm on ch1 is 0xA4, but the current code will only scan 0xA0 and 0xA2 if DIMM_MAX = 2 Also, MemorySpdPtr10 UPD for ch1 is not filled accordingly Change-Id: Ia235b75870360d464839aa3b66045b421fd72ddf Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/romstage.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/19914/1 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 2d2e6b7..e0d61f0 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -42,7 +42,7 @@ config DIMM_MAX int - default 2 + default 4 config DIMM_SPD_SIZE int diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index be1d552..a1da494 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -36,7 +36,7 @@ get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; - mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; dump_spd_info(&blk); } -- To view, visit https://review.coreboot.org/19914 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ia235b75870360d464839aa3b66045b421fd72ddf Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: [WIP]Use CPU common code
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19827 ) Change subject: soc/intel/apollolake: [WIP]Use CPU common code ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10110/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54386/ : SUCCESS -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: [WIP]Use CPU common code
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19566 ) Change subject: soc/intel/skylake: [WIP]Use CPU common code ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10109/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54385/ : SUCCESS -- To view, visit https://review.coreboot.org/19566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common CPU code
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19540 ) Change subject: soc/intel/common/block: [WIP]Add Intel common CPU code ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10108/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54384/ : SUCCESS -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: [WIP]Use CPU common code
by Barnali Sarkar (Code Review) 25 May '17

25 May '17

Barnali Sarkar has uploaded a new patch set (#3). ( https://review.coreboot.org/19827 ) Change subject: soc/intel/apollolake: [WIP]Use CPU common code ...................................................................... soc/intel/apollolake: [WIP]Use CPU common code This patch uses common CPU Model library. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/include/soc/cpu.h M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/tsc_freq.c 7 files changed, 17 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/19827/3 -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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coreboot-gerrit May 2017