coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Use CPU common code
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19566 ) Change subject: soc/intel/skylake: Use CPU common code ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10114/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54390/ : SUCCESS -- To view, visit https://review.coreboot.org/19566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common CPU code
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19540 ) Change subject: soc/intel/common/block: Add Intel common CPU code ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10113/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54389/ : SUCCESS -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/*60: Remove not existing DIMMs from SPD map
by Martin Roth (Code Review) 25 May '17

25 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19862 ) Change subject: mb/lenovo/*60: Remove not existing DIMMs from SPD map ...................................................................... mb/lenovo/*60: Remove not existing DIMMs from SPD map Should result in a tiny speed bump in raminit since those addresses are not checked for present DIMMs. Checked in schematics of both Thinkpad X60 and T60 and tested to configure raminit correctly for all DIMMs populated on X60. Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/19862 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index cb3f8bc..80b989f 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -172,7 +172,7 @@ { int s3resume = 0; int dock_err; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; + const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; timestamp_init(get_initial_timestamp()); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 51624a0..eddb150 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -171,7 +171,7 @@ void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; + const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; timestamp_init(get_initial_timestamp()); -- To view, visit https://review.coreboot.org/19862 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common CPU code
by Barnali Sarkar (Code Review) 25 May '17

25 May '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/19540 ) Change subject: soc/intel/common/block: Add Intel common CPU code ...................................................................... Patch Set 8: (12 comments) https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/Kcon… File src/soc/intel/common/block/cpu/Kconfig: PS8, Line 4: Intel Common CPU Model Support. > can you please add little bit more like below. Done https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/cpu.c File src/soc/intel/common/block/cpu/cpu.c: PS8, Line 18: #include <assert.h> : #include <bootstate.h> : #include <console/console.h> : #include <cpu/cpu.h> : #include <cpu/x86/mtrr.h> : #include <cpu/x86/msr.h> : #include <cpu/x86/lapic.h> : #include <cpu/x86/mp.h> : #include <cpu/intel/microcode.h> : #include <cpu/intel/speedstep.h> : #include <cpu/intel/turbo.h> : #include <cpu/x86/cache.h> : #include <cpu/x86/name.h> : #include <cpu/x86/smm.h> : #include <delay.h> : #include <device/device.h> : #include <device/pci.h> : #include <intelblocks/cpu.h> : #include <intelblocks/msr.h> : #include <intelblocks/smm.h> : #include <pc80/mc146818rtc.h> : #include <soc/cpu.h> : #include <soc/pci_devs.h> : #include <soc/systemagent.h> : #include <string.h> > let see if we can optimize this Done PS8, Line 48: : eax = cpuid_eax(CPUID_LEAF_PM); : : msr = rdmsr(MSR_IA32_MISC_ENABLES); : eax &= 0x2; : if ((!eax) && ((msr.hi & BURST_MODE_DISABLE) == 0)) { : /* Burst Mode has been factory configured as disabled : * and is not available in this physical processor : * package. : */ : printk(BIOS_DEBUG, "Burst Mode is factory disabled\n"); : return; : } : : /* Enable burst mode */ : msr.hi &= ~BURST_MODE_DISABLE; : wrmsr(MSR_IA32_MISC_ENABLES, msr); > can this be put into a function and call as enable/disable turbo for romsta Done PS8, Line 66: /* Enable speed step. */ : msr = rdmsr(MSR_IA32_MISC_ENABLES); : msr.lo |= 1 << 16; : wrmsr(MSR_IA32_MISC_ENABLES, msr); > make as function so, mp init feature programming can use this. Done https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/cpu_… File src/soc/intel/common/block/cpu/cpu_early.c: Line 53: } > can we also have a int get_nominal_ratio() { Done PS8, Line 150: void set_P_State_to_turbo_ratio(void) > no camel case Done PS8, Line 170: set_P_State_to_nominal_TDP_ratio > same Done PS8, Line 189: set_P_State_to_max_non_turbo_ratio > -same Done https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/smmr… File src/soc/intel/common/block/cpu/smmrelocate.c: PS8, Line 34: #include "chip.h" > do we need? removed and optimized. https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/cpu.h: PS8, Line 25: > one tab less? Done https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/msr.h: PS8, Line 47: > one tab less Done PS8, Line 53: 0x40 > (1 << 6) Done -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Use CPU common code
by Barnali Sarkar (Code Review) 25 May '17

25 May '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/19566 ) Change subject: soc/intel/skylake: Use CPU common code ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/19566/6/src/soc/intel/skylake/bootblock/rep… File src/soc/intel/skylake/bootblock/report_platform.c: PS6, Line 23: #include <intelblocks/cpu.h> > order Done -- To view, visit https://review.coreboot.org/19566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/apollolake: Use CPU common code
by Barnali Sarkar (Code Review) 25 May '17

25 May '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/19827 ) Change subject: soc/intel/apollolake: Use CPU common code ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/19827/2/src/soc/intel/apollolake/Makefile.i… File src/soc/intel/apollolake/Makefile.inc: PS2, Line 97: CPPFLAGS_common += -I$(src)/soc/intel/apollolake > why we need this will remove https://review.coreboot.org/#/c/19827/2/src/soc/intel/apollolake/include/so… File src/soc/intel/apollolake/include/soc/cpu.h: PS2, Line 33: define BASE_CLOCK_MHZ 100 > bclk is there at common code will remove from here PS2, Line 39: #define APL_BURST_MODE_DISABLE 0x40 > already there will remove from here -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/apollolake: Use CPU common code
by Barnali Sarkar (Code Review) 25 May '17

25 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19827 to look at the new patch set (#4). Change subject: soc/intel/apollolake: Use CPU common code ...................................................................... soc/intel/apollolake: Use CPU common code This patch uses common CPU Model library. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/include/soc/cpu.h M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/tsc_freq.c 6 files changed, 20 insertions(+), 172 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/19827/4 -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common CPU code
by Barnali Sarkar (Code Review) 25 May '17

25 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19540 to look at the new patch set (#10). Change subject: soc/intel/common/block: Add Intel common CPU code ...................................................................... soc/intel/common/block: Add Intel common CPU code Create Intel Common CPU Model support code which provides various CPU related APIs which are common over Intel Processor families. Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/cpu.c A src/soc/intel/common/block/cpu/cpu_early.c A src/soc/intel/common/block/cpu/smmrelocate.c A src/soc/intel/common/block/include/intelblocks/cpu.h M src/soc/intel/common/block/include/intelblocks/msr.h A src/soc/intel/common/block/include/intelblocks/smm.h 8 files changed, 977 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/19540/10 -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Use CPU common code
by Barnali Sarkar (Code Review) 25 May '17

25 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19566 to look at the new patch set (#8). Change subject: soc/intel/skylake: Use CPU common code ...................................................................... soc/intel/skylake: Use CPU common code This patch uses common CPU Model library. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/cpu_info.c M src/soc/intel/skylake/include/fsp11/soc/ramstage.h M src/soc/intel/skylake/include/fsp20/soc/ramstage.h M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/smi.c D src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/tsc_freq.c 20 files changed, 45 insertions(+), 777 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/19566/8 -- To view, visit https://review.coreboot.org/19566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: lib/spd_bin: make SMBus SPD addresses an input
by Furquan Shaikh (Code Review) 25 May '17

25 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19915 ) Change subject: lib/spd_bin: make SMBus SPD addresses an input ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19915 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017