Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19256
to look at the new patch set (#6).
Change subject: mb/intel/dg43gt: Add mainboard
......................................................................
mb/intel/dg43gt: Add mainboard
This mainboard features is an G43 northbridge, ICH10 southbridge and
Winbond W83627dhg SuperI/O. This board is impossible to flash
internally with vendor bios (BIOS region is WP and other regions like
IFD and ME are read only and inaccessible respectively). Due to either
ICH10 or board layout it is also impossible to do ISP, which requires
desoldering flash chip. To make hacking more easy there is an empty
SPI header next to spi flash pads which can be hooked up to a SPI
flash.
What works:
* 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1);
* SATA
* Integrated GPU with option rom (extracted from a Gigabyte vendor
bios)
* PCI
* PEG slot with additional patches
* Reboot and S3 resume
* USB.
What does not work:
* GBE (requires descriptor);
* Lots of dmesg spam complaining about interrupt storm on HDMI
connector.
Not tested:
* Booting with descriptor (most likely fixes GBE);
* ME with descriptor;
* Sound;
* All the rest.
Not coreboot related problems:
* Flashing this board with vendor bios is a PITA and requires
desoldering flash chip;
* In situ programming is not possible.
TESTED with SeaBIOS and Linux 4.10.8
Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
A src/mainboard/intel/dg43gt/Kconfig
A src/mainboard/intel/dg43gt/Kconfig.name
A src/mainboard/intel/dg43gt/Makefile.inc
A src/mainboard/intel/dg43gt/acpi/ec.asl
A src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl
A src/mainboard/intel/dg43gt/acpi/platform.asl
A src/mainboard/intel/dg43gt/acpi/superio.asl
A src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl
A src/mainboard/intel/dg43gt/acpi_tables.c
A src/mainboard/intel/dg43gt/board_info.txt
A src/mainboard/intel/dg43gt/cmos.default
A src/mainboard/intel/dg43gt/cmos.layout
A src/mainboard/intel/dg43gt/cstates.c
A src/mainboard/intel/dg43gt/devicetree.cb
A src/mainboard/intel/dg43gt/dsdt.asl
A src/mainboard/intel/dg43gt/gpio.c
A src/mainboard/intel/dg43gt/hda_verb.c
A src/mainboard/intel/dg43gt/romstage.c
18 files changed, 901 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/19256/6
--
To view, visit https://review.coreboot.org/19256
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Gerrit-PatchSet: 6
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19253
to look at the new patch set (#5).
Change subject: sb/intel/i82801lx: Generate default fadt and madt
......................................................................
sb/intel/i82801lx: Generate default fadt and madt
Function copied from i82801gx with offsets fixed for i82801lx.
Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/southbridge/intel/i82801lx/Kconfig
M src/southbridge/intel/i82801lx/chip.h
M src/southbridge/intel/i82801lx/lpc.c
3 files changed, 150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/19253/5
--
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To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a
Gerrit-PatchSet: 5
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19249
to look at the new patch set (#3).
Change subject: sb/intel/i82801lx: Add correct PCI ids and change names
......................................................................
sb/intel/i82801lx: Add correct PCI ids and change names
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/southbridge/intel/i82801lx/Kconfig
M src/southbridge/intel/i82801lx/Makefile.inc
M src/southbridge/intel/i82801lx/acpi/audio.asl
R src/southbridge/intel/i82801lx/acpi/ich10.asl
M src/southbridge/intel/i82801lx/acpi/lpc.asl
M src/southbridge/intel/i82801lx/acpi/pci.asl
M src/southbridge/intel/i82801lx/acpi/usb.asl
M src/southbridge/intel/i82801lx/chip.h
M src/southbridge/intel/i82801lx/dmi_setup.c
M src/southbridge/intel/i82801lx/early_init.c
M src/southbridge/intel/i82801lx/early_smbus.c
M src/southbridge/intel/i82801lx/hdaudio.c
R src/southbridge/intel/i82801lx/i82801lx.c
R src/southbridge/intel/i82801lx/i82801lx.h
M src/southbridge/intel/i82801lx/lpc.c
M src/southbridge/intel/i82801lx/pci.c
M src/southbridge/intel/i82801lx/pcie.c
M src/southbridge/intel/i82801lx/sata.c
M src/southbridge/intel/i82801lx/smbus.c
M src/southbridge/intel/i82801lx/smbus.h
M src/southbridge/intel/i82801lx/smi.c
M src/southbridge/intel/i82801lx/smihandler.c
M src/southbridge/intel/i82801lx/thermal.c
M src/southbridge/intel/i82801lx/usb_ehci.c
24 files changed, 141 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19249/3
--
To view, visit https://review.coreboot.org/19249
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19248
to look at the new patch set (#3).
Change subject: sb/intel/i82801lx: Copy i82801ix
......................................................................
sb/intel/i82801lx: Copy i82801ix
Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
A src/southbridge/intel/i82801lx/Kconfig
A src/southbridge/intel/i82801lx/Makefile.inc
A src/southbridge/intel/i82801lx/acpi/audio.asl
A src/southbridge/intel/i82801lx/acpi/globalnvs.asl
A src/southbridge/intel/i82801lx/acpi/ich9.asl
A src/southbridge/intel/i82801lx/acpi/irqlinks.asl
A src/southbridge/intel/i82801lx/acpi/lpc.asl
A src/southbridge/intel/i82801lx/acpi/pci.asl
A src/southbridge/intel/i82801lx/acpi/pcie.asl
A src/southbridge/intel/i82801lx/acpi/pcie_port.asl
A src/southbridge/intel/i82801lx/acpi/sata.asl
A src/southbridge/intel/i82801lx/acpi/sleepstates.asl
A src/southbridge/intel/i82801lx/acpi/smbus.asl
A src/southbridge/intel/i82801lx/acpi/usb.asl
A src/southbridge/intel/i82801lx/bootblock.c
A src/southbridge/intel/i82801lx/chip.h
A src/southbridge/intel/i82801lx/dmi_setup.c
A src/southbridge/intel/i82801lx/early_init.c
A src/southbridge/intel/i82801lx/early_smbus.c
A src/southbridge/intel/i82801lx/hdaudio.c
A src/southbridge/intel/i82801lx/i82801ix.c
A src/southbridge/intel/i82801lx/i82801ix.h
A src/southbridge/intel/i82801lx/lpc.c
A src/southbridge/intel/i82801lx/nvs.h
A src/southbridge/intel/i82801lx/pci.c
A src/southbridge/intel/i82801lx/pcie.c
A src/southbridge/intel/i82801lx/sata.c
A src/southbridge/intel/i82801lx/smbus.c
A src/southbridge/intel/i82801lx/smbus.h
A src/southbridge/intel/i82801lx/smi.c
A src/southbridge/intel/i82801lx/smihandler.c
A src/southbridge/intel/i82801lx/thermal.c
A src/southbridge/intel/i82801lx/usb_ehci.c
33 files changed, 5,972 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/19248/3
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19559 )
Change subject: mainboard/google/poppy: Enable MODE_CHANGE event in SCI_MASK
......................................................................
mainboard/google/poppy: Enable MODE_CHANGE event in SCI_MASK
This is required to ensure that SCI is generated whenever a host event
is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs,
eSPI SCI is generated which results in kernel handler reading host
event from the EC and thus causes the wake pin to be de-asserted.
BUG=b:37223093
TEST=Verified that wake from mode change event works fine in suspend
mode and there is no interrupt storm for GPE SCI after resume.
Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: https://review.coreboot.org/19559
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Jenny Tc <jenny.tc(a)intel.com>
---
M src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
Jenny Tc: Looks good to me, but someone else must approve
Paul Menzel: Looks good to me, but someone else must approve
Duncan Laurie: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h
index 8be83f3..5d6cf4c 100644
--- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h
@@ -35,6 +35,7 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
#define MAINBOARD_EC_SMI_EVENTS \
--
To view, visit https://review.coreboot.org/19559
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: merged
Gerrit-Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>