coreboot-gerrit May 2017

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Change in coreboot[master]: soc/intel/skylake: Enable SATA ports
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19553 ) Change subject: soc/intel/skylake: Enable SATA ports ...................................................................... soc/intel/skylake: Enable SATA ports The current implementation is incorrect and is actually disabling the ports. Fixes that. BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that we can boot from SATA SSD. Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Signed-off-by: Shelley Chen <shchen(a)chromium.org> Reviewed-on: https://review.coreboot.org/19553 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/soc/intel/skylake/sata.c 1 file changed, 6 insertions(+), 4 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c index c110436..277d6da 100644 --- a/src/soc/intel/skylake/sata.c +++ b/src/soc/intel/skylake/sata.c @@ -40,14 +40,16 @@ static void sata_final(device_t dev) { void *ahcibar = get_ahci_bar(); - u8 port_impl; + u32 port_impl, temp; dev = PCH_DEV_SATA; /* Read Ports Implemented (GHC_PI) */ - port_impl = read32(ahcibar + 0x0c); - port_impl = ~port_impl & 0x07; + port_impl = read32(ahcibar + 0x0c) & 0x07; /* Port enable */ - pci_write_config8(dev, 0x92, port_impl); + temp = pci_read_config32(dev, 0x92); + temp |= port_impl; + pci_write_config32(dev, 0x92, temp); + } static struct device_operations sata_ops = { -- To view, visit https://review.coreboot.org/19553 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/fizz: Enable devices under pci 1c.0
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19533 ) Change subject: google/fizz: Enable devices under pci 1c.0 ...................................................................... google/fizz: Enable devices under pci 1c.0 Turn on device 1c.0 in order to enable devices under it. BUG=b:37486021, b:35775024 BRANCH=None TEST=Boot from NVMe Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe Signed-off-by: Shelley Chen <shchen(a)chromium.org> Reviewed-on: https://review.coreboot.org/19533 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index e18b767..ff2ec7f 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -228,7 +228,7 @@ device pci 19.1 on end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 on end # PCI Express Port 3 for LAN device pci 1c.3 on -- To view, visit https://review.coreboot.org/19533 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intelmetool: handle failures to mmap MEI memory
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19562 ) Change subject: intelmetool: handle failures to mmap MEI memory ...................................................................... intelmetool: handle failures to mmap MEI memory Fixes crashes when there is an error mapping memory. Error mapping physical memory 0x0000004275159040 [0x4000] ERRNO=1 Segmentation fault (core dumped) Change-Id: I5becc0c2870dd97297c4e8d1b101b95b31792ca7 Signed-off-by: Paul Wise <pabs3(a)bonedaddy.net> Reviewed-on: https://review.coreboot.org/19562 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M util/intelmetool/intelmetool.c M util/intelmetool/me.c 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Philipp Deppenwiese: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index 62dc4d9..11c2120 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -83,6 +83,10 @@ uint8_t *dump; dump = map_physical_exact((off_t)me_clone, (void *)me_clone, 0x2000000); + if (dump == NULL) { + printf("Could not map ME memory\n"); + return; + } zeroit(dump, 0x2000000); printf("Send magic command for memory clone\n"); @@ -210,6 +214,12 @@ rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; rcba = map_physical((off_t)rcba_phys, size); + if (rcba == NULL) { + printf("Could not map MEI PCI device memory\n"); + pci_free_dev(sb); + pci_cleanup(pacc); + return 1; + } //printf("RCBA at 0x%08" PRIx32 "\n", (uint32_t)rcba_phys); fd2 = *(uint32_t *)(rcba + FD2); diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index da5fb716..8c703a3 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -581,6 +581,10 @@ mei_base_address = dev->base_addr[0] & ~0xf; pagerounded = mei_base_address & ~0xfff; mei_mmap = map_physical(pagerounded, 0x2000) + mei_base_address - pagerounded; + if (mei_mmap == NULL) { + printf("Could not map ME setup memory\n"); + return 1; + } /* Ensure Memory and Bus Master bits are set */ reg32 = pci_read_long(dev, PCI_COMMAND); -- To view, visit https://review.coreboot.org/19562 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I5becc0c2870dd97297c4e8d1b101b95b31792ca7 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Paul Wise (Debian) <pabs(a)debian.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intelmetool: free sb pci_dev struct allocated by pci_get_dev()
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19561 ) Change subject: intelmetool: free sb pci_dev struct allocated by pci_get_dev() ...................................................................... intelmetool: free sb pci_dev struct allocated by pci_get_dev() This fixes a memory leak in the activate_me() function. Change-Id: I011b2f96122d8f88aed121352afe3f0d41edef60 Signed-off-by: Paul Wise <pabs3(a)bonedaddy.net> Reviewed-on: https://review.coreboot.org/19561 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M util/intelmetool/intelmetool.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Philipp Deppenwiese: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index d6fd0fe..62dc4d9 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -220,6 +220,7 @@ printf("MEI not hidden on PCI, checking if visible\n"); } + pci_free_dev(sb); pci_cleanup(pacc); return 0; -- To view, visit https://review.coreboot.org/19561 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I011b2f96122d8f88aed121352afe3f0d41edef60 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Paul Wise (Debian) <pabs(a)debian.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intelmetool: Print strerror() results for mmap errors
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19560 ) Change subject: intelmetool: Print strerror() results for mmap errors ...................................................................... intelmetool: Print strerror() results for mmap errors These are more human readable for folks not familiar with errno values. Change-Id: I21352a00b583163472ccd3302a83adf1f8396c61 Signed-off-by: Paul Wise <pabs3(a)bonedaddy.net> Reviewed-on: https://review.coreboot.org/19560 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M util/intelmetool/mmap.c 1 file changed, 5 insertions(+), 4 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Philipp Deppenwiese: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/intelmetool/mmap.c b/util/intelmetool/mmap.c index 041aac9..2462b22 100644 --- a/util/intelmetool/mmap.c +++ b/util/intelmetool/mmap.c @@ -15,6 +15,7 @@ #include "mmap.h" #include <errno.h> +#include <string.h> #ifndef __DARWIN__ int fd_mem; @@ -28,8 +29,8 @@ if (virt_addr == MAP_FAILED) { err = errno; - printf("Error mapping physical memory 0x%016jd [0x%zx] ERRNO=%d\n", - (intmax_t)phys_addr, len, err); + printf("Error mapping physical memory 0x%016jd [0x%zx] ERRNO=%d %s\n", + (intmax_t)phys_addr, len, err, strerror(err)); return NULL; } @@ -44,8 +45,8 @@ if (virt_addr == MAP_FAILED) { err = errno; - printf("Error mapping physical memory 0x%016jd [0x%zx] ERRNO=%d\n", - (intmax_t)phys_addr, len, err); + printf("Error mapping physical memory 0x%016jd [0x%zx] ERRNO=%d %s\n", + (intmax_t)phys_addr, len, err, strerror(err)); return NULL; } -- To view, visit https://review.coreboot.org/19560 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I21352a00b583163472ccd3302a83adf1f8396c61 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Paul Wise (Debian) <pabs(a)debian.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]soc/intel/common/block: Add Intel PMC support
by Shaunak Saha (Code Review) 06 May '17

06 May '17

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/19349 ) Change subject: [WIP]soc/intel/common/block: Add Intel PMC support ...................................................................... Patch Set 4: I am working on your comments. Changing the code and testing it on various soc's before pushing the change. Brandon was trying to push a patch which depends on these pmc changes and so patchset 4 got pushed by him. -- To view, visit https://review.coreboot.org/19349 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic3d96fc23a98c30e8ea0969a7be09d217eeaa889 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/galileo: Add SD controller configuration
by build bot (Jenkins) (Code Review) 06 May '17

06 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19212 ) Change subject: mainboard/intel/galileo: Add SD controller configuration ...................................................................... Patch Set 12: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53369/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9175/ : SUCCESS -- To view, visit https://review.coreboot.org/19212 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4 Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/quark: Add SD/MMC test support
by build bot (Jenkins) (Code Review) 06 May '17

06 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19211 ) Change subject: soc/intel/quark: Add SD/MMC test support ...................................................................... Patch Set 12: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53368/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9174/ : SUCCESS -- To view, visit https://review.coreboot.org/19211 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I72785f0dcd466c05c1385cef166731219b583551 Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/quark: Add SD/MMC test support
by Lee Leahy (Code Review) 06 May '17

06 May '17

Lee Leahy has posted comments on this change. ( https://review.coreboot.org/19211 ) Change subject: soc/intel/quark: Add SD/MMC test support ...................................................................... Patch Set 12: (8 comments) https://review.coreboot.org/#/c/19211/11/src/soc/intel/quark/Kconfig File src/soc/intel/quark/Kconfig: PS11, Line 317: User must : also enable one or both of DRIVERS_STORAGE_SD or DRIVERS_STORAGE_MMC. > Should we have a 'depends on' statement for these instead of just adding it A "depends on" is necessary since the intent is to make it easy to test on all Quark boards. https://review.coreboot.org/#/c/19211/11/src/soc/intel/quark/Makefile.inc File src/soc/intel/quark/Makefile.inc: PS11, Line 65: > Why so many stages? Is it doing useful things in all of them? It seems li Removed extra stages and moved into romstage and ramstage https://review.coreboot.org/#/c/19211/11/src/soc/intel/quark/storage_test.c File src/soc/intel/quark/storage_test.c: PS11, Line 164: E) > I think we got rid of CONFIG_CAR_DRIVERS_STORAGE, so we should just be able Removed CONFIG_CAR_DRIVERS_STORAGE PS11, Line 170: RT((struct sd > We're in a !ENV_BOOTBLOCK #if section here, so this can't be true. Same wi Removed ENV_BOOTBLOCK PS11, Line 194: err); > For these printk statements, you could do something like this in console.h. Defined LOG_DEBUG as shown above and defined STORAGE_DEBUG as BIOS_DEBUG PS11, Line 219: name = storage_partition_name(media > No need for this if when calling display log, as everything in the function Done PS11, Line 232: > BIOS_SPEW? Using STORAGE_DEBUG to output at same level as LOG_DEBUG. PS11, Line 247: tr_t)(media + 1) + 0x7) & > again, i think we got rid of this. Done -- To view, visit https://review.coreboot.org/19211 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I72785f0dcd466c05c1385cef166731219b583551 Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: mainboard/intel/galileo: Add SD controller configuration
by Lee Leahy (Code Review) 06 May '17

06 May '17

Lee Leahy has posted comments on this change. ( https://review.coreboot.org/19212 ) Change subject: mainboard/intel/galileo: Add SD controller configuration ...................................................................... Patch Set 11: (3 comments) https://review.coreboot.org/#/c/19212/11/src/mainboard/intel/galileo/Kconfig File src/mainboard/intel/galileo/Kconfig: Line 25: > add select DRIVERS_STORAGE_SD here, or default it to on below? Added DRIVERS_STORAGE_SD below PS11, Line 182: ENABLE_SD_TESTING > if not adding the select above, add depends on DRIVERS_STORAGE_SD here? Done https://review.coreboot.org/#/c/19212/11/src/mainboard/intel/galileo/Makefi… File src/mainboard/intel/galileo/Makefile.inc: PS11, Line 22: y > $(CONFIG_DRIVERS_STORAGE_SD)? Done -- To view, visit https://review.coreboot.org/19212 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017