coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/amd/pi/00730F01: Initialize IOMMU device
by build bot (Jenkins) (Code Review) 06 May '17

06 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/15186 ) Change subject: nb/amd/pi/00730F01: Initialize IOMMU device ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/53373/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/9179/ : SUCCESS -- To view, visit https://review.coreboot.org/15186 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I12d3ed35770ee06626f884db23004652084c88c0 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Dave Frodin <dave.frodin(a)se-eng.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/scarlet: Enable innolux, p079zca MIPI panel
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19597 ) Change subject: google/scarlet: Enable innolux,p079zca MIPI panel ...................................................................... Patch Set 1: Code-Review+2 Apologies - The original version of this patch at https://review.coreboot.org/19476 was merged before the previous patch in the train was ready. I reverted that submission to fix the build, and this is the replacement patch. -- To view, visit https://review.coreboot.org/19597 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I059a47661aef97cb5954281fecacdba1f3dbf983 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-HasComments: No

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Change in coreboot[master]: google/scarlet: Enable innolux, p079zca MIPI panel
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has uploaded a new change for review. ( https://review.coreboot.org/19597 ) Change subject: google/scarlet: Enable innolux,p079zca MIPI panel ...................................................................... google/scarlet: Enable innolux,p079zca MIPI panel TEST=Boot from scarlet, and mipi panel work Original-Signed-off-by: Nickey Yang <nickey.yang(a)rock-chips.com> Original-Reviewed-on: https://review.coreboot.org/19476 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I059a47661aef97cb5954281fecacdba1f3dbf983 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/gru/devicetree.scarlet.cb 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/19597/1 diff --git a/src/mainboard/google/gru/devicetree.scarlet.cb b/src/mainboard/google/gru/devicetree.scarlet.cb index 2c31654..e5a9b31 100644 --- a/src/mainboard/google/gru/devicetree.scarlet.cb +++ b/src/mainboard/google/gru/devicetree.scarlet.cb @@ -15,6 +15,16 @@ chip soc/rockchip/rk3399 device cpu_cluster 0 on end - register "vop_mode" = "VOP_MODE_NONE" + register "vop_mode" = "VOP_MODE_MIPI" register "framebuffer_bits_per_pixel" = "32" + register "panel_pixel_clock" = "56900" + register "panel_refresh" = "60" + register "panel_ha" = "768" + register "panel_hbl" = "120" + register "panel_hso" = "40" + register "panel_hspw" = "40" + register "panel_va" = "1024" + register "panel_vbl" = "44" + register "panel_vso" = "20" + register "panel_vspw" = "4" end -- To view, visit https://review.coreboot.org/19597 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I059a47661aef97cb5954281fecacdba1f3dbf983 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: Revert "google/scarlet: Enable innolux, p079zca MIPI panel"
by build bot (Jenkins) (Code Review) 06 May '17

06 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19596 ) Change subject: Revert "google/scarlet: Enable innolux,p079zca MIPI panel" ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53371/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9177/ : SUCCESS -- To view, visit https://review.coreboot.org/19596 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iaca6d43cc8fc0959565d5d151a330c0c7ba38309 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: Revert "google/scarlet: Enable innolux, p079zca MIPI panel"
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has uploaded a new change for review. ( https://review.coreboot.org/19596 ) Change subject: Revert "google/scarlet: Enable innolux,p079zca MIPI panel" ...................................................................... Revert "google/scarlet: Enable innolux,p079zca MIPI panel" This reverts commit 39b633b26d6d4cf185fbbdd5a256d0665409bd5b. Commit was accidentally pushed too early and broke the tree. I'll repush the original. Change-Id: Iaca6d43cc8fc0959565d5d151a330c0c7ba38309 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/gru/devicetree.scarlet.cb 1 file changed, 1 insertion(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19596/1 diff --git a/src/mainboard/google/gru/devicetree.scarlet.cb b/src/mainboard/google/gru/devicetree.scarlet.cb index e5a9b31..2c31654 100644 --- a/src/mainboard/google/gru/devicetree.scarlet.cb +++ b/src/mainboard/google/gru/devicetree.scarlet.cb @@ -15,16 +15,6 @@ chip soc/rockchip/rk3399 device cpu_cluster 0 on end - register "vop_mode" = "VOP_MODE_MIPI" + register "vop_mode" = "VOP_MODE_NONE" register "framebuffer_bits_per_pixel" = "32" - register "panel_pixel_clock" = "56900" - register "panel_refresh" = "60" - register "panel_ha" = "768" - register "panel_hbl" = "120" - register "panel_hso" = "40" - register "panel_hspw" = "40" - register "panel_va" = "1024" - register "panel_vbl" = "44" - register "panel_vso" = "20" - register "panel_vspw" = "4" end -- To view, visit https://review.coreboot.org/19596 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iaca6d43cc8fc0959565d5d151a330c0c7ba38309 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by build bot (Jenkins) (Code Review) 06 May '17

06 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18993 ) Change subject: mainboard: Add ASRock G41C-GS ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53370/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9176/ : SUCCESS -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by Arthur Heymans (Code Review) 06 May '17

06 May '17

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18993 to look at the new patch set (#6). Change subject: mainboard: Add ASRock G41C-GS ...................................................................... mainboard: Add ASRock G41C-GS Start-point is Gigabyte GA-G41M-ES2L. This board features a G41 northbridge and an ICH7 southbridge. This board has slots for both DDR2 and DDR3 (cannot run concurrently though) but only DDR2 is implemented in coreboot. The SPI flash resides in a DIP-8 socket. Tested and working: * DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky with assymetric dimm setups); * 3,5" IDE; * SATA; * PCIe x16 (with some patches up for review); * Uart, PS2 Keyboard; * USB, ethernet, audio; * Native graphic init; * Fan control; * Reboot, poweroff; * Flashrom (vendor and coreboot). Tested but fails: * Raminit on resume from S3 (might work with SIO enabling 3VSBSW#); * DDR3 (not implemented in coreboot). Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0. Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/g41c-gs/Kconfig A src/mainboard/asrock/g41c-gs/Kconfig.name A src/mainboard/asrock/g41c-gs/Makefile.inc A src/mainboard/asrock/g41c-gs/acpi/ec.asl A src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl A src/mainboard/asrock/g41c-gs/acpi/platform.asl A src/mainboard/asrock/g41c-gs/acpi/superio.asl A src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl A src/mainboard/asrock/g41c-gs/acpi_tables.c A src/mainboard/asrock/g41c-gs/board_info.txt A src/mainboard/asrock/g41c-gs/cmos.default A src/mainboard/asrock/g41c-gs/cmos.layout A src/mainboard/asrock/g41c-gs/cstates.c A src/mainboard/asrock/g41c-gs/devicetree.cb A src/mainboard/asrock/g41c-gs/dsdt.asl A src/mainboard/asrock/g41c-gs/gpio.c A src/mainboard/asrock/g41c-gs/hda_verb.c A src/mainboard/asrock/g41c-gs/romstage.c 18 files changed, 912 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/18993/6 -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/scarlet: Enable innolux, p079zca MIPI panel
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19476 ) Change subject: google/scarlet: Enable innolux,p079zca MIPI panel ...................................................................... google/scarlet: Enable innolux,p079zca MIPI panel TEST=Boot from scarlet, and mipi panel work Change-Id: Id5f81867ea50f72cc0bc13074627134e0dc198ba Signed-off-by: Nickey Yang <nickey.yang(a)rock-chips.com> Reviewed-on: https://review.coreboot.org/19476 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/gru/devicetree.scarlet.cb 1 file changed, 11 insertions(+), 1 deletion(-) Approvals: Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/gru/devicetree.scarlet.cb b/src/mainboard/google/gru/devicetree.scarlet.cb index 2c31654..e5a9b31 100644 --- a/src/mainboard/google/gru/devicetree.scarlet.cb +++ b/src/mainboard/google/gru/devicetree.scarlet.cb @@ -15,6 +15,16 @@ chip soc/rockchip/rk3399 device cpu_cluster 0 on end - register "vop_mode" = "VOP_MODE_NONE" + register "vop_mode" = "VOP_MODE_MIPI" register "framebuffer_bits_per_pixel" = "32" + register "panel_pixel_clock" = "56900" + register "panel_refresh" = "60" + register "panel_ha" = "768" + register "panel_hbl" = "120" + register "panel_hso" = "40" + register "panel_hspw" = "40" + register "panel_va" = "1024" + register "panel_vbl" = "44" + register "panel_vso" = "20" + register "panel_vspw" = "4" end -- To view, visit https://review.coreboot.org/19476 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Id5f81867ea50f72cc0bc13074627134e0dc198ba Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey.yang(a)rock-chips.com

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Change in coreboot[master]: mainboard/google/sand: Update DPTF parameters provided from ...
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19538 ) Change subject: mainboard/google/sand: Update DPTF parameters provided from thermal team ...................................................................... mainboard/google/sand: Update DPTF parameters provided from thermal team Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:83, critial point:99 TSR0 passive point:60, critial point:70 TSR1 passive point:50, critial point:90 TSR2 passive point:77, critial point:90 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 4W, max to 12W, and step size to 0.2W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 5secs Change CPU Effect on Temp Sensor 0 sample rate to 60secs The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs Change Charger Effect on Temp Sensor 2 sample rate to 30secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=None TEST=build and boot on electro dut Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db Signed-off-by: Katherine Hsieh <Katherine.Hsieh(a)quantatw.com> Reviewed-on: https://review.coreboot.org/19538 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl 1 file changed, 70 insertions(+), 2 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl index fe4bf01..e90b159 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl @@ -14,5 +14,73 @@ * GNU General Public License for more details. */ -/* Use the one from baseboard for now until the real testing is done. */ -#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 83 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 60 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 50 +#define DPTF_TSR1_CRITICAL 90 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 77 +#define DPTF_TSR2_CRITICAL 90 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 4000, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) -- To view, visit https://review.coreboot.org/19538 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Katherine Hsieh <Katherine.Hsieh(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: blobtool/ifd-x200.set: Fix flashmap0 NR
by Martin Roth (Code Review) 06 May '17

06 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19565 ) Change subject: blobtool/ifd-x200.set: Fix flashmap0 NR ...................................................................... blobtool/ifd-x200.set: Fix flashmap0 NR NR indicates the last non empty region, which in this case is GbE (region3). Needed for flashrom ifd layout support. Change-Id: I3f4dcb0d41718dd176982679f8e045681fd3f486 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/19565 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M util/blobtool/ifd-x200.set 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/util/blobtool/ifd-x200.set b/util/blobtool/ifd-x200.set index 2894562..255eb88 100644 --- a/util/blobtool/ifd-x200.set +++ b/util/blobtool/ifd-x200.set @@ -24,7 +24,7 @@ "flmap0_nc" = 0x0, "flmap0_reserved0" = 0x0, "flmap0_frba" = 0x4, - "flmap0_nr" = 0x2, + "flmap0_nr" = 0x3, "flmap0_reserved1" = 0x0, "flmap1_fmba" = 0x6, "flmap1_nm" = 0x2, -- To view, visit https://review.coreboot.org/19565 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I3f4dcb0d41718dd176982679f8e045681fd3f486 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit May 2017