coreboot-gerrit May 2017

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Change in coreboot[master]: mainboard/intel/galileo: Add SD controller configuration
by Lee Leahy (Code Review) 06 May '17

06 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19212 to look at the new patch set (#12). Change subject: mainboard/intel/galileo: Add SD controller configuration ...................................................................... mainboard/intel/galileo: Add SD controller configuration Configure the SD controller to handle the SD card slot. * Galileo supports a removable SD card slot. * Set SD card initialization frequency to 100 MHz. * Set default removable delays. * Build SD/MMC components by default TEST=Build and run on Galileo Gen2 Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- M src/mainboard/intel/galileo/Kconfig M src/mainboard/intel/galileo/Makefile.inc A src/mainboard/intel/galileo/sd.c 3 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/19212/12 -- To view, visit https://review.coreboot.org/19212 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4 Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/quark: Add SD/MMC test support
by Lee Leahy (Code Review) 06 May '17

06 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19211 to look at the new patch set (#12). Change subject: soc/intel/quark: Add SD/MMC test support ...................................................................... soc/intel/quark: Add SD/MMC test support The SD/MMC test support consists of: * Add Kconfig value to enable the SD/MMC test support. * Add Kconfig value to enable the logging support. * Add SD/MMC controller init code and read block 0 from each partition. * Add logging code to snapshot the transactions with the SD/MMC device. * Add eMMC driver for ramstage to call test code. * Add romstage code to call test code. * Add bootblock code to call test code. TEST=Build and run on Galileo Gen2 Change-Id: I72785f0dcd466c05c1385cef166731219b583551 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- M src/soc/intel/quark/Kconfig M src/soc/intel/quark/Makefile.inc M src/soc/intel/quark/include/soc/iomap.h M src/soc/intel/quark/include/soc/pci_devs.h A src/soc/intel/quark/include/soc/storage_test.h M src/soc/intel/quark/romstage/fsp2_0.c A src/soc/intel/quark/sd.c A src/soc/intel/quark/storage_test.c 8 files changed, 403 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/19211/12 -- To view, visit https://review.coreboot.org/19211 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I72785f0dcd466c05c1385cef166731219b583551 Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/d510mo: Configure clockgen
by build bot (Jenkins) (Code Review) 06 May '17

06 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19595 ) Change subject: mb/intel/d510mo: Configure clockgen ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53367/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9173/ : SUCCESS -- To view, visit https://review.coreboot.org/19595 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/i82801gx: Make smbus block r/w functions available ...
by build bot (Jenkins) (Code Review) 06 May '17

06 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19594 ) Change subject: sb/intel/i82801gx: Make smbus block r/w functions available in romstage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53366/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9172/ : SUCCESS -- To view, visit https://review.coreboot.org/19594 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0a06178d2474ce65972de157cb437b42f3354da0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/intel/d510mo: Configure clockgen
by Arthur Heymans (Code Review) 06 May '17

06 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19595 ) Change subject: mb/intel/d510mo: Configure clockgen ...................................................................... mb/intel/d510mo: Configure clockgen Configuring the clockgen like vendor bios fixes the issue where the display wobbles from left to right on the analog VGA output. Note: This seems to be common issue/requirement on Intel devices from that generation (also happens on dg43gt). TESTED on Intel D510MO. Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/d510mo/romstage.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/19595/1 diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 3209d81..16e2b28 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -99,6 +99,8 @@ void mainboard_romstage_entry(unsigned long bist) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; + u8 clockgen_block[13] = {0x61, 0xd9, 0xfe, 0xff, 0xff, 0x00, 0x00, + 0x01, 0x03, 0x25, 0x83, 0x17, 0x0d}; if (bist == 0) enable_lapic(); @@ -116,6 +118,8 @@ report_bist_failure(bist); enable_smbus(); + smbus_block_write(0x69, 0, 13, clockgen_block); + pineview_early_initialization(); post_code(0x30); -- To view, visit https://review.coreboot.org/19595 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: sb/intel/i82801gx: Make smbus block r/w functions available ...
by Arthur Heymans (Code Review) 06 May '17

06 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19594 ) Change subject: sb/intel/i82801gx: Make smbus block r/w functions available in romstage ...................................................................... sb/intel/i82801gx: Make smbus block r/w functions available in romstage Those are needed to reconfigure the clockgen on smbus offset 0x69. Change-Id: I0a06178d2474ce65972de157cb437b42f3354da0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/19594/1 diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 5d204e9..bb5caf5 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -59,3 +59,14 @@ { return do_i2c_block_read(SMBUS_IO_BASE, device, offset, bytes, buf); } + +int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) +{ + return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); +} + +int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, + const u8 *buf) +{ + return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d1c861d..b3c1b48 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -52,6 +52,9 @@ int smbus_read_byte(unsigned int device, unsigned int address); int i2c_block_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); +int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); +int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, + const u8 *buf); int southbridge_detect_s3_resume(void); #endif #endif -- To view, visit https://review.coreboot.org/19594 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I0a06178d2474ce65972de157cb437b42f3354da0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mainboard/google/reef: Config needed GPIO for pull-up WA
by build bot (Jenkins) (Code Review) 06 May '17

06 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19577 ) Change subject: mainboard/google/reef: Config needed GPIO for pull-up WA ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53365/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9171/ : SUCCESS -- To view, visit https://review.coreboot.org/19577 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Freddy Paul <freddy.paul(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/reef: Config needed GPIO for pull-up WA
by build bot (Jenkins) (Code Review) 06 May '17

06 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19577 ) Change subject: mainboard/google/reef: Config needed GPIO for pull-up WA ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53364/ : SUCCESS -- To view, visit https://review.coreboot.org/19577 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Freddy Paul <freddy.paul(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/reef: Config needed GPIO for pull-up WA
by Lijian Zhao (Code Review) 06 May '17

06 May '17

Lijian Zhao has uploaded a new change for review. ( https://review.coreboot.org/19577 ) Change subject: mainboard/google/reef: Config needed GPIO for pull-up WA ...................................................................... mainboard/google/reef: Config needed GPIO for pull-up WA This change is needed to minimize circuit level stress, by adjusting circuit voltage for proper operation. For mem config GPIO changes: To avoid leakge as those pins have internal 20K pull and 3.3K pull down on mainboard, change internal pull up to none. BUG=b.37998248 TEST=Boot up into OS and enter s0ix. Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/reef/variants/baseboard/gpio.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/19577/8 diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 9155e66..5aa9f77 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -31,15 +31,15 @@ /* EMMC interface */ PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ - PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ - PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ - PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ - PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ - PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ - PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ - PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ - PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ - PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D4 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D5 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D6 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D7 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_CMD */ PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ /* SDIO -- unused. */ @@ -245,8 +245,8 @@ PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_MOSI_IO0 */ PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_GPI(GPIO_101, NONE, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, NONE, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK */ PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK_FB */ PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE), /* FST_SPI_CS2_N */ @@ -316,7 +316,7 @@ PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ /* LPSS_UART[0:2] */ - PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ + PAD_CFG_GPI(GPIO_38, NONE, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ /* Next 2 are straps. */ PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ @@ -324,7 +324,7 @@ PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ - PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ + PAD_CFG_GPI(GPIO_45, NONE, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ -- To view, visit https://review.coreboot.org/19577 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Freddy Paul <freddy.paul(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/dg43gt: Add mainboard
by Arthur Heymans (Code Review) 06 May '17

06 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19256 ) Change subject: mb/intel/dg43gt: Add mainboard ...................................................................... Patch Set 7: Needs to reconfigure clockgen to work fine on Analog output through DVI port. For this ICH10 patches need to be rebased on https://review.coreboot.org/#/c/19258/ (common smbus functions) to provide smbus_block_read/write to configure clockgen. -- To view, visit https://review.coreboot.org/19256 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017