Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19258
to look at the new patch set (#15).
Change subject: sb/intel/*: Use common SMBus functions
......................................................................
sb/intel/*: Use common SMBus functions
All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.
This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.
Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/sandybridge/raminit.c
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/bd82x6x/early_smbus.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/smbus.c
D src/southbridge/intel/bd82x6x/smbus.h
M src/southbridge/intel/common/Kconfig
M src/southbridge/intel/common/Makefile.inc
R src/southbridge/intel/common/smbus.c
A src/southbridge/intel/common/smbus.h
M src/southbridge/intel/fsp_bd82x6x/Kconfig
M src/southbridge/intel/fsp_i89xx/Kconfig
M src/southbridge/intel/fsp_i89xx/early_smbus.c
M src/southbridge/intel/fsp_i89xx/pch.h
D src/southbridge/intel/fsp_i89xx/smbus.h
M src/southbridge/intel/fsp_rangeley/Kconfig
M src/southbridge/intel/fsp_rangeley/early_smbus.c
M src/southbridge/intel/fsp_rangeley/smbus.c
D src/southbridge/intel/fsp_rangeley/smbus.h
M src/southbridge/intel/fsp_rangeley/soc.h
M src/southbridge/intel/i3100/Kconfig
M src/southbridge/intel/i3100/early_smbus.c
M src/southbridge/intel/i3100/smbus.c
D src/southbridge/intel/i3100/smbus.h
M src/southbridge/intel/i82371eb/Kconfig
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/smbus.c
D src/southbridge/intel/i82371eb/smbus.h
M src/southbridge/intel/i82801ax/Kconfig
M src/southbridge/intel/i82801ax/early_smbus.c
M src/southbridge/intel/i82801ax/i82801ax.h
M src/southbridge/intel/i82801ax/smbus.c
D src/southbridge/intel/i82801ax/smbus.h
M src/southbridge/intel/i82801bx/Kconfig
M src/southbridge/intel/i82801bx/early_smbus.c
M src/southbridge/intel/i82801bx/i82801bx.h
M src/southbridge/intel/i82801bx/smbus.c
D src/southbridge/intel/i82801bx/smbus.h
M src/southbridge/intel/i82801dx/Kconfig
M src/southbridge/intel/i82801dx/early_smbus.c
M src/southbridge/intel/i82801dx/i82801dx.h
D src/southbridge/intel/i82801dx/smbus.c
M src/southbridge/intel/i82801ex/Kconfig
M src/southbridge/intel/i82801ex/early_smbus.c
M src/southbridge/intel/i82801ex/smbus.c
D src/southbridge/intel/i82801ex/smbus.h
M src/southbridge/intel/i82801gx/Kconfig
M src/southbridge/intel/i82801gx/early_smbus.c
M src/southbridge/intel/i82801gx/i82801gx.h
M src/southbridge/intel/i82801gx/smbus.c
D src/southbridge/intel/i82801gx/smbus.h
M src/southbridge/intel/i82801ix/Kconfig
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801ix/i82801ix.h
M src/southbridge/intel/i82801ix/smbus.c
D src/southbridge/intel/i82801ix/smbus.h
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/ibexpeak/early_smbus.c
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/early_smbus.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/smbus.c
D src/southbridge/intel/lynxpoint/smbus.h
65 files changed, 237 insertions(+), 1,909 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19258/15
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Gerrit-PatchSet: 15
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19258 )
Change subject: sb/intel/*: Use common SMBus functions
......................................................................
Patch Set 14:
(3 comments)
https://review.coreboot.org/#/c/19258/10//COMMIT_MSG
Commit Message:
Line 11: implementations with a common file.
> Any reason why i82801dx is not touched?
forgot it.
its funny that it has smbus.c with supposedly ramstage functions but it is not even linked in...
Line 15: this function can reduce the time being spent to read SPD five-fold.
> Revisit kernel driver about these smbus/i2c block read functions. There was
command 6 does not seem to be used by the the i801 kernel driver...
https://review.coreboot.org/#/c/19258/14/src/southbridge/intel/common/smbus…
File src/southbridge/intel/common/smbus.c:
PS14, Line 95: /* poll for it to start */
: if (smbus_wait_until_active(smbus_base) < 0) {
: return -4;
: }
not sure if this is needed/desired...
--
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Gerrit-MessageType: comment
Gerrit-Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Gerrit-PatchSet: 14
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: Yes
Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19258
to look at the new patch set (#14).
Change subject: sb/intel/*: Use common SMBus functions
......................................................................
sb/intel/*: Use common SMBus functions
All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.
This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.
Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/sandybridge/raminit.c
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/bd82x6x/early_smbus.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/smbus.c
D src/southbridge/intel/bd82x6x/smbus.h
M src/southbridge/intel/common/Kconfig
M src/southbridge/intel/common/Makefile.inc
R src/southbridge/intel/common/smbus.c
A src/southbridge/intel/common/smbus.h
M src/southbridge/intel/fsp_bd82x6x/Kconfig
M src/southbridge/intel/fsp_bd82x6x/pch.h
M src/southbridge/intel/fsp_i89xx/Kconfig
M src/southbridge/intel/fsp_i89xx/early_smbus.c
M src/southbridge/intel/fsp_i89xx/pch.h
D src/southbridge/intel/fsp_i89xx/smbus.h
M src/southbridge/intel/fsp_rangeley/Kconfig
M src/southbridge/intel/fsp_rangeley/early_smbus.c
M src/southbridge/intel/fsp_rangeley/smbus.c
D src/southbridge/intel/fsp_rangeley/smbus.h
M src/southbridge/intel/fsp_rangeley/soc.h
M src/southbridge/intel/i3100/Kconfig
M src/southbridge/intel/i3100/early_smbus.c
M src/southbridge/intel/i3100/smbus.c
D src/southbridge/intel/i3100/smbus.h
M src/southbridge/intel/i82371eb/Kconfig
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/smbus.c
D src/southbridge/intel/i82371eb/smbus.h
M src/southbridge/intel/i82801ax/Kconfig
M src/southbridge/intel/i82801ax/early_smbus.c
M src/southbridge/intel/i82801ax/i82801ax.h
M src/southbridge/intel/i82801ax/smbus.c
D src/southbridge/intel/i82801ax/smbus.h
M src/southbridge/intel/i82801bx/Kconfig
M src/southbridge/intel/i82801bx/early_smbus.c
M src/southbridge/intel/i82801bx/i82801bx.h
M src/southbridge/intel/i82801bx/smbus.c
D src/southbridge/intel/i82801bx/smbus.h
M src/southbridge/intel/i82801dx/Kconfig
M src/southbridge/intel/i82801dx/early_smbus.c
M src/southbridge/intel/i82801dx/i82801dx.h
D src/southbridge/intel/i82801dx/smbus.c
M src/southbridge/intel/i82801ex/Kconfig
M src/southbridge/intel/i82801ex/early_smbus.c
M src/southbridge/intel/i82801ex/smbus.c
D src/southbridge/intel/i82801ex/smbus.h
M src/southbridge/intel/i82801gx/Kconfig
M src/southbridge/intel/i82801gx/early_smbus.c
M src/southbridge/intel/i82801gx/i82801gx.h
M src/southbridge/intel/i82801gx/smbus.c
D src/southbridge/intel/i82801gx/smbus.h
M src/southbridge/intel/i82801ix/Kconfig
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801ix/i82801ix.h
M src/southbridge/intel/i82801ix/smbus.c
D src/southbridge/intel/i82801ix/smbus.h
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/ibexpeak/early_smbus.c
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/early_smbus.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/smbus.c
D src/southbridge/intel/lynxpoint/smbus.h
66 files changed, 237 insertions(+), 1,934 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19258/14
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Gerrit-PatchSet: 14
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................
Patch Set 4: Verified+1
Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/53331/ : SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/9143/ : SUCCESS
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Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Gerrit-PatchSet: 4
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Gerrit-Branch: master
Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com>
Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com>
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19558 )
Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
Patch Set 4: Verified+1
Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/53330/ : SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/9142/ : SUCCESS
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Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19558
to look at the new patch set (#4).
Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
google/gru: support 800M/928M frequency for bob
The coreboot had no supported the different frequency for gru yet.
e.g:
we can't support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
So, in order to support the 800M and 928M ddr frequency for bob different
boards. We will use the ram_id and board_id to select the board on bob.
Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Signed-off-by: Caesar Wang <wxt(a)rock-chips.com>
---
M src/mainboard/google/gru/Kconfig
M src/mainboard/google/gru/Makefile.inc
M src/mainboard/google/gru/sdram_configs.c
M src/mainboard/google/gru/sdram_params_800/Makefile.inc
R src/mainboard/google/gru/sdram_params_928/Makefile.inc
R src/mainboard/google/gru/sdram_params_928/sdram-lpddr3-hynix-4GB.c
R src/mainboard/google/gru/sdram_params_928/sdram-lpddr3-micron-2GB.c
R src/mainboard/google/gru/sdram_params_928/sdram-lpddr3-micron-4GB.c
R src/mainboard/google/gru/sdram_params_928/sdram-lpddr3-samsung-2GB-24EB.c
R src/mainboard/google/gru/sdram_params_928/sdram-lpddr3-samsung-4GB-04EB.c
10 files changed, 32 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19558/4
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Gerrit-PatchSet: 4
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19557
to look at the new patch set (#4).
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................
rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to
modulate the frequency of the Silicon Creations’ Fractional PLL in order
to reduce EMI.
We need to turn the DPLL spread spectrum feature on to
reduce the EMI noise for DDR on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com>
Signed-off-by: Caesar Wang <wxt(a)rock-chips.com>
---
M src/mainboard/google/gru/Kconfig
M src/soc/rockchip/rk3399/Kconfig
M src/soc/rockchip/rk3399/clock.c
3 files changed, 96 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/19557/4
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Gerrit-PatchSet: 4
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19558 )
Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/19558/3/src/mainboard/google/gru/Kconfig
File src/mainboard/google/gru/Kconfig:
Line 97
> I think it might be nice to keep this option and use it for snprintf. In fa
I guess that's no
https://review.coreboot.org/#/c/19558/3/src/mainboard/google/gru/sdram_conf…
File src/mainboard/google/gru/sdram_configs.c:
Line 49: if (IS_ENABLED(CONFIG_BOARD_GOOGLE_BOB) && board_id() < 4)
> Rather than duplicating the file name list for all frequencies, why not jus
Then, can the CONFIG_GRU_SDRAM_FREQ be defined by the board_id()?
e.g:
I want to support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
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