Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18917
to look at the new patch set (#20).
Change subject: soc/intel/common/block:[WIP] Add GPIO common code
......................................................................
soc/intel/common/block:[WIP] Add GPIO common code
Here are some differences between APL and SKL GPIO registers
DW0:
PMODE: SKL[11:10] and APL[12:10]
RXTXENCFG: APL[21:20] and RSVD in SKL
PREGFRXSEL: APL[24] and RSVD in SKL
DW1: SKL only has INTSEL and TERM whereas APL and GLK share same bit
definitions for rest of the bits that are reserved in SKL
EVMAP and EVOUTEN are not there on SKL
DW1_PAD_TOL has been used only in SKL
Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
A src/soc/intel/common/block/gpio/Kconfig
A src/soc/intel/common/block/gpio/Makefile.inc
A src/soc/intel/common/block/gpio/gpio.c
A src/soc/intel/common/block/include/intelblocks/gpio.h
A src/soc/intel/common/block/include/intelblocks/gpio_defs.h
5 files changed, 842 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/18917/20
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c
Gerrit-PatchSet: 20
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Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19608 )
Change subject: soc/intel/skylake: Enable PARALLEL_MP_AP_WORK
......................................................................
soc/intel/skylake: Enable PARALLEL_MP_AP_WORK
With change a4b11e5c90 to perform CPU MP init before FSP-S init, MTRR
programming was moved to be performed after CPU init is done. However,
in order to allow callbacks after MP init, PARALLEL_MP_AP_WORK needs
to be enabled. Since this option was not selected, MTRR programming
always failed in ramstage for Skylake / Kaby Lake mainboards.
BUG=b:36656098
TEST=Verified 2500+ cycles of suspend resume on poppy.
Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
M src/soc/intel/skylake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/19608/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 515de91..fba6f7f 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -38,6 +38,7 @@
select NO_FIXED_XIP_ROM_SIZE
select MRC_SETTINGS_PROTECT
select PARALLEL_MP
+ select PARALLEL_MP_AP_WORK
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select PCIEXP_CLK_PM
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771
Gerrit-PatchSet: 1
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