coreboot-gerrit May 2017

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Change in coreboot[master]: mb/intel/dg43gt: Add mainboard
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19256 to look at the new patch set (#10). Change subject: mb/intel/dg43gt: Add mainboard ...................................................................... mb/intel/dg43gt: Add mainboard This mainboard features is an G43 northbridge, ICH10 southbridge and Winbond W83627dhg SuperI/O. This board is impossible to flash internally with vendor bios (BIOS region is WP and other regions like IFD and ME are read only and inaccessible respectively). Due to either ICH10 or board layout it is also impossible to do ISP, which requires desoldering flash chip. To make hacking more easy there is an empty SPI header next to spi flash pads which can be hooked up to a SPI flash. What works: * 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1); * SATA * Integrated GPU with option rom (extracted from a Gigabyte vendor bios) * PCI * PEG slot with additional patches * Reboot and S3 resume * USB. What does not work: * GBE (requires descriptor); * Lots of dmesg spam complaining about interrupt storm on HDMI connector; * NGI with analog on DVI port but that does not work (not enabled for this reason); * Analog on DVI port out is shaking, which is not the case with vendor BIOS. Not tested: * Booting with descriptor (most likely fixes GBE); * ME with descriptor; * Sound; * All the rest. Not coreboot related problems: * Flashing this board with vendor bios is a PITA and requires desoldering flash chip; * In situ programming is not possible. TESTED with SeaBIOS and Linux 4.10.8 Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/intel/dg43gt/Kconfig A src/mainboard/intel/dg43gt/Kconfig.name A src/mainboard/intel/dg43gt/Makefile.inc A src/mainboard/intel/dg43gt/acpi/ec.asl A src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl A src/mainboard/intel/dg43gt/acpi/platform.asl A src/mainboard/intel/dg43gt/acpi/superio.asl A src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl A src/mainboard/intel/dg43gt/acpi_tables.c A src/mainboard/intel/dg43gt/board_info.txt A src/mainboard/intel/dg43gt/cmos.default A src/mainboard/intel/dg43gt/cmos.layout A src/mainboard/intel/dg43gt/cstates.c A src/mainboard/intel/dg43gt/devicetree.cb A src/mainboard/intel/dg43gt/dsdt.asl A src/mainboard/intel/dg43gt/gpio.c A src/mainboard/intel/dg43gt/hda_verb.c A src/mainboard/intel/dg43gt/romstage.c 18 files changed, 894 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/19256/10 -- To view, visit https://review.coreboot.org/19256 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/dg43gt: Add mainboard
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19256 to look at the new patch set (#9). Change subject: mb/intel/dg43gt: Add mainboard ...................................................................... mb/intel/dg43gt: Add mainboard This mainboard features is an G43 northbridge, ICH10 southbridge and Winbond W83627dhg SuperI/O. This board is impossible to flash internally with vendor bios (BIOS region is WP and other regions like IFD and ME are read only and inaccessible respectively). Due to either ICH10 or board layout it is also impossible to do ISP, which requires desoldering flash chip. To make hacking more easy there is an empty SPI header next to spi flash pads which can be hooked up to a SPI flash. What works: * 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1); * SATA * Integrated GPU with option rom (extracted from a Gigabyte vendor bios) * PCI * PEG slot with additional patches * Reboot and S3 resume * USB. What does not work: * GBE (requires descriptor); * Lots of dmesg spam complaining about interrupt storm on HDMI connector; * NGI with analog on DVI port but that does not work (not enabled for this reason); * Analog on DVI port out is shaking, which is not the case with vendor BIOS. Not tested: * Booting with descriptor (most likely fixes GBE); * ME with descriptor; * Sound; * All the rest. Not coreboot related problems: * Flashing this board with vendor bios is a PITA and requires desoldering flash chip; * In situ programming is not possible. TESTED with SeaBIOS and Linux 4.10.8 Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/intel/dg43gt/Kconfig A src/mainboard/intel/dg43gt/Kconfig.name A src/mainboard/intel/dg43gt/Makefile.inc A src/mainboard/intel/dg43gt/acpi/ec.asl A src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl A src/mainboard/intel/dg43gt/acpi/platform.asl A src/mainboard/intel/dg43gt/acpi/superio.asl A src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl A src/mainboard/intel/dg43gt/acpi_tables.c A src/mainboard/intel/dg43gt/board_info.txt A src/mainboard/intel/dg43gt/cmos.default A src/mainboard/intel/dg43gt/cmos.layout A src/mainboard/intel/dg43gt/cstates.c A src/mainboard/intel/dg43gt/devicetree.cb A src/mainboard/intel/dg43gt/dsdt.asl A src/mainboard/intel/dg43gt/gpio.c A src/mainboard/intel/dg43gt/hda_verb.c A src/mainboard/intel/dg43gt/romstage.c 18 files changed, 890 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/19256/9 -- To view, visit https://review.coreboot.org/19256 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/i82801jx: Route all PIRQ to INT11
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19254 to look at the new patch set (#6). Change subject: sb/intel/i82801jx: Route all PIRQ to INT11 ...................................................................... sb/intel/i82801jx: Route all PIRQ to INT11 Interrupt 11 is not used by legacy devices and so can always be used for PCI interrupts. Full legacy IRQ routing is complicated and hard to get right. Change-Id: I6c718f4b9fb91ffcc4a136120581a4fcd7ec7231 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/lpc.c 2 files changed, 21 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/19254/6 -- To view, visit https://review.coreboot.org/19254 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6c718f4b9fb91ffcc4a136120581a4fcd7ec7231 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/i82801jx: Add Interrupt pin and routing RCBA offset...
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19255 to look at the new patch set (#6). Change subject: sb/intel/i82801jx: Add Interrupt pin and routing RCBA offsets macros ...................................................................... sb/intel/i82801jx: Add Interrupt pin and routing RCBA offsets macros Change-Id: If8e82a291f666d5f310422b100f02d5df17ab74e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801jx/i82801jx.h 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/19255/6 -- To view, visit https://review.coreboot.org/19255 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: If8e82a291f666d5f310422b100f02d5df17ab74e Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/i82801jx: Generate default fadt and madt
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19253 to look at the new patch set (#6). Change subject: sb/intel/i82801jx: Generate default fadt and madt ...................................................................... sb/intel/i82801jx: Generate default fadt and madt Function copied from i82801gx with offsets fixed for i82801lx. Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/lpc.c 3 files changed, 150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/19253/6 -- To view, visit https://review.coreboot.org/19253 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/i82801lx: Add addition IO resources
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19251 to look at the new patch set (#6). Change subject: sb/intel/i82801lx: Add addition IO resources ...................................................................... sb/intel/i82801lx: Add addition IO resources Adapted from i82801gx. Change-Id: I9108a45135908b7c4e74e9df3bb8f89f55893299 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801jx/lpc.c 1 file changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/19251/6 -- To view, visit https://review.coreboot.org/19251 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9108a45135908b7c4e74e9df3bb8f89f55893299 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/dg43gt: Add mainboard
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19256 to look at the new patch set (#8). Change subject: mb/intel/dg43gt: Add mainboard ...................................................................... mb/intel/dg43gt: Add mainboard This mainboard features is an G43 northbridge, ICH10 southbridge and Winbond W83627dhg SuperI/O. This board is impossible to flash internally with vendor bios (BIOS region is WP and other regions like IFD and ME are read only and inaccessible respectively). Due to either ICH10 or board layout it is also impossible to do ISP, which requires desoldering flash chip. To make hacking more easy there is an empty SPI header next to spi flash pads which can be hooked up to a SPI flash. What works: * 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1); * SATA * Integrated GPU with option rom (extracted from a Gigabyte vendor bios) * PCI * PEG slot with additional patches * Reboot and S3 resume * USB. What does not work: * GBE (requires descriptor); * Lots of dmesg spam complaining about interrupt storm on HDMI connector; * NGI with analog on DVI port but that does not work (not enabled for this reason); * Analog on DVI port out is shaking, which is not the case with vendor BIOS. Not tested: * Booting with descriptor (most likely fixes GBE); * ME with descriptor; * Sound; * All the rest. Not coreboot related problems: * Flashing this board with vendor bios is a PITA and requires desoldering flash chip; * In situ programming is not possible. TESTED with SeaBIOS and Linux 4.10.8 Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/intel/dg43gt/Kconfig A src/mainboard/intel/dg43gt/Kconfig.name A src/mainboard/intel/dg43gt/Makefile.inc A src/mainboard/intel/dg43gt/acpi/ec.asl A src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl A src/mainboard/intel/dg43gt/acpi/platform.asl A src/mainboard/intel/dg43gt/acpi/superio.asl A src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl A src/mainboard/intel/dg43gt/acpi_tables.c A src/mainboard/intel/dg43gt/board_info.txt A src/mainboard/intel/dg43gt/cmos.default A src/mainboard/intel/dg43gt/cmos.layout A src/mainboard/intel/dg43gt/cstates.c A src/mainboard/intel/dg43gt/devicetree.cb A src/mainboard/intel/dg43gt/dsdt.asl A src/mainboard/intel/dg43gt/gpio.c A src/mainboard/intel/dg43gt/hda_verb.c A src/mainboard/intel/dg43gt/romstage.c 18 files changed, 890 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/19256/8 -- To view, visit https://review.coreboot.org/19256 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/i82801jx: Add function to detect s3 resume
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19252 to look at the new patch set (#6). Change subject: sb/intel/i82801jx: Add function to detect s3 resume ...................................................................... sb/intel/i82801jx: Add function to detect s3 resume File copied from i82801gx. Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801jx/Makefile.inc A src/southbridge/intel/i82801jx/early_lpc.c M src/southbridge/intel/i82801jx/i82801jx.h 3 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/19252/6 -- To view, visit https://review.coreboot.org/19252 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/i82801jx: Copy i82801ix
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19248 to look at the new patch set (#4). Change subject: sb/intel/i82801jx: Copy i82801ix ...................................................................... sb/intel/i82801jx: Copy i82801ix Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/southbridge/intel/i82801jx/Kconfig A src/southbridge/intel/i82801jx/Makefile.inc A src/southbridge/intel/i82801jx/acpi/audio.asl A src/southbridge/intel/i82801jx/acpi/globalnvs.asl A src/southbridge/intel/i82801jx/acpi/ich9.asl A src/southbridge/intel/i82801jx/acpi/irqlinks.asl A src/southbridge/intel/i82801jx/acpi/lpc.asl A src/southbridge/intel/i82801jx/acpi/pci.asl A src/southbridge/intel/i82801jx/acpi/pcie.asl A src/southbridge/intel/i82801jx/acpi/pcie_port.asl A src/southbridge/intel/i82801jx/acpi/sata.asl A src/southbridge/intel/i82801jx/acpi/sleepstates.asl A src/southbridge/intel/i82801jx/acpi/smbus.asl A src/southbridge/intel/i82801jx/acpi/usb.asl A src/southbridge/intel/i82801jx/bootblock.c A src/southbridge/intel/i82801jx/chip.h A src/southbridge/intel/i82801jx/dmi_setup.c A src/southbridge/intel/i82801jx/early_init.c A src/southbridge/intel/i82801jx/early_smbus.c A src/southbridge/intel/i82801jx/hdaudio.c A src/southbridge/intel/i82801jx/i82801ix.c A src/southbridge/intel/i82801jx/i82801ix.h A src/southbridge/intel/i82801jx/lpc.c A src/southbridge/intel/i82801jx/nvs.h A src/southbridge/intel/i82801jx/pci.c A src/southbridge/intel/i82801jx/pcie.c A src/southbridge/intel/i82801jx/sata.c A src/southbridge/intel/i82801jx/smbus.c A src/southbridge/intel/i82801jx/smbus.h A src/southbridge/intel/i82801jx/smi.c A src/southbridge/intel/i82801jx/smihandler.c A src/southbridge/intel/i82801jx/thermal.c A src/southbridge/intel/i82801jx/usb_ehci.c 33 files changed, 5,972 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/19248/4 -- To view, visit https://review.coreboot.org/19248 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/i82801jx: Add correct PCI ids and change names
by Arthur Heymans (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19249 to look at the new patch set (#4). Change subject: sb/intel/i82801jx: Add correct PCI ids and change names ...................................................................... sb/intel/i82801jx: Add correct PCI ids and change names Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smmrelocate.S M src/northbridge/intel/x4x/early_init.c M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr2.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/Makefile.inc M src/southbridge/intel/i82801jx/acpi/audio.asl R src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl M src/southbridge/intel/i82801jx/acpi/pci.asl M src/southbridge/intel/i82801jx/acpi/usb.asl M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/dmi_setup.c M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/hdaudio.c R src/southbridge/intel/i82801jx/i82801jx.c R src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/pci.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/smbus.h M src/southbridge/intel/i82801jx/smi.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82801jx/usb_ehci.c 29 files changed, 165 insertions(+), 122 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19249/4 -- To view, visit https://review.coreboot.org/19249 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit May 2017