Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19558 )
Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/19558/3/src/mainboard/google/gru/sdram_conf…
File src/mainboard/google/gru/sdram_configs.c:
Line 49: if (IS_ENABLED(CONFIG_BOARD_GOOGLE_BOB) && board_id() < 4)
> Rather than duplicating the file name list for all frequencies, why not jus
(1) Is that worth increasing the size to solve it?
I'm assuming that's worth.
src/console/Makefile.inc to enable vsprintf.c in all stages, but I have seen some other build failure.
...
CC bootblock/lib/memchr.o
src/console/vsprintf.c:55:5: error: no previous prototype for 'snprintf' [-Werror=missing-prototypes]
int snprintf(char *buf, size_t size, const char *fmt, ...)
Looks like, we don't need define the __PRE_RAM__ first.
index 5b2486a..34aa370 100644
--- a/src/include/string.h
+++ b/src/include/string.h
@@ -15,9 +15,9 @@ void *memmove(void *dest, const void *src, size_t n);
void *memset(void *s, int c, size_t n);
int memcmp(const void *s1, const void *s2, size_t n);
void *memchr(const void *s, int c, size_t n);
+//#if !defined(__PRE_RAM__)
int snprintf(char * buf, size_t size, const char *fmt, ...);
+//#endif
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Iru Cai has uploaded a new change for review. ( https://review.coreboot.org/19618 )
Change subject: [NOT FOR MERGE] buildgcc: Update GCC to 7.1.0.
......................................................................
[NOT FOR MERGE] buildgcc: Update GCC to 7.1.0.
Tested with lenovo/x230 without libgfxinit.
libgfxinit fails to build with the following error:
hw-mmio_range.adb:50:63: volatile object cannot appear in this context (SPARK RM 7.1.3(11))
hw-mmio_range.adb:65:63: volatile object cannot appear in this context (SPARK RM 7.1.3(11))
Change-Id: I262fb421067f2e58d7f3905f86bea28bcec219b5
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
M util/crossgcc/buildgcc
D util/crossgcc/patches/gcc-6.3.0_memmodel.patch
D util/crossgcc/patches/gcc-6.3.0_nds32.patch
D util/crossgcc/patches/gcc-6.3.0_riscv.patch
R util/crossgcc/patches/gcc-7.1.0_elf_biarch.patch
R util/crossgcc/patches/gcc-7.1.0_gnat.patch
R util/crossgcc/patches/gcc-7.1.0_libgcc.patch
D util/crossgcc/sum/gcc-6.3.0.tar.bz2.cksum
A util/crossgcc/sum/gcc-7.1.0.tar.bz2.cksum
9 files changed, 2 insertions(+), 10,967 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/19618/1
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Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c
File src/soc/rockchip/rk3399/clock.c:
Line 373: PLL_FRAC_MODE << PLL_DSMPD_SHIFT));
> I believe this fractional mode is different with the pll fractional divider
In other word, the SSC register just enable the decimal mode, do not set the fractional frequency, the clock is calculated in different ways.
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Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c
File src/soc/rockchip/rk3399/clock.c:
PS4, Line 359: /* Wait for the dpll stable */
: udelay(30);
: assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6);
Can we change it with the below patch?
+ if (!(dpll_cfg->refdiv && dpll_cfg->refdiv <=6)) {
+ printk(BIOS_ERR,"%s: failed to get refdiv(%d)\n",__func__,
+ dpll_cfg->refdiv);
+ return;
+ }
That's fine from the short test. I don't see the error log.
That's weird, we should printf the log if the assert() failed.
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Iru Cai has posted comments on this change. ( https://review.coreboot.org/18480 )
Change subject: superiotool: Add SMSC KBC1126
......................................................................
Patch Set 5:
> is there a public datasheet containing the register description?
There's only a "KBC1122 Priliminary DS" found on the internet. It can be downloaded on some forums that need to register to download. It contains register description.
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Iru Cai has posted comments on this change. ( https://review.coreboot.org/19606 )
Change subject: superiotool: Add registers of LPC47N217
......................................................................
Patch Set 1:
> Is there a public datasheet to compare against?
Yes, the LPC47N217 datasheet can be found on internet:
https://versalogic.com/Support/Downloads/PDF/LPC47N217_(Data%20Sheet).pdf
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