coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by Caesar Wang (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19558 to look at the new patch set (#6). Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... google/gru: support 800M/928M frequency for bob The coreboot had no supported the different frequency for gru yet. e.g: we can't support the bob to run ddr 800M for rev3 board and run 928M for rev4 board. So, in order to support the 800M and 928M ddr frequency for bob different boards. We will use the ram_id and board_id to select the board on bob. Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> --- M src/mainboard/google/gru/Kconfig M src/mainboard/google/gru/Makefile.inc M src/mainboard/google/gru/sdram_configs.c R src/mainboard/google/gru/sdram_params/Makefile.inc R src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c D src/mainboard/google/gru/sdram_params_933/Makefile.inc 14 files changed, 38 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19558/6 -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/include: remove the __ROMCC__ to enable snprintf
by Caesar Wang (Code Review) 08 May '17

08 May '17

Caesar Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/19622 ) Change subject: src/include: remove the __ROMCC__ to enable snprintf ...................................................................... src/include: remove the __ROMCC__ to enable snprintf Change-Id: I6966dc8ebc911b954bc5ea8981df093df226dd6c Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> --- M src/include/string.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/19622/2 -- To view, visit https://review.coreboot.org/19622 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6966dc8ebc911b954bc5ea8981df093df226dd6c Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>

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Change in coreboot[master]: src/include: remove the __ROMCC__ to enable snprintf
by Caesar Wang (Code Review) 08 May '17

08 May '17

Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19622 ) Change subject: src/include: remove the __ROMCC__ to enable snprintf ...................................................................... Patch Set 1: I saw Paul posted the patch. commit 8941158d1970c3da1d7fd9714dea32bec88d180e Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Wed Apr 19 15:09:57 2017 +0200 console: Make snprintf available in all stages Change-Id: If5e255c75e7774393ef7e4febef84d97a1a3a118 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de ---- As the previous said:" src/console/Makefile.inc to enable vsprintf.c in all stages, but I have seen some other build failure." ... CC bootblock/lib/memchr.o src/console/vsprintf.c:55:5: error: no previous prototype for 'snprintf' [-Werror=missing-prototypes] int snprintf(char *buf, size_t size, const char *fmt, ...) Looks like, we don't need define the __PRE_RAM__ first. index 5b2486a..34aa370 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -15,9 +15,9 @@ void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); +//#if !defined(__PRE_RAM__) int snprintf(char * buf, size_t size, const char *fmt, ...); +//#endif -- To view, visit https://review.coreboot.org/19622 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6966dc8ebc911b954bc5ea8981df093df226dd6c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-HasComments: No

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Change in coreboot[master]: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
by build bot (Jenkins) (Code Review) 08 May '17

08 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19557 ) Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53440/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9238/ : SUCCESS -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: src/include: remove the __ROMCC__ to enable snprintf
by Caesar Wang (Code Review) 08 May '17

08 May '17

Caesar Wang has uploaded a new change for review. ( https://review.coreboot.org/19622 ) Change subject: src/include: remove the __ROMCC__ to enable snprintf ...................................................................... src/include: remove the __ROMCC__ to enable snprintf BRANCH=none BUG=b:36666655 TEST=boot from bob Change-Id: I6966dc8ebc911b954bc5ea8981df093df226dd6c Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> --- M src/include/string.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/19622/1 diff --git a/src/include/string.h b/src/include/string.h index 7597323..f50bc07 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -15,10 +15,7 @@ void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); -#if !defined(__ROMCC__) int snprintf(char *buf, size_t size, const char *fmt, ...); -#endif - // simple string functions static inline size_t strnlen(const char *src, size_t max) -- To view, visit https://review.coreboot.org/19622 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I6966dc8ebc911b954bc5ea8981df093df226dd6c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com>

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by Caesar Wang (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19558 to look at the new patch set (#5). Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... google/gru: support 800M/928M frequency for bob The coreboot had no supported the different frequency for gru yet. e.g: we can't support the bob to run ddr 800M for rev3 board and run 928M for rev4 board. So, in order to support the 800M and 928M ddr frequency for bob different boards. We will use the ram_id and board_id to select the board on bob. Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> --- M src/mainboard/google/gru/Kconfig M src/mainboard/google/gru/Makefile.inc M src/mainboard/google/gru/sdram_configs.c R src/mainboard/google/gru/sdram_params/Makefile.inc R src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c D src/mainboard/google/gru/sdram_params_933/Makefile.inc 14 files changed, 38 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19558/5 -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
by Caesar Wang (Code Review) 08 May '17

08 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19557 to look at the new patch set (#5). Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI. We need to turn the DPLL spread spectrum feature on to reduce the EMI noise for DDR on bob. Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com> Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> --- M src/mainboard/google/gru/Kconfig M src/soc/rockchip/rk3399/Kconfig M src/soc/rockchip/rk3399/clock.c 3 files changed, 98 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/19557/5 -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenovo/s230u: fix sata port map for the msata port
by build bot (Jenkins) (Code Review) 08 May '17

08 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19523 ) Change subject: mb/lenovo/s230u: fix sata port map for the msata port ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53439/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9237/ : SUCCESS -- To view, visit https://review.coreboot.org/19523 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1e9e96f0d0849b1e8c4e02aa4f686ceb5e10b3ab Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/gigabyte/ga-b75m-d3h: Add tpm support for its onboard tpm...
by build bot (Jenkins) (Code Review) 08 May '17

08 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19521 ) Change subject: mb/gigabyte/ga-b75m-d3h: Add tpm support for its onboard tpm socket ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53438/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9236/ : SUCCESS -- To view, visit https://review.coreboot.org/19521 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable MTRR check
by build bot (Jenkins) (Code Review) 08 May '17

08 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19609 ) Change subject: soc/intel/skylake: Enable MTRR check ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53437/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9235/ : SUCCESS -- To view, visit https://review.coreboot.org/19609 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I440405c58c470ffa338be386d84870635530a031 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017