Hello Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18993
to look at the new patch set (#13).
Change subject: mainboard: Add ASRock G41C-GS
......................................................................
mainboard: Add ASRock G41C-GS
Start-point is Gigabyte GA-G41M-ES2L.
This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.
Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).
Tested but fails:
* DDR3 (not implemented in coreboot).
Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.
Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
A src/mainboard/asrock/g41c-gs/Kconfig
A src/mainboard/asrock/g41c-gs/Kconfig.name
A src/mainboard/asrock/g41c-gs/Makefile.inc
A src/mainboard/asrock/g41c-gs/acpi/ec.asl
A src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
A src/mainboard/asrock/g41c-gs/acpi/platform.asl
A src/mainboard/asrock/g41c-gs/acpi/superio.asl
A src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl
A src/mainboard/asrock/g41c-gs/acpi_tables.c
A src/mainboard/asrock/g41c-gs/board_info.txt
A src/mainboard/asrock/g41c-gs/cmos.default
A src/mainboard/asrock/g41c-gs/cmos.layout
A src/mainboard/asrock/g41c-gs/cstates.c
A src/mainboard/asrock/g41c-gs/devicetree.cb
A src/mainboard/asrock/g41c-gs/dsdt.asl
A src/mainboard/asrock/g41c-gs/gpio.c
A src/mainboard/asrock/g41c-gs/hda_verb.c
A src/mainboard/asrock/g41c-gs/romstage.c
18 files changed, 874 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/18993/13
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Gerrit-PatchSet: 13
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins), coreboot org,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19143
to look at the new patch set (#16).
Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection
......................................................................
nb/x4x/raminit: Rewrite SPD decode and timing selection
This is mostly written from scratch and uses common spd ddr2 decode
functions.
This improves the following:
* This fixes incorrect CAS/Freq detection on DDR2;
* Fixes tRFC computation; tRFC == 78 is a valid timing which is
excluded and 0 ends up being used. (TESTED)
* Timings selection does not use loops;
* Removes ddr3 spd decode, since there is no DDR3 raminit. For this it
would be nice to use similar common functions for DDR3;
* Raminit would bail out if dimm was unsupported, now in some cases it
just marks the dimm slot as empty;
* It dramatically reduces stack usage since it does not allocate 4
times 256 bytes to store full SPDs, amongs other unused things that
were stored in sysinfo.
* Reports when no dimms are present.
* Uses i2c block read to read SPD which is about 5 times faster than
bytewise read, with a fallback to smbus mode in case of failure.
TESTED: on ga-g41m-es2l.
Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr2.c
M src/northbridge/intel/x4x/x4x.h
3 files changed, 294 insertions(+), 380 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19143/16
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071
Gerrit-PatchSet: 16
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19654 )
Change subject: mb/lenovo/x60/t60: Remove `fn_ctrl_swap` option
......................................................................
Patch Set 1: Code-Review+2
Does this actually work on a thinkpad in the tree? (does not work on x200 either)
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Gerrit-MessageType: comment
Gerrit-Change-Id: Id2964002406a5fcf992f0ffc3627e3f66a2bb13f
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: No
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19655 )
Change subject: nb/amd/amdk8: Don't bail out on dimms on channel 1
......................................................................
Patch Set 1:
Actually should be: "inlude channel 1 for dimm presence test"...
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Gerrit-MessageType: comment
Gerrit-Change-Id: Ieb4a7c7c0e154bdb683d22691f4323635b37cae3
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: No