coreboot-gerrit May 2017

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Change in coreboot[master]: drivers/storage: Fix array references
by Lee Leahy (Code Review) 11 May '17

11 May '17

Lee Leahy has submitted this change and it was merged. ( https://review.coreboot.org/19643 ) Change subject: drivers/storage: Fix array references ...................................................................... drivers/storage: Fix array references Fix bug detected by coverity to handle the zero capacity case. Specific changes: * Reduce loop count by one to handle zero capacity case * Use structure instead of dual arrays * Move structures into display_capacity routine Coverity Issues: * 1374931 * 1374932 * 1374933 * 1374934 TEST=Build and run on Galileo Gen2 Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/19643 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/drivers/storage/storage.c 1 file changed, 31 insertions(+), 46 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/storage/storage.c b/src/drivers/storage/storage.c index 57477f9..8d7692c 100644 --- a/src/drivers/storage/storage.c +++ b/src/drivers/storage/storage.c @@ -30,41 +30,9 @@ #define DECIMAL_CAPACITY_MULTIPLIER 1000ULL #define HEX_CAPACITY_MULTIPLIER 1024ULL -static const char * const hex_unit_name[] = { - "TiB", "GiB", "MiB", "KiB", "B" -}; -static const char * const decimal_unit_name[] = { - "TB", "GB", "MB", "KB", "B" -}; - -static const uint64_t decimal_capacity_table[] = { - /* TB */ - DECIMAL_CAPACITY_MULTIPLIER * DECIMAL_CAPACITY_MULTIPLIER - * DECIMAL_CAPACITY_MULTIPLIER * DECIMAL_CAPACITY_MULTIPLIER, - /* GB */ - DECIMAL_CAPACITY_MULTIPLIER * DECIMAL_CAPACITY_MULTIPLIER - * DECIMAL_CAPACITY_MULTIPLIER, - /* MB */ - DECIMAL_CAPACITY_MULTIPLIER * DECIMAL_CAPACITY_MULTIPLIER, - /* KB */ - DECIMAL_CAPACITY_MULTIPLIER, - /* B */ - 1 -}; - -static const uint64_t hex_capacity_table[] = { - /* TiB */ - HEX_CAPACITY_MULTIPLIER * HEX_CAPACITY_MULTIPLIER - * HEX_CAPACITY_MULTIPLIER * HEX_CAPACITY_MULTIPLIER, - /* GiB */ - HEX_CAPACITY_MULTIPLIER * HEX_CAPACITY_MULTIPLIER - * HEX_CAPACITY_MULTIPLIER, - /* MiB */ - HEX_CAPACITY_MULTIPLIER * HEX_CAPACITY_MULTIPLIER, - /* KiB */ - HEX_CAPACITY_MULTIPLIER, - /* B */ - 1 +struct capacity { + const char * const units; + uint64_t bytes; }; static void display_capacity(struct storage_media *media, int partition_number) @@ -77,6 +45,26 @@ int index; const char *name; const char *separator; + const struct capacity decimal_list[] = { + {"TB", DECIMAL_CAPACITY_MULTIPLIER * DECIMAL_CAPACITY_MULTIPLIER + * DECIMAL_CAPACITY_MULTIPLIER + * DECIMAL_CAPACITY_MULTIPLIER}, + {"GB", DECIMAL_CAPACITY_MULTIPLIER * DECIMAL_CAPACITY_MULTIPLIER + * DECIMAL_CAPACITY_MULTIPLIER}, + {"MB", DECIMAL_CAPACITY_MULTIPLIER + * DECIMAL_CAPACITY_MULTIPLIER}, + {"KB", DECIMAL_CAPACITY_MULTIPLIER}, + {"B", 1} + }; + const struct capacity hex_list[] = { + {"TiB", HEX_CAPACITY_MULTIPLIER * HEX_CAPACITY_MULTIPLIER + * HEX_CAPACITY_MULTIPLIER * HEX_CAPACITY_MULTIPLIER}, + {"GiB", HEX_CAPACITY_MULTIPLIER * HEX_CAPACITY_MULTIPLIER + * HEX_CAPACITY_MULTIPLIER}, + {"MiB", HEX_CAPACITY_MULTIPLIER * HEX_CAPACITY_MULTIPLIER}, + {"KiB", HEX_CAPACITY_MULTIPLIER}, + {"B", 1} + }; /* Get the partition name */ capacity = media->capacity[partition_number]; @@ -86,23 +74,20 @@ separator = ": "; /* Determine the decimal divisor for the capacity */ - ASSERT(ARRAY_SIZE(decimal_capacity_table) - == ARRAY_SIZE(decimal_unit_name)); - for (index = 0; index < ARRAY_SIZE(decimal_capacity_table); index++) { - if (capacity >= decimal_capacity_table[index]) + for (index = 0; index < ARRAY_SIZE(decimal_list) - 1; index++) { + if (capacity >= decimal_list[index].bytes) break; } - decimal_divisor = decimal_capacity_table[index]; - decimal_units = decimal_unit_name[index]; + decimal_divisor = decimal_list[index].bytes; + decimal_units = decimal_list[index].units; /* Determine the hex divisor for the capacity */ - ASSERT(ARRAY_SIZE(hex_capacity_table) == ARRAY_SIZE(hex_unit_name)); - for (index = 0; index < ARRAY_SIZE(hex_capacity_table); index++) { - if (capacity >= hex_capacity_table[index]) + for (index = 0; index < ARRAY_SIZE(hex_list) - 1; index++) { + if (capacity >= hex_list[index].bytes) break; } - hex_divisor = hex_capacity_table[index]; - hex_units = hex_unit_name[index]; + hex_divisor = hex_list[index].bytes; + hex_units = hex_list[index].units; /* Display the capacity */ sdhc_debug("%3lld.%03lld %sytes (%3lld.%03lld %sytes)%s%s\n", -- To view, visit https://review.coreboot.org/19643 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intel/common: drop duplicate initializer
by build bot (Jenkins) (Code Review) 11 May '17

11 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19656 ) Change subject: intel/common: drop duplicate initializer ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9328/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53535/ : SUCCESS -- To view, visit https://review.coreboot.org/19656 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I99d0bd7d9b897a10edce35316e095e0223522c54 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: xcompile: Also try clang variants under the $triplet-clang s...
by build bot (Jenkins) (Code Review) 11 May '17

11 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19660 ) Change subject: xcompile: Also try clang variants under the $triplet-clang scheme ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9332/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53539/ : SUCCESS -- To view, visit https://review.coreboot.org/19660 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I14fe767d20f91b64e96c909291760bddcd108e5c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: xcompile: replace -print-librt-file-name with -print-libgcc-...
by build bot (Jenkins) (Code Review) 11 May '17

11 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19658 ) Change subject: xcompile: replace -print-librt-file-name with -print-libgcc-file-name ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9329/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53536/ : SUCCESS -- To view, visit https://review.coreboot.org/19658 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1e30d5518cf78e1d66925d6f2ccada60a43bb4f8 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: arch/arm64: Use variables of the right size for msr/mrs opcodes
by build bot (Jenkins) (Code Review) 11 May '17

11 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19661 ) Change subject: arch/arm64: Use variables of the right size for msr/mrs opcodes ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9331/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53538/ : SUCCESS -- To view, visit https://review.coreboot.org/19661 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9c8b9fe3a1adc521e393c2e2a0216f7f425a2a3e Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: xcompile: silence clang when referencing packed structs' mem...
by build bot (Jenkins) (Code Review) 11 May '17

11 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19659 ) Change subject: xcompile: silence clang when referencing packed structs' members ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9330/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53537/ : SUCCESS -- To view, visit https://review.coreboot.org/19659 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I5400f50d8b5b462270c700f7ff90d9d517278e71 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: drivers/storage: Fix array references
by Lee Leahy (Code Review) 11 May '17

11 May '17

Lee Leahy has posted comments on this change. ( https://review.coreboot.org/19643 ) Change subject: drivers/storage: Fix array references ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/19643/2/src/drivers/storage/storage.c File src/drivers/storage/storage.c: PS2, Line 77: ARRAY_SIZE(decimal_list) - 1 > Why is it minus 1? If the '1' entries don't matter remove them? And just ch The less than ensures that index only references actual elements of the array. The minus one handles the case where capacity is zero and returns an index of (ARRAY_SIZE(array) - 1) which is the last element of the array with a divisor of 1 and units of bytes. This eliminates the need for special case code to handle the zero capacity case. Coverity should be happy now since all possible exits from the loop have a valid index value. -- To view, visit https://review.coreboot.org/19643 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

1 0

Change in coreboot[master]: toolchain.inc: Use -Wstack-usage only on gcc
by build bot (Jenkins) (Code Review) 11 May '17

11 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19657 ) Change subject: toolchain.inc: Use -Wstack-usage only on gcc ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9327/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53534/ : SUCCESS -- To view, visit https://review.coreboot.org/19657 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2c22171dedc77df24e739ec26335010f0f443963 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: xcompile: Also try clang variants under the $triplet-clang s...
by Patrick Georgi (Code Review) 11 May '17

11 May '17

Patrick Georgi has uploaded a new change for review. ( https://review.coreboot.org/19660 ) Change subject: xcompile: Also try clang variants under the $triplet-clang scheme ...................................................................... xcompile: Also try clang variants under the $triplet-clang scheme That seems to be the more reliable way to build clang cross compilers for now. Change-Id: I14fe767d20f91b64e96c909291760bddcd108e5c Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/xcompile/xcompile 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/19660/1 diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 6986b53..3f6641d7 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -423,14 +423,16 @@ fi for clang_arch in $TCLIST invalid; do - testcc "${XGCCPATH}clang" "-target ${clang_arch}-$TABI -c" && break + for clang_prefix in $search $XGCCPATH ""; do + testcc "${clang_prefix}clang" "-target ${clang_arch}-$TABI -c" && break 2 + done done if [ "invalid" != "$clang_arch" ]; then # FIXME: this may break in a clang && !gcc configuration, # but that's more of a clang limitation. Let's be optimistic # that this will change in the future. - CLANG="${XGCCPATH}clang" + CLANG="${clang_prefix}clang" CFLAGS_CLANG="-target ${clang_arch}-${TABI} $CFLAGS_CLANG -ccc-gcc-name ${GCC}" fi } -- To view, visit https://review.coreboot.org/19660 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I14fe767d20f91b64e96c909291760bddcd108e5c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

1 0

Change in coreboot[master]: arch/arm64: Use variables of the right size for msr/mrs opcodes
by Patrick Georgi (Code Review) 11 May '17

11 May '17

Patrick Georgi has uploaded a new change for review. ( https://review.coreboot.org/19661 ) Change subject: arch/arm64: Use variables of the right size for msr/mrs opcodes ...................................................................... arch/arm64: Use variables of the right size for msr/mrs opcodes They do 64bit accesses, and gcc does the necessary fix ups to handle 32bit values as zero-padded 64bit values. clang, however, isn't happy with it. Change-Id: I9c8b9fe3a1adc521e393c2e2a0216f7f425a2a3e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/arch/arm64/armv8/lib/clock.c M src/arch/arm64/armv8/lib/pstate.c M src/arch/arm64/armv8/lib/sysctrl.c 3 files changed, 84 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/19661/1 diff --git a/src/arch/arm64/armv8/lib/clock.c b/src/arch/arm64/armv8/lib/clock.c index 7cd4bc6..f15adf4 100644 --- a/src/arch/arm64/armv8/lib/clock.c +++ b/src/arch/arm64/armv8/lib/clock.c @@ -23,5 +23,5 @@ void set_cntfrq(uint32_t freq) { - __asm__ __volatile__("msr cntfrq_el0, %0" :: "r"(freq)); + __asm__ __volatile__("msr cntfrq_el0, %0" :: "r"((uint64_t)freq)); } diff --git a/src/arch/arm64/armv8/lib/pstate.c b/src/arch/arm64/armv8/lib/pstate.c index f3189f0..e068031 100644 --- a/src/arch/arm64/armv8/lib/pstate.c +++ b/src/arch/arm64/armv8/lib/pstate.c @@ -25,7 +25,7 @@ /* CurrentEL */ uint32_t raw_read_current_el(void) { - uint32_t current_el; + uint64_t current_el; __asm__ __volatile__("mrs %0, CurrentEL\n\t" : "=r" (current_el) : : "memory"); @@ -41,7 +41,7 @@ /* DAIF */ uint32_t raw_read_daif(void) { - uint32_t daif; + uint64_t daif; __asm__ __volatile__("mrs %0, DAIF\n\t" : "=r" (daif) : : "memory"); @@ -50,7 +50,7 @@ void raw_write_daif(uint32_t daif) { - __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory"); + __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" ((uint64_t)daif) : "memory"); } void enable_debug_exceptions(void) @@ -189,7 +189,7 @@ /* FPCR */ uint32_t raw_read_fpcr(void) { - uint32_t fpcr; + uint64_t fpcr; __asm__ __volatile__("mrs %0, FPCR\n\t" : "=r" (fpcr) : : "memory"); @@ -198,13 +198,13 @@ void raw_write_fpcr(uint32_t fpcr) { - __asm__ __volatile__("msr FPCR, %0\n\t" : : "r" (fpcr) : "memory"); + __asm__ __volatile__("msr FPCR, %0\n\t" : : "r" ((uint64_t)fpcr) : "memory"); } /* FPSR */ uint32_t raw_read_fpsr(void) { - uint32_t fpsr; + uint64_t fpsr; __asm__ __volatile__("mrs %0, FPSR\n\t" : "=r" (fpsr) : : "memory"); @@ -213,13 +213,13 @@ void raw_write_fpsr(uint32_t fpsr) { - __asm__ __volatile__("msr FPSR, %0\n\t" : : "r" (fpsr) : "memory"); + __asm__ __volatile__("msr FPSR, %0\n\t" : : "r" ((uint64_t)fpsr) : "memory"); } /* NZCV */ uint32_t raw_read_nzcv(void) { - uint32_t nzcv; + uint64_t nzcv; __asm__ __volatile__("mrs %0, NZCV\n\t" : "=r" (nzcv) : : "memory"); @@ -228,7 +228,7 @@ void raw_write_nzcv(uint32_t nzcv) { - __asm__ __volatile__("msr NZCV, %0\n\t" : : "r" (nzcv) : "memory"); + __asm__ __volatile__("msr NZCV, %0\n\t" : : "r" ((uint64_t)nzcv) : "memory"); } /* SP */ @@ -277,7 +277,7 @@ /* SPSel */ uint32_t raw_read_spsel(void) { - uint32_t spsel; + uint64_t spsel; __asm__ __volatile__("mrs %0, SPSel\n\t" : "=r" (spsel) : : "memory"); @@ -286,7 +286,7 @@ void raw_write_spsel(uint32_t spsel) { - __asm__ __volatile__("msr SPSel, %0\n\t" : : "r" (spsel) : "memory"); + __asm__ __volatile__("msr SPSel, %0\n\t" : : "r" ((uint64_t)spsel) : "memory"); } uint64_t raw_read_sp_el3(void) @@ -333,7 +333,7 @@ /* SPSR */ uint32_t raw_read_spsr_abt(void) { - uint32_t spsr_abt; + uint64_t spsr_abt; __asm__ __volatile__("mrs %0, SPSR_abt\n\t" : "=r" (spsr_abt) : : "memory"); @@ -342,12 +342,12 @@ void raw_write_spsr_abt(uint32_t spsr_abt) { - __asm__ __volatile__("msr SPSR_abt, %0\n\t" : : "r" (spsr_abt) : "memory"); + __asm__ __volatile__("msr SPSR_abt, %0\n\t" : : "r" ((uint64_t)spsr_abt) : "memory"); } uint32_t raw_read_spsr_el1(void) { - uint32_t spsr_el1; + uint64_t spsr_el1; __asm__ __volatile__("mrs %0, SPSR_EL1\n\t" : "=r" (spsr_el1) : : "memory"); @@ -356,12 +356,12 @@ void raw_write_spsr_el1(uint32_t spsr_el1) { - __asm__ __volatile__("msr SPSR_EL1, %0\n\t" : : "r" (spsr_el1) : "memory"); + __asm__ __volatile__("msr SPSR_EL1, %0\n\t" : : "r" ((uint64_t)spsr_el1) : "memory"); } uint32_t raw_read_spsr_el2(void) { - uint32_t spsr_el2; + uint64_t spsr_el2; __asm__ __volatile__("mrs %0, SPSR_EL2\n\t" : "=r" (spsr_el2) : : "memory"); @@ -370,12 +370,12 @@ void raw_write_spsr_el2(uint32_t spsr_el2) { - __asm__ __volatile__("msr SPSR_EL2, %0\n\t" : : "r" (spsr_el2) : "memory"); + __asm__ __volatile__("msr SPSR_EL2, %0\n\t" : : "r" ((uint64_t)spsr_el2) : "memory"); } uint32_t raw_read_spsr_el3(void) { - uint32_t spsr_el3; + uint64_t spsr_el3; __asm__ __volatile__("mrs %0, SPSR_EL3\n\t" : "=r" (spsr_el3) : : "memory"); @@ -384,7 +384,7 @@ void raw_write_spsr_el3(uint32_t spsr_el3) { - __asm__ __volatile__("msr SPSR_EL3, %0\n\t" : : "r" (spsr_el3) : "memory"); + __asm__ __volatile__("msr SPSR_EL3, %0\n\t" : : "r" ((uint64_t)spsr_el3) : "memory"); } uint32_t raw_read_spsr_current(void) @@ -411,7 +411,7 @@ uint32_t raw_read_spsr_fiq(void) { - uint32_t spsr_fiq; + uint64_t spsr_fiq; __asm__ __volatile__("mrs %0, SPSR_fiq\n\t" : "=r" (spsr_fiq) : : "memory"); @@ -420,12 +420,12 @@ void raw_write_spsr_fiq(uint32_t spsr_fiq) { - __asm__ __volatile__("msr SPSR_fiq, %0\n\t" : : "r" (spsr_fiq) : "memory"); + __asm__ __volatile__("msr SPSR_fiq, %0\n\t" : : "r" ((uint64_t)spsr_fiq) : "memory"); } uint32_t raw_read_spsr_irq(void) { - uint32_t spsr_irq; + uint64_t spsr_irq; __asm__ __volatile__("mrs %0, SPSR_irq\n\t" : "=r" (spsr_irq) : : "memory"); @@ -434,12 +434,12 @@ void raw_write_spsr_irq(uint32_t spsr_irq) { - __asm__ __volatile__("msr SPSR_irq, %0\n\t" : : "r" (spsr_irq) : "memory"); + __asm__ __volatile__("msr SPSR_irq, %0\n\t" : : "r" ((uint64_t)spsr_irq) : "memory"); } uint32_t raw_read_spsr_und(void) { - uint32_t spsr_und; + uint64_t spsr_und; __asm__ __volatile__("mrs %0, SPSR_und\n\t" : "=r" (spsr_und) : : "memory"); @@ -448,5 +448,5 @@ void raw_write_spsr_und(uint32_t spsr_und) { - __asm__ __volatile__("msr SPSR_und, %0\n\t" : : "r" (spsr_und) : "memory"); + __asm__ __volatile__("msr SPSR_und, %0\n\t" : : "r" ((uint64_t)spsr_und) : "memory"); } diff --git a/src/arch/arm64/armv8/lib/sysctrl.c b/src/arch/arm64/armv8/lib/sysctrl.c index e349a25..9cf26a5 100644 --- a/src/arch/arm64/armv8/lib/sysctrl.c +++ b/src/arch/arm64/armv8/lib/sysctrl.c @@ -25,7 +25,7 @@ /* ACTLR */ uint32_t raw_read_actlr_el1(void) { - uint32_t actlr_el1; + uint64_t actlr_el1; __asm__ __volatile__("mrs %0, ACTLR_EL1\n\t" : "=r" (actlr_el1) : : "memory"); @@ -34,12 +34,12 @@ void raw_write_actlr_el1(uint32_t actlr_el1) { - __asm__ __volatile__("msr ACTLR_EL1, %0\n\t" : : "r" (actlr_el1) : "memory"); + __asm__ __volatile__("msr ACTLR_EL1, %0\n\t" : : "r" ((uint64_t)actlr_el1) : "memory"); } uint32_t raw_read_actlr_el2(void) { - uint32_t actlr_el2; + uint64_t actlr_el2; __asm__ __volatile__("mrs %0, ACTLR_EL2\n\t" : "=r" (actlr_el2) : : "memory"); @@ -48,12 +48,12 @@ void raw_write_actlr_el2(uint32_t actlr_el2) { - __asm__ __volatile__("msr ACTLR_EL2, %0\n\t" : : "r" (actlr_el2) : "memory"); + __asm__ __volatile__("msr ACTLR_EL2, %0\n\t" : : "r" ((uint64_t)actlr_el2) : "memory"); } uint32_t raw_read_actlr_el3(void) { - uint32_t actlr_el3; + uint64_t actlr_el3; __asm__ __volatile__("mrs %0, ACTLR_EL3\n\t" : "=r" (actlr_el3) : : "memory"); @@ -62,7 +62,7 @@ void raw_write_actlr_el3(uint32_t actlr_el3) { - __asm__ __volatile__("msr ACTLR_EL3, %0\n\t" : : "r" (actlr_el3) : "memory"); + __asm__ __volatile__("msr ACTLR_EL3, %0\n\t" : : "r" ((uint64_t)actlr_el3) : "memory"); } uint32_t raw_read_actlr_current(void) @@ -90,7 +90,7 @@ /* AFSR0 */ uint32_t raw_read_afsr0_el1(void) { - uint32_t afsr0_el1; + uint64_t afsr0_el1; __asm__ __volatile__("mrs %0, AFSR0_EL1\n\t" : "=r" (afsr0_el1) : : "memory"); @@ -99,12 +99,12 @@ void raw_write_afsr0_el1(uint32_t afsr0_el1) { - __asm__ __volatile__("msr AFSR0_EL1, %0\n\t" : : "r" (afsr0_el1) : "memory"); + __asm__ __volatile__("msr AFSR0_EL1, %0\n\t" : : "r" ((uint64_t)afsr0_el1) : "memory"); } uint32_t raw_read_afsr0_el2(void) { - uint32_t afsr0_el2; + uint64_t afsr0_el2; __asm__ __volatile__("mrs %0, AFSR0_EL2\n\t" : "=r" (afsr0_el2) : : "memory"); @@ -113,12 +113,12 @@ void raw_write_afsr0_el2(uint32_t afsr0_el2) { - __asm__ __volatile__("msr AFSR0_EL2, %0\n\t" : : "r" (afsr0_el2) : "memory"); + __asm__ __volatile__("msr AFSR0_EL2, %0\n\t" : : "r" ((uint64_t)afsr0_el2) : "memory"); } uint32_t raw_read_afsr0_el3(void) { - uint32_t afsr0_el3; + uint64_t afsr0_el3; __asm__ __volatile__("mrs %0, AFSR0_EL3\n\t" : "=r" (afsr0_el3) : : "memory"); @@ -127,7 +127,7 @@ void raw_write_afsr0_el3(uint32_t afsr0_el3) { - __asm__ __volatile__("msr AFSR0_EL3, %0\n\t" : : "r" (afsr0_el3) : "memory"); + __asm__ __volatile__("msr AFSR0_EL3, %0\n\t" : : "r" ((uint64_t)afsr0_el3) : "memory"); } uint32_t raw_read_afsr0_current(void) @@ -155,7 +155,7 @@ /* AFSR1 */ uint32_t raw_read_afsr1_el1(void) { - uint32_t afsr1_el1; + uint64_t afsr1_el1; __asm__ __volatile__("mrs %0, AFSR1_EL1\n\t" : "=r" (afsr1_el1) : : "memory"); @@ -164,12 +164,12 @@ void raw_write_afsr1_el1(uint32_t afsr1_el1) { - __asm__ __volatile__("msr AFSR1_EL1, %0\n\t" : : "r" (afsr1_el1) : "memory"); + __asm__ __volatile__("msr AFSR1_EL1, %0\n\t" : : "r" ((uint64_t)afsr1_el1) : "memory"); } uint32_t raw_read_afsr1_el2(void) { - uint32_t afsr1_el2; + uint64_t afsr1_el2; __asm__ __volatile__("mrs %0, AFSR1_EL2\n\t" : "=r" (afsr1_el2) : : "memory"); @@ -178,12 +178,12 @@ void raw_write_afsr1_el2(uint32_t afsr1_el2) { - __asm__ __volatile__("msr AFSR1_EL2, %0\n\t" : : "r" (afsr1_el2) : "memory"); + __asm__ __volatile__("msr AFSR1_EL2, %0\n\t" : : "r" ((uint64_t)afsr1_el2) : "memory"); } uint32_t raw_read_afsr1_el3(void) { - uint32_t afsr1_el3; + uint64_t afsr1_el3; __asm__ __volatile__("mrs %0, AFSR1_EL3\n\t" : "=r" (afsr1_el3) : : "memory"); @@ -192,7 +192,7 @@ void raw_write_afsr1_el3(uint32_t afsr1_el3) { - __asm__ __volatile__("msr AFSR1_EL3, %0\n\t" : : "r" (afsr1_el3) : "memory"); + __asm__ __volatile__("msr AFSR1_EL3, %0\n\t" : : "r" ((uint64_t)afsr1_el3) : "memory"); } uint32_t raw_read_afsr1_current(void) @@ -220,7 +220,7 @@ /* AIDR */ uint32_t raw_read_aidr_el1(void) { - uint32_t aidr_el1; + uint64_t aidr_el1; __asm__ __volatile__("mrs %0, AIDR_EL1\n\t" : "=r" (aidr_el1) : : "memory"); @@ -295,7 +295,7 @@ /* CCSIDR */ uint32_t raw_read_ccsidr_el1(void) { - uint32_t ccsidr_el1; + uint64_t ccsidr_el1; __asm__ __volatile__("mrs %0, CCSIDR_EL1\n\t" : "=r" (ccsidr_el1) : : "memory"); @@ -305,7 +305,7 @@ /* CLIDR */ uint32_t raw_read_clidr_el1(void) { - uint32_t clidr_el1; + uint64_t clidr_el1; __asm__ __volatile__("mrs %0, CLIDR_EL1\n\t" : "=r" (clidr_el1) : : "memory"); @@ -315,7 +315,7 @@ /* CPACR */ uint32_t raw_read_cpacr_el1(void) { - uint32_t cpacr_el1; + uint64_t cpacr_el1; __asm__ __volatile__("mrs %0, CPACR_EL1\n\t" : "=r" (cpacr_el1) : : "memory"); @@ -324,13 +324,13 @@ void raw_write_cpacr_el1(uint32_t cpacr_el1) { - __asm__ __volatile__("msr CPACR_EL1, %0\n\t" : : "r" (cpacr_el1) : "memory"); + __asm__ __volatile__("msr CPACR_EL1, %0\n\t" : : "r" ((uint64_t)cpacr_el1) : "memory"); } /* CPTR */ uint32_t raw_read_cptr_el2(void) { - uint32_t cptr_el2; + uint64_t cptr_el2; __asm__ __volatile__("mrs %0, CPTR_EL2\n\t" : "=r" (cptr_el2) : : "memory"); @@ -339,12 +339,12 @@ void raw_write_cptr_el2(uint32_t cptr_el2) { - __asm__ __volatile__("msr CPTR_EL2, %0\n\t" : : "r" (cptr_el2) : "memory"); + __asm__ __volatile__("msr CPTR_EL2, %0\n\t" : : "r" ((uint64_t)cptr_el2) : "memory"); } uint32_t raw_read_cptr_el3(void) { - uint32_t cptr_el3; + uint64_t cptr_el3; __asm__ __volatile__("mrs %0, CPTR_EL3\n\t" : "=r" (cptr_el3) : : "memory"); @@ -353,13 +353,13 @@ void raw_write_cptr_el3(uint32_t cptr_el3) { - __asm__ __volatile__("msr CPTR_EL3, %0\n\t" : : "r" (cptr_el3) : "memory"); + __asm__ __volatile__("msr CPTR_EL3, %0\n\t" : : "r" ((uint64_t)cptr_el3) : "memory"); } /* CSSELR */ uint32_t raw_read_csselr_el1(void) { - uint32_t csselr_el1; + uint64_t csselr_el1; __asm__ __volatile__("mrs %0, CSSELR_EL1\n\t" : "=r" (csselr_el1) : : "memory"); @@ -368,13 +368,13 @@ void raw_write_csselr_el1(uint32_t csselr_el1) { - __asm__ __volatile__("msr CSSELR_EL1, %0\n\t" : : "r" (csselr_el1) : "memory"); + __asm__ __volatile__("msr CSSELR_EL1, %0\n\t" : : "r" ((uint64_t)csselr_el1) : "memory"); } /* CTR */ uint32_t raw_read_ctr_el0(void) { - uint32_t ctr_el0; + uint64_t ctr_el0; __asm__ __volatile__("mrs %0, CTR_EL0\n\t" : "=r" (ctr_el0) : : "memory"); @@ -384,7 +384,7 @@ /* ESR */ uint32_t raw_read_esr_el1(void) { - uint32_t esr_el1; + uint64_t esr_el1; __asm__ __volatile__("mrs %0, ESR_EL1\n\t" : "=r" (esr_el1) : : "memory"); @@ -393,12 +393,12 @@ void raw_write_esr_el1(uint32_t esr_el1) { - __asm__ __volatile__("msr ESR_EL1, %0\n\t" : : "r" (esr_el1) : "memory"); + __asm__ __volatile__("msr ESR_EL1, %0\n\t" : : "r" ((uint64_t)esr_el1) : "memory"); } uint32_t raw_read_esr_el2(void) { - uint32_t esr_el2; + uint64_t esr_el2; __asm__ __volatile__("mrs %0, ESR_EL2\n\t" : "=r" (esr_el2) : : "memory"); @@ -407,12 +407,12 @@ void raw_write_esr_el2(uint32_t esr_el2) { - __asm__ __volatile__("msr ESR_EL2, %0\n\t" : : "r" (esr_el2) : "memory"); + __asm__ __volatile__("msr ESR_EL2, %0\n\t" : : "r" ((uint64_t)esr_el2) : "memory"); } uint32_t raw_read_esr_el3(void) { - uint32_t esr_el3; + uint64_t esr_el3; __asm__ __volatile__("mrs %0, ESR_EL3\n\t" : "=r" (esr_el3) : : "memory"); @@ -421,7 +421,7 @@ void raw_write_esr_el3(uint32_t esr_el3) { - __asm__ __volatile__("msr ESR_EL3, %0\n\t" : : "r" (esr_el3) : "memory"); + __asm__ __volatile__("msr ESR_EL3, %0\n\t" : : "r" ((uint64_t)esr_el3) : "memory"); } uint32_t raw_read_esr_current(void) @@ -604,7 +604,7 @@ /* MIDR */ uint32_t raw_read_midr_el1(void) { - uint32_t midr_el1; + uint64_t midr_el1; __asm__ __volatile__("mrs %0, MIDR_EL1\n\t" : "=r" (midr_el1) : : "memory"); @@ -624,7 +624,7 @@ /* RMR */ uint32_t raw_read_rmr_el1(void) { - uint32_t rmr_el1; + uint64_t rmr_el1; __asm__ __volatile__("mrs %0, RMR_EL1\n\t" : "=r" (rmr_el1) : : "memory"); @@ -633,12 +633,12 @@ void raw_write_rmr_el1(uint32_t rmr_el1) { - __asm__ __volatile__("msr RMR_EL1, %0\n\t" : : "r" (rmr_el1) : "memory"); + __asm__ __volatile__("msr RMR_EL1, %0\n\t" : : "r" ((uint64_t)rmr_el1) : "memory"); } uint32_t raw_read_rmr_el2(void) { - uint32_t rmr_el2; + uint64_t rmr_el2; __asm__ __volatile__("mrs %0, RMR_EL2\n\t" : "=r" (rmr_el2) : : "memory"); @@ -647,12 +647,12 @@ void raw_write_rmr_el2(uint32_t rmr_el2) { - __asm__ __volatile__("msr RMR_EL2, %0\n\t" : : "r" (rmr_el2) : "memory"); + __asm__ __volatile__("msr RMR_EL2, %0\n\t" : : "r" ((uint64_t)rmr_el2) : "memory"); } uint32_t raw_read_rmr_el3(void) { - uint32_t rmr_el3; + uint64_t rmr_el3; __asm__ __volatile__("mrs %0, RMR_EL3\n\t" : "=r" (rmr_el3) : : "memory"); @@ -661,7 +661,7 @@ void raw_write_rmr_el3(uint32_t rmr_el3) { - __asm__ __volatile__("msr RMR_EL3, %0\n\t" : : "r" (rmr_el3) : "memory"); + __asm__ __volatile__("msr RMR_EL3, %0\n\t" : : "r" ((uint64_t)rmr_el3) : "memory"); } uint32_t raw_read_rmr_current(void) @@ -754,7 +754,7 @@ /* Scr */ uint32_t raw_read_scr_el3(void) { - uint32_t scr_el3; + uint64_t scr_el3; __asm__ __volatile__("mrs %0, SCR_EL3\n\t" : "=r" (scr_el3) : : "memory"); @@ -763,13 +763,13 @@ void raw_write_scr_el3(uint32_t scr_el3) { - __asm__ __volatile__("msr SCR_EL3, %0\n\t" : : "r" (scr_el3) : "memory"); + __asm__ __volatile__("msr SCR_EL3, %0\n\t" : : "r" ((uint64_t)scr_el3) : "memory"); } /* SCTLR */ uint32_t raw_read_sctlr_el1(void) { - uint32_t sctlr_el1; + uint64_t sctlr_el1; __asm__ __volatile__("mrs %0, SCTLR_EL1\n\t" : "=r" (sctlr_el1) : : "memory"); @@ -778,12 +778,12 @@ void raw_write_sctlr_el1(uint32_t sctlr_el1) { - __asm__ __volatile__("msr SCTLR_EL1, %0\n\t" : : "r" (sctlr_el1) : "memory"); + __asm__ __volatile__("msr SCTLR_EL1, %0\n\t" : : "r" ((uint64_t)sctlr_el1) : "memory"); } uint32_t raw_read_sctlr_el2(void) { - uint32_t sctlr_el2; + uint64_t sctlr_el2; __asm__ __volatile__("mrs %0, SCTLR_EL2\n\t" : "=r" (sctlr_el2) : : "memory"); @@ -792,12 +792,12 @@ void raw_write_sctlr_el2(uint32_t sctlr_el2) { - __asm__ __volatile__("msr SCTLR_EL2, %0\n\t" : : "r" (sctlr_el2) : "memory"); + __asm__ __volatile__("msr SCTLR_EL2, %0\n\t" : : "r" ((uint64_t)sctlr_el2) : "memory"); } uint32_t raw_read_sctlr_el3(void) { - uint32_t sctlr_el3; + uint64_t sctlr_el3; __asm__ __volatile__("mrs %0, SCTLR_EL3\n\t" : "=r" (sctlr_el3) : : "memory"); @@ -806,7 +806,7 @@ void raw_write_sctlr_el3(uint32_t sctlr_el3) { - __asm__ __volatile__("msr SCTLR_EL3, %0\n\t" : : "r" (sctlr_el3) : "memory"); + __asm__ __volatile__("msr SCTLR_EL3, %0\n\t" : : "r" ((uint64_t)sctlr_el3) : "memory"); } uint32_t raw_read_sctlr_current(void) @@ -848,7 +848,7 @@ uint32_t raw_read_tcr_el2(void) { - uint32_t tcr_el2; + uint64_t tcr_el2; __asm__ __volatile__("mrs %0, TCR_EL2\n\t" : "=r" (tcr_el2) : : "memory"); @@ -857,12 +857,12 @@ void raw_write_tcr_el2(uint32_t tcr_el2) { - __asm__ __volatile__("msr TCR_EL2, %0\n\t" : : "r" (tcr_el2) : "memory"); + __asm__ __volatile__("msr TCR_EL2, %0\n\t" : : "r" ((uint64_t)tcr_el2) : "memory"); } uint32_t raw_read_tcr_el3(void) { - uint32_t tcr_el3; + uint64_t tcr_el3; __asm__ __volatile__("mrs %0, TCR_EL3\n\t" : "=r" (tcr_el3) : : "memory"); @@ -871,7 +871,7 @@ void raw_write_tcr_el3(uint32_t tcr_el3) { - __asm__ __volatile__("msr TCR_EL3, %0\n\t" : : "r" (tcr_el3) : "memory"); + __asm__ __volatile__("msr TCR_EL3, %0\n\t" : : "r" ((uint64_t)tcr_el3) : "memory"); } @@ -1049,15 +1049,13 @@ uint32_t raw_read_cntfrq_el0(void) { - uint32_t cntfrq_el0; + uint64_t cntfrq_el0; - __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : - "memory"); + __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory"); return cntfrq_el0; } void raw_write_cntfrq_el0(uint32_t cntfrq_el0) { - __asm__ __volatile__("msr CNTFRQ_EL0, %0\n\t" : : "r" (cntfrq_el0) : - "memory"); + __asm__ __volatile__("msr CNTFRQ_EL0, %0\n\t" : : "r" ((uint64_t)cntfrq_el0) : "memory"); } -- To view, visit https://review.coreboot.org/19661 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I9c8b9fe3a1adc521e393c2e2a0216f7f425a2a3e Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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coreboot-gerrit May 2017