coreboot-gerrit May 2017

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Change in coreboot[master]: siemens/mc_apl1: Add usage of external RTC RX6110 SA
by Mario Scheithauer (Code Review) 11 May '17

11 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19647 to look at the new patch set (#2). Change subject: siemens/mc_apl1: Add usage of external RTC RX6110 SA ...................................................................... siemens/mc_apl1: Add usage of external RTC RX6110 SA This mainboard contains an external RTC chip RX6110 SA. Enable usage of this chip and set some initialization values to device tree. Change-Id: I5aceb4401f0bb059ef893dfe7d157716c82e4a76 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/devicetree.cb 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/19647/2 -- To view, visit https://review.coreboot.org/19647 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5aceb4401f0bb059ef893dfe7d157716c82e4a76 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/sapphire/pureplatinumh61: Sanitize Kconfig
by Nicola Corna (Code Review) 11 May '17

11 May '17

Nicola Corna has posted comments on this change. ( https://review.coreboot.org/19354 ) Change subject: mb/sapphire/pureplatinumh61: Sanitize Kconfig ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19354 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I11d1c7155bf1c7f9298f60638a6c2f3b128f3fe8 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rockchip/rk3399: Add MIPI driver
by Julius Werner (Code Review) 11 May '17

11 May '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19477 ) Change subject: rockchip/rk3399: Add MIPI driver ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/19477/5/src/soc/rockchip/rk3399/mipi.c File src/soc/rockchip/rk3399/mipi.c: Line 432: mdelay(120); > The SOC tells the panel to enter the display mode, and then wait for the pa So this is a panel-dependent value? Isn't there anything in the datasheet about how long the panel needs for this initialization? I would feel much better with that then "it seems to work with more than 120ms for some reason". (If we can't find a source, we should probably have a little more margin... maybe 150ms. But an official number would be much better.) -- To view, visit https://review.coreboot.org/19477 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sean Paul <seanpaul(a)chromium.org> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey.yang(a)rock-chips.com Gerrit-HasComments: Yes

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by Julius Werner (Code Review) 11 May '17

11 May '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/19558 ) Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... google/gru: support 800M/928M frequency for bob The coreboot had no supported the different frequency for gru yet. e.g: we can't support the bob to run ddr 800M for rev3 board and run 928M for rev4 board. So, in order to support the 800M and 928M ddr frequency for bob different boards. We will use the ram_id and board_id to select the board on bob. Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> Reviewed-on: https://review.coreboot.org/19558 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/gru/Kconfig M src/mainboard/google/gru/Makefile.inc M src/mainboard/google/gru/sdram_configs.c R src/mainboard/google/gru/sdram_params/Makefile.inc R src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c D src/mainboard/google/gru/sdram_params_933/Makefile.inc 14 files changed, 37 insertions(+), 48 deletions(-) Approvals: Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 0dba3e9..3a30013 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -95,13 +95,6 @@ default "Gru" if BOARD_GOOGLE_GRU default "Kevin" if BOARD_GOOGLE_KEVIN -# The default max sdram freq is 933M(actually 928M dpll), and -# 800M is another choice. -config MAX_SDRAM_FREQ - int - default 800 if BOARD_GOOGLE_BOB - default 933 - config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index d54ce2f..122139d 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -subdirs-y += sdram_params_$(CONFIG_MAX_SDRAM_FREQ)/ +subdirs-y += sdram_params/ bootblock-y += bootblock.c bootblock-y += chromeos.c diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index b9f77d0..eec8a0d 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -23,23 +23,40 @@ #include <types.h> static const char *sdram_configs[] = { - [0] = "sdram-lpddr3-hynix-4GB", - [3] = "sdram-lpddr3-samsung-2GB-24EB", - [4] = "sdram-lpddr3-micron-2GB", - [5] = "sdram-lpddr3-samsung-4GB-04EB", - [6] = "sdram-lpddr3-micron-4GB", + [0] = "sdram-lpddr3-hynix-4GB", + [3] = "sdram-lpddr3-samsung-2GB-24EB", + [4] = "sdram-lpddr3-micron-2GB", + [5] = "sdram-lpddr3-samsung-4GB-04EB", + [6] = "sdram-lpddr3-micron-4GB", }; static struct rk3399_sdram_params params; +enum dram_speeds { + dram_800MHz = 800, + dram_928MHz = 928, +}; + +static enum dram_speeds get_sdram_target_mhz(void) +{ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_BOB) && board_id() < 4) + return dram_800MHz; + + return dram_928MHz; +} + const struct rk3399_sdram_params *get_sdram_config() { + char config_file[64]; uint32_t ramcode; ramcode = ram_code(); - if (ramcode >= ARRAY_SIZE(sdram_configs) || !sdram_configs[ramcode] || - (cbfs_boot_load_struct(sdram_configs[ramcode], - &params, sizeof(params)) != sizeof(params))) + if (ramcode >= ARRAY_SIZE(sdram_configs) || + !snprintf(config_file, sizeof(config_file), "%s-%d", + sdram_configs[ramcode], get_sdram_target_mhz()) || + (cbfs_boot_load_struct(config_file, &params, + sizeof(params)) != sizeof(params))) die("Cannot load SDRAM parameter file!"); + return &params; } diff --git a/src/mainboard/google/gru/sdram_params_800/Makefile.inc b/src/mainboard/google/gru/sdram_params/Makefile.inc similarity index 64% rename from src/mainboard/google/gru/sdram_params_800/Makefile.inc rename to src/mainboard/google/gru/sdram_params/Makefile.inc index ca7b52b..6720c0c 100644 --- a/src/mainboard/google/gru/sdram_params_800/Makefile.inc +++ b/src/mainboard/google/gru/sdram_params/Makefile.inc @@ -14,10 +14,17 @@ ## sdram-params := -sdram-params += sdram-lpddr3-samsung-2GB-24EB -sdram-params += sdram-lpddr3-micron-2GB -sdram-params += sdram-lpddr3-samsung-4GB-04EB -sdram-params += sdram-lpddr3-micron-4GB +sdram-params += sdram-lpddr3-hynix-4GB-928 + +sdram-params += sdram-lpddr3-micron-2GB-800 +sdram-params += sdram-lpddr3-micron-2GB-928 +sdram-params += sdram-lpddr3-micron-4GB-800 +sdram-params += sdram-lpddr3-micron-4GB-928 + +sdram-params += sdram-lpddr3-samsung-2GB-24EB-800 +sdram-params += sdram-lpddr3-samsung-2GB-24EB-928 +sdram-params += sdram-lpddr3-samsung-4GB-04EB-800 +sdram-params += sdram-lpddr3-samsung-4GB-04EB-928 $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-hynix-4GB.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c similarity index 100% rename from src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-hynix-4GB.c rename to src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c diff --git a/src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-micron-2GB.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c similarity index 100% rename from src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-micron-2GB.c rename to src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c diff --git a/src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-micron-2GB.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c similarity index 100% rename from src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-micron-2GB.c rename to src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c diff --git a/src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-micron-4GB.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c similarity index 100% rename from src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-micron-4GB.c rename to src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c diff --git a/src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-micron-4GB.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c similarity index 100% rename from src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-micron-4GB.c rename to src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c diff --git a/src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-samsung-2GB-24EB.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c similarity index 100% rename from src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-samsung-2GB-24EB.c rename to src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c diff --git a/src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-samsung-2GB-24EB.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c similarity index 100% rename from src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-samsung-2GB-24EB.c rename to src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c diff --git a/src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-samsung-4GB-04EB.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c similarity index 100% rename from src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-samsung-4GB-04EB.c rename to src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c diff --git a/src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-samsung-4GB-04EB.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c similarity index 100% rename from src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-samsung-4GB-04EB.c rename to src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c diff --git a/src/mainboard/google/gru/sdram_params_933/Makefile.inc b/src/mainboard/google/gru/sdram_params_933/Makefile.inc deleted file mode 100644 index 8751e53..0000000 --- a/src/mainboard/google/gru/sdram_params_933/Makefile.inc +++ /dev/null @@ -1,28 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2016 Rockchip Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -sdram-params := -sdram-params += sdram-lpddr3-hynix-4GB -sdram-params += sdram-lpddr3-samsung-2GB-24EB -sdram-params += sdram-lpddr3-micron-2GB -sdram-params += sdram-lpddr3-samsung-4GB-04EB -sdram-params += sdram-lpddr3-micron-4GB - -$(foreach params,$(sdram-params), \ - $(eval cbfs-files-y += $(params)) \ - $(eval $(params)-file := $(params).c:struct) \ - $(eval $(params)-type := struct) \ - $(eval $(params)-compression := $(CBFS_COMPRESS_FLAG)) \ -) -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
by Julius Werner (Code Review) 11 May '17

11 May '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/19557 ) Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI. We need to turn the DPLL spread spectrum feature on to reduce the EMI noise for DDR on bob. Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com> Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> Reviewed-on: https://review.coreboot.org/19557 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/gru/Kconfig M src/soc/rockchip/rk3399/Kconfig M src/soc/rockchip/rk3399/clock.c 3 files changed, 104 insertions(+), 0 deletions(-) Approvals: Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 0fce7cc..0dba3e9 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -38,6 +38,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT select RAM_CODE_SUPPORT + select RK3399_SPREAD_SPECTRUM_DDR if BOARD_GOOGLE_BOB select RTC select SOC_ROCKCHIP_RK3399 select SPI_FLASH diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 65b31d5..ff857c0 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -24,4 +24,12 @@ int default -1 +config RK3399_SPREAD_SPECTRUM_DDR + bool "Spread-spectrum DDR clock" + default n + help + Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit + used to modulate the frequency of the Silicon Creations’ Fractional + PLL in order to reduce EMI. + endif diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index eb413a1..944ca6f 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -82,7 +82,22 @@ PLL_MODE_DEEP, PLL_DSMPD_MASK = 1, PLL_DSMPD_SHIFT = 3, + PLL_FRAC_MODE = 0, PLL_INTEGER_MODE = 1, + + /* PLL_CON4 */ + PLL_SSMOD_BP_MASK = 1, + PLL_SSMOD_BP_SHIFT = 0, + PLL_SSMOD_DIS_SSCG_MASK = 1, + PLL_SSMOD_DIS_SSCG_SHIFT = 1, + PLL_SSMOD_RESET_MASK = 1, + PLL_SSMOD_RESET_SHIFT = 2, + PLL_SSMOD_DOWNSPEAD_MASK = 1, + PLL_SSMOD_DOWNSPEAD_SHIFT = 3, + PLL_SSMOD_DIVVAL_MASK = 0Xf, + PLL_SSMOD_DIVVAL_SHIFT = 4, + PLL_SSMOD_SPREADAMP_MASK = 0x1f, + PLL_SSMOD_SPREADAMP_SHIFT = 8, /* PMUCRU_CLKSEL_CON0 */ PMU_PCLK_DIV_CON_MASK = 0x1f, @@ -324,6 +339,83 @@ /* pll enter normal mode */ write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT, PLL_MODE_NORM << PLL_MODE_SHIFT)); +} + +/* + * Configure the DPLL spread spectrum feature on memory clock. + * Configure sequence: + * 1. PLL been configured as frac mode, and DACPD should be set to 1’b0. + * 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with + * extern wave table). + * 3. set ssmod_disable_sscg = 1’b0, and set ssmod_bp = 1’b0. + * 4. Assert RESET = 1’b1 to SSMOD. + * 5. RESET = 1’b0 on SSMOD. + * 6. Adjust SPREAD/DIVVAL/DOWNSPREAD. + */ +static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) +{ + u32 divval; + + /* + * TODO find the root cause why is the delay needed, otherwise sometimes + * hang somewhere with reboot tests. + */ + udelay(30); + assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6); + + /* + * Need to acquire ~30kHZ which is the target modulation frequency. + * The modulation frequency ~ 30kHz= OSC_HZ/revdiv/128/divval + * (the 128 is the number points in the query table). + */ + divval = OSC_HZ / 128 / (30 * KHz) / dpll_cfg->refdiv; + + /* + * Use frac mode. + * Make sure the output frequency isn't offset, set 0 for Fractional + * part of feedback divide. + */ + write32(&cru_ptr->dpll_con[3], + RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, + PLL_FRAC_MODE << PLL_DSMPD_SHIFT)); + clrsetbits_le32(&cru_ptr->dpll_con[2], + PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT, + 0 << PLL_FRACDIV_SHIFT); + + /* + * Configure SSC divval. + * Spread amplitude range = 0.1 * SPREAD[4:0] (%). + * The below 8 means SPREAD[4:0] that appears to mitigate EMI on boards + * tested. Center and down spread modulation amplitudes based on the + * value of SPREAD. + * SPREAD[4:0] Center Spread Down Spread + * 0 0 0 + * 1 ±0.1% -0.10% + * 2 ±0.2% -0.20% + * 3 ±0.3% -0.30% + * 4 ±0.4% -0.40% + * 5 ±0.5% -0.50% + * ... + * 31 ±3.1% -3.10% + */ + write32(&cru_ptr->dpll_con[4], + RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT, + divval << PLL_SSMOD_DIVVAL_SHIFT)); + write32(&cru_ptr->dpll_con[4], + RK_CLRSETBITS(PLL_SSMOD_SPREADAMP_MASK << + PLL_SSMOD_SPREADAMP_SHIFT, + 8 << PLL_SSMOD_SPREADAMP_SHIFT)); + + /* Enable SSC for DPLL */ + write32(&cru_ptr->dpll_con[4], + RK_CLRBITS(PLL_SSMOD_BP_MASK << PLL_SSMOD_BP_SHIFT | + PLL_SSMOD_DIS_SSCG_MASK << PLL_SSMOD_DIS_SSCG_SHIFT)); + + /* Deassert reset SSMOD */ + write32(&cru_ptr->dpll_con[4], + RK_CLRBITS(PLL_SSMOD_RESET_MASK << PLL_SSMOD_RESET_SHIFT)); + + udelay(20); } static int pll_para_config(u32 freq_hz, struct pll_div *div) @@ -571,6 +663,9 @@ die("Unsupported SDRAM frequency, add to clock.c!"); } rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg); + + if (IS_ENABLED(CONFIG_RK3399_SPREAD_SPECTRUM_DDR)) + rkclk_set_dpllssc(&dpll_cfg); } #define SPI_CLK_REG_VALUE(bus, clk_div) \ -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by Julius Werner (Code Review) 11 May '17

11 May '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19558 ) Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
by Julius Werner (Code Review) 11 May '17

11 May '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19557 ) Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rockchip/rk3399: Add MIPI driver
by Anonymous Coward (Code Review) 11 May '17

11 May '17

nickey.yang(a)rock-chips.com has posted comments on this change. ( https://review.coreboot.org/19477 ) Change subject: rockchip/rk3399: Add MIPI driver ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/19477/5/src/soc/rockchip/rk3399/mipi.c File src/soc/rockchip/rk3399/mipi.c: Line 432: return; > You reduced the delay but you still didn't explain what it's for. Can you p The SOC tells the panel to enter the display mode, and then wait for the panel to complete the initialization.the last SOC switch to the video mode to display. I tried the value of 100ms - 500ms, and then use the button to reset devices a number of times, when 100ms, the panel will showe blurred screen occasionally.so i set 120ms,and everythings works well. -- To view, visit https://review.coreboot.org/19477 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sean Paul <seanpaul(a)chromium.org> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey.yang(a)rock-chips.com Gerrit-HasComments: Yes

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Change in coreboot[master]: rockchip/rk3399: Add MIPI driver
by build bot (Jenkins) (Code Review) 11 May '17

11 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19477 ) Change subject: rockchip/rk3399: Add MIPI driver ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9337/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53544/ : SUCCESS -- To view, visit https://review.coreboot.org/19477 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sean Paul <seanpaul(a)chromium.org> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey.yang(a)rock-chips.com Gerrit-HasComments: No

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Change in coreboot[master]: rockchip/rk3399: Add MIPI driver
by Anonymous Coward (Code Review) 11 May '17

11 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19477 to look at the new patch set (#6). Change subject: rockchip/rk3399: Add MIPI driver ...................................................................... rockchip/rk3399: Add MIPI driver This patch configures clock for mipi and then adds mipi driver for support innolux-p079zca mipi panel in rk3399 scarlet. Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Signed-off-by: Nickey Yang <nickey.yang(a)rock-chips.com> --- M src/soc/rockchip/common/include/soc/vop.h M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3399/Makefile.inc M src/soc/rockchip/rk3399/chip.h M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/include/soc/addressmap.h M src/soc/rockchip/rk3399/include/soc/clock.h A src/soc/rockchip/rk3399/include/soc/mipi.h A src/soc/rockchip/rk3399/mipi.c 10 files changed, 798 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/19477/6 -- To view, visit https://review.coreboot.org/19477 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sean Paul <seanpaul(a)chromium.org> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey.yang(a)rock-chips.com

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coreboot-gerrit May 2017