coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

1 participants
3888 discussions

Change in coreboot[master]: soc/amd/stoneyridge: Add CPU files
by Marshall Dawson (Code Review) 30 May '17

30 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19723 to look at the new patch set (#4). Change subject: soc/amd/stoneyridge: Add CPU files ...................................................................... soc/amd/stoneyridge: Add CPU files Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/include/cpu/amd/car.h M src/northbridge/amd/pi/Kconfig M src/soc/amd/common/Kconfig M src/soc/amd/common/Makefile.inc A src/soc/amd/common/amd_late_init.c A src/soc/amd/common/cache_as_ram.inc A src/soc/amd/common/heapmanager.c A src/soc/amd/common/spi.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/acpi/cpu.asl A src/soc/amd/stoneyridge/fixme.c A src/soc/amd/stoneyridge/model_15_init.c M src/vendorcode/amd/Kconfig M src/vendorcode/amd/pi/Kconfig M src/vendorcode/amd/pi/Makefile.inc 16 files changed, 975 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/19723/4 -- To view, visit https://review.coreboot.org/19723 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc: Add AMD Stoney Ridge southbridge code
by Marshall Dawson (Code Review) 30 May '17

30 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19722 to look at the new patch set (#4). Change subject: soc: Add AMD Stoney Ridge southbridge code ...................................................................... soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- A src/soc/amd/common/Kconfig A src/soc/amd/common/Makefile.inc A src/soc/amd/common/amd_defs.h A src/soc/amd/common/amd_pci_util.c A src/soc/amd/common/amd_pci_util.h A src/soc/amd/stoneyridge/Kconfig A src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/acpi/fch.asl A src/soc/amd/stoneyridge/acpi/lpc.asl A src/soc/amd/stoneyridge/acpi/pci_int.asl A src/soc/amd/stoneyridge/acpi/pcie.asl A src/soc/amd/stoneyridge/acpi/sleepstates.asl A src/soc/amd/stoneyridge/acpi/smbus.asl A src/soc/amd/stoneyridge/acpi/usb.asl A src/soc/amd/stoneyridge/bootblock/bootblock.c A src/soc/amd/stoneyridge/chip.c A src/soc/amd/stoneyridge/chip.h A src/soc/amd/stoneyridge/early_setup.c A src/soc/amd/stoneyridge/enable_usbdebug.c A src/soc/amd/stoneyridge/fadt.c A src/soc/amd/stoneyridge/gpio.c A src/soc/amd/stoneyridge/hda.c A src/soc/amd/stoneyridge/hudson.c A src/soc/amd/stoneyridge/ide.c A src/soc/amd/stoneyridge/imc.c A src/soc/amd/stoneyridge/include/amd_pci_int_defs.h A src/soc/amd/stoneyridge/include/amd_pci_int_types.h A src/soc/amd/stoneyridge/include/soc/gpio.h A src/soc/amd/stoneyridge/include/soc/hudson.h A src/soc/amd/stoneyridge/include/soc/imc.h A src/soc/amd/stoneyridge/include/soc/pci_devs.h A src/soc/amd/stoneyridge/include/soc/smbus.h A src/soc/amd/stoneyridge/include/soc/smi.h A src/soc/amd/stoneyridge/lpc.c A src/soc/amd/stoneyridge/pci.c A src/soc/amd/stoneyridge/pcie.c A src/soc/amd/stoneyridge/reset.c A src/soc/amd/stoneyridge/sata.c A src/soc/amd/stoneyridge/sd.c A src/soc/amd/stoneyridge/sm.c A src/soc/amd/stoneyridge/smbus.c A src/soc/amd/stoneyridge/smbus_spd.c A src/soc/amd/stoneyridge/smi.c A src/soc/amd/stoneyridge/smi_util.c A src/soc/amd/stoneyridge/smihandler.c A src/soc/amd/stoneyridge/uart.c A src/soc/amd/stoneyridge/usb.c M src/vendorcode/amd/pi/Makefile.inc 48 files changed, 5,007 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/19722/4 -- To view, visit https://review.coreboot.org/19722 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: purism/librem13v1: Rename librem13 to librem13v1
by Youness Alaoui (Code Review) 30 May '17

30 May '17

Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/19931 ) Change subject: purism/librem13v1: Rename librem13 to librem13v1 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/19931/1/src/mainboard/purism/librem13v1/Kco… File src/mainboard/purism/librem13v1/Kconfig: PS1, Line 38: Librem 13 v1 > IIRC, flashrom uses another path and another set of values if it Humm.. we actually have the VERSION number in smbios already, so maybe it's better to keep it as "Librem 13" for both v1 and v2 hardware, and just have MAINBOARD_VERSION == 1.0 or 2.0 for the v1 vs. v2 (the MAINBOARD_VERSION is already set correctly) -- To view, visit https://review.coreboot.org/19931 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I23fa977717230c2001868741bb684e9633a2c0bb Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

1 0

Change in coreboot[master]: console/flashsconsole: Add spi flash console for debugging
by Julius Werner (Code Review) 30 May '17

30 May '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19849 ) Change subject: console/flashsconsole: Add spi flash console for debugging ...................................................................... Patch Set 11: Code-Review+2 I was about to say you could try to tie the romstage compilation to CONFIG_EARLY_CONSOLE so you could at least disable that and still get ramstage on Broadwell. But it seems like we actually removed the EARLY_CONSOLE option years ago, so that won't work. ^^ -- To view, visit https://review.coreboot.org/19849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: arch: Unify basic cache clearing API
by Julius Werner (Code Review) 30 May '17

30 May '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/19788 ) Change subject: arch: Unify basic cache clearing API ...................................................................... arch: Unify basic cache clearing API Caching is a very architecture-specific thing, but most architectures have a cache in general. Therefore it can be useful to have a generic architecture-independent API to perform simple cache management tasks from common code. We have already standardized on the dcache_clean/invalidate naming scheme that originally comes from ARM in libpayload, so let's just do the same for coreboot. Unlike libpayload, there are other things than just DMA coherency we may want to achieve with those functions, so actually implement them for real even on architectures with cache-snooping DMA like x86. (In the future, we may find applications like this in libpayload as well and should probably rethink the API there... maybe move the current functionality to a separate dma_map/unmap API instead. But that's beyond scope of this patch.) Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/19788 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> --- M src/arch/mips/include/arch/cache.h A src/arch/power8/include/arch/cache.h A src/arch/riscv/include/arch/cache.h M src/arch/x86/include/arch/cache.h 4 files changed, 107 insertions(+), 0 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Philippe Mathieu-Daudé: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h index de1209a..d90a85f 100644 --- a/src/arch/mips/include/arch/cache.h +++ b/src/arch/mips/include/arch/cache.h @@ -41,4 +41,11 @@ /* Invalidate all caches: instruction, data, L2 data */ void cache_invalidate_all(uintptr_t start, size_t size); +/* TODO: Global cache API. Implement properly once we finally have a MIPS board + again where we can figure out what exactly these should be doing. */ +static inline void cache_sync_instructions(void) {} +static inline void dcache_clean_all(void) {} +static inline void dcache_invalidate_all(void) {} +static inline void dcache_clean_invalidate_all(void) {} + #endif /* __MIPS_ARCH_CACHE_H */ diff --git a/src/arch/power8/include/arch/cache.h b/src/arch/power8/include/arch/cache.h new file mode 100644 index 0000000..9b91ac2 --- /dev/null +++ b/src/arch/power8/include/arch/cache.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef ARCH_CACHE_H +#define ARCH_CACHE_H + +/* TODO: implement these API stubs once caching is available on Power 8 */ +static inline void cache_sync_instructions(void) {} +static inline void dcache_clean_all(void) {} +static inline void dcache_invalidate_all(void) {} +static inline void dcache_clean_invalidate_all(void) {} + +#endif /* ARCH_CACHE_H */ diff --git a/src/arch/riscv/include/arch/cache.h b/src/arch/riscv/include/arch/cache.h new file mode 100644 index 0000000..ba7c33d --- /dev/null +++ b/src/arch/riscv/include/arch/cache.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef ARCH_CACHE_H +#define ARCH_CACHE_H + +/* TODO: implement these API stubs once caching is available on RISC-V */ +static inline void cache_sync_instructions(void) {} +static inline void dcache_clean_all(void) {} +static inline void dcache_invalidate_all(void) {} +static inline void dcache_clean_invalidate_all(void) {} + +#endif /* ARCH_CACHE_H */ diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h index 687d3bf..9f7cda2 100644 --- a/src/arch/x86/include/arch/cache.h +++ b/src/arch/x86/include/arch/cache.h @@ -31,6 +31,9 @@ #ifndef ARCH_CACHE_H #define ARCH_CACHE_H +#include <arch/early_variables.h> +#include <cpu/x86/cache.h> + /* * For the purposes of the currently executing CPU loading code that will be * run there aren't any cache coherency operations required. This just provides @@ -38,4 +41,21 @@ */ static inline void cache_sync_instructions(void) {} +/* Executing WBINVD when running out of CAR would not be good, prevent that. */ +static inline void dcache_clean_invalidate_all(void) +{ + if (!car_active()) + wbinvd(); +} +static inline void dcache_clean_all(void) +{ + /* x86 doesn't have a "clean without invalidate", fall back to both. */ + dcache_clean_invalidate_all(); +} +static inline void dcache_invalidate_all(void) +{ + if (!car_active()) + invd(); +} + #endif /* ARCH_CACHE_H */ -- To view, visit https://review.coreboot.org/19788 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: arch/x86: Add function to determine if we're currently runni...
by Julius Werner (Code Review) 30 May '17

30 May '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/19787 ) Change subject: arch/x86: Add function to determine if we're currently running from CAR ...................................................................... arch/x86: Add function to determine if we're currently running from CAR This patch adds a simple function that can be used to check if CAR_GLOBALs are currently being read from CAR or from DRAM. Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/19787 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> --- M src/arch/x86/include/arch/early_variables.h M src/cpu/x86/car.c 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Philippe Mathieu-Daudé: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index d0cfda7..2c6c539 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -44,12 +44,20 @@ { return var; } + +static inline int car_active(void) +{ + return 1; +} #else /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); /* Get and update a CAR_GLOBAL pointing elsewhere in car.global_data*/ void *car_sync_var_ptr(void *var); + +/* Return 1 when currently running with globals in Cache-as-RAM, 0 otherwise. */ +int car_active(void); #endif /* ENV_VERSTAGE */ /* Get and set a primitive type global variable. */ @@ -73,6 +81,7 @@ #else #define CAR_GLOBAL static inline void *car_get_var_ptr(void *var) { return var; } +static inline int car_active(void) { return 0; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) (var) = (val) diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 606a35e..1b02f8b 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -113,6 +113,11 @@ return mig_var; } +int car_active(void) +{ + return !car_migrated; +} + static void do_car_migrate_variables(void) { void *migrated_base; -- To view, visit https://review.coreboot.org/19787 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: tegra210: Remove fake cpu_reset()
by Julius Werner (Code Review) 30 May '17

30 May '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/19786 ) Change subject: tegra210: Remove fake cpu_reset() ...................................................................... tegra210: Remove fake cpu_reset() The Tegra210 SoC never had a proper cpu_reset() implementation, so it's pointless to pretend there is one. Most ARM SoCs/boards only define hard_reset() at the moment anyway, so let's stick with that. Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/19786 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> --- M src/mainboard/google/foster/pmic.c M src/mainboard/google/smaug/pmic.c M src/soc/nvidia/tegra210/Makefile.inc D src/soc/nvidia/tegra210/reset.c 4 files changed, 4 insertions(+), 32 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Philippe Mathieu-Daudé: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 2e655b5..2eeccb2 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -43,8 +43,8 @@ if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); - /* Reset the SoC on any PMIC write error */ - cpu_reset(); + /* Reset the board on any PMIC write error */ + hard_reset(); } else { if (delay) udelay(500); diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index cba555a..25e870a 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -46,8 +46,8 @@ if (i2c_writeb(bus, chip, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); - /* Reset the SoC on any PMIC write error */ - cpu_reset(); + /* Reset the board on any PMIC write error */ + hard_reset(); } else { if (delay) udelay(500); diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 756d413..a2b50c9 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -12,7 +12,6 @@ bootblock-y += padconfig.c bootblock-y += power.c bootblock-y += funitcfg.c -bootblock-y += reset.c bootblock-y += ../tegra/gpio.c bootblock-y += ../tegra/i2c.c bootblock-y += ../tegra/pingroup.c @@ -41,7 +40,6 @@ romstage-y += ccplex.c romstage-y += clock.c romstage-y += cpu.c -romstage-y += reset.c romstage-y += spi.c romstage-y += i2c.c romstage-y += dma.c @@ -87,7 +85,6 @@ ramstage-y += monotonic_timer.c ramstage-y += padconfig.c ramstage-y += funitcfg.c -ramstage-y += reset.c ramstage-y += ram_code.c ramstage-y += ../tegra/apbmisc.c ramstage-y += ../tegra/gpio.c diff --git a/src/soc/nvidia/tegra210/reset.c b/src/soc/nvidia/tegra210/reset.c deleted file mode 100644 index 38a97d8..0000000 --- a/src/soc/nvidia/tegra210/reset.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <reset.h> - -/* - * Promote cpu_reset() to a hard_reset(). A shallower reset can be added, - * if needed, at a later time. - */ -void cpu_reset(void) -{ - hard_reset(); -} -- To view, visit https://review.coreboot.org/19786 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: arm64: Align cache maintenance code with libpayload and ARM32
by Julius Werner (Code Review) 30 May '17

30 May '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/19785 ) Change subject: arm64: Align cache maintenance code with libpayload and ARM32 ...................................................................... arm64: Align cache maintenance code with libpayload and ARM32 coreboot and libpayload currently use completely different code to perform a full cache flush on ARM64, with even different function names. The libpayload code is closely inspired by the ARM32 version, so for the sake of overall consistency let's sync coreboot to that. Also align a few other cache management details to work the same way as the corresponding ARM32 parts (such as only flushing but not invalidating the data cache after loading a new stage, which may have a small performance benefit). Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/19785 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M payloads/libpayload/arch/arm64/cache.c M src/arch/arm64/armv8/Makefile.inc M src/arch/arm64/armv8/cache.c D src/arch/arm64/armv8/cache_helpers.S M src/arch/arm64/armv8/cpu.S M src/arch/arm64/armv8/mmu.c D src/arch/arm64/include/arch/cache_helpers.h M src/arch/arm64/include/armv8/arch/cache.h 8 files changed, 93 insertions(+), 194 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index 0755c56..2d42522 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -119,7 +119,11 @@ void cache_sync_instructions(void) { - dcache_clean_all(); /* includes trailing DSB (in assembly) */ + uint32_t sctlr = raw_read_sctlr_current(); + if (sctlr & SCTLR_C) + dcache_clean_all(); /* includes trailing DSB (assembly) */ + else if (sctlr & SCTLR_I) + dcache_clean_invalidate_all(); icache_invalidate_all(); /* includes leading DSB and trailing ISB */ } diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index a7a6b19..21ebf70 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -28,7 +28,6 @@ bootblock-y += bootblock.S endif bootblock-y += cache.c -bootblock-y += cache_helpers.S bootblock-y += cpu.S bootblock-y += mmu.c @@ -50,7 +49,6 @@ verstage-y += cache.c verstage-y += cpu.S -verstage-y += cache_helpers.S verstage-y += exception.c verstage-generic-ccopts += $(armv8_flags) @@ -63,7 +61,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) romstage-y += cache.c -romstage-y += cache_helpers.S romstage-y += cpu.S romstage-y += exception.c romstage-y += mmu.c @@ -80,7 +77,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) ramstage-y += cache.c -ramstage-y += cache_helpers.S ramstage-y += cpu.S ramstage-y += exception.c ramstage-y += mmu.c diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 4f91de0..4b99cd7 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -34,7 +34,6 @@ #include <stdint.h> #include <arch/cache.h> -#include <arch/cache_helpers.h> #include <arch/lib_helpers.h> #include <program_loading.h> @@ -121,7 +120,11 @@ void cache_sync_instructions(void) { - flush_dcache_all(DCCISW); /* includes trailing DSB (in assembly) */ + uint32_t sctlr = raw_read_sctlr_current(); + if (sctlr & SCTLR_C) + dcache_clean_all(); /* includes trailing DSB (assembly) */ + else if (sctlr & SCTLR_I) + dcache_clean_invalidate_all(); icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */ } @@ -131,6 +134,10 @@ */ void arch_segment_loaded(uintptr_t start, size_t size, int flags) { - dcache_clean_invalidate_by_mva((void *)start, size); + uint32_t sctlr = raw_read_sctlr_current(); + if (sctlr & SCTLR_C) + dcache_clean_by_mva((void *)start, size); + else if (sctlr & SCTLR_I) + dcache_clean_invalidate_by_mva((void *)start, size); icache_invalidate_all(); } diff --git a/src/arch/arm64/armv8/cache_helpers.S b/src/arch/arm64/armv8/cache_helpers.S deleted file mode 100644 index b94bc30..0000000 --- a/src/arch/arm64/armv8/cache_helpers.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch/asm.h> -#include <arch/cache_helpers.h> - - /* --------------------------------------------------------------- - * Data cache operations by set/way to the level specified - * - * The main function, do_dcsw_op requires: - * x0: The operation type (0-2), as defined in cache_helpers.h - * x3: The last cache level to operate on - * x9: clidr_el1 - * and will carry out the operation on each data cache from level 0 - * to the level in x3 in sequence - * - * The dcsw_op macro sets up the x3 and x9 parameters based on - * clidr_el1 cache information before invoking the main function - * --------------------------------------------------------------- - */ - -.macro dcsw_op shift, fw, ls - mrs x9, clidr_el1 - ubfx x3, x9, \shift, \fw - lsl x3, x3, \ls - b do_dcsw_op -.endm - -ENTRY(do_dcsw_op) - cbz x3, exit - mov x10, xzr - adr x14, dcsw_loop_table // compute inner loop address - add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions - mov x0, x9 - mov w8, #1 -loop1: - add x2, x10, x10, lsr #1 // work out 3x current cache level - lsr x1, x0, x2 // extract cache type bits from clidr - and x1, x1, #7 // mask the bits for current cache only - cmp x1, #2 // see what cache we have at this level - b.lt level_done // nothing to do if no cache or icache - - msr csselr_el1, x10 // select current cache level in csselr - isb // isb to sych the new cssr&csidr - mrs x1, ccsidr_el1 // read the new ccsidr - and x2, x1, #7 // extract the length of the cache lines - add x2, x2, #4 // add 4 (line length offset) - ubfx x4, x1, #3, #10 // maximum way number - clz w5, w4 // bit position of way size increment - lsl w9, w4, w5 // w9 = aligned max way number - lsl w16, w8, w5 // w16 = way number loop decrement - orr w9, w10, w9 // w9 = combine way and cache number - ubfx w6, w1, #13, #15 // w6 = max set number - lsl w17, w8, w2 // w17 = set number loop decrement - dsb sy // barrier before we start this level - br x14 // jump to DC operation specific loop - -level_done: - add x10, x10, #2 // increment cache number - cmp x3, x10 - b.gt loop1 - msr csselr_el1, xzr // select cache level 0 in csselr - dsb sy // barrier to complete final cache operation - isb -exit: - ret -ENDPROC(do_dcsw_op) - -.macro dcsw_loop _op -loop2_\_op: - lsl w7, w6, w2 // w7 = aligned max set number - -loop3_\_op: - orr w11, w9, w7 // combine cache, way and set number - dc \_op, x11 - subs w7, w7, w17 // decrement set number - b.ge loop3_\_op - - subs x9, x9, x16 // decrement way number - b.ge loop2_\_op - - b level_done -.endm - -dcsw_loop_table: - dcsw_loop isw - dcsw_loop cisw - dcsw_loop csw - -ENTRY(flush_dcache_louis) - dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT -ENDPROC(flush_dcache_louis) - -ENTRY(flush_dcache_all) - dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT -ENDPROC(flush_dcache_all) diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 711c338..1bb8c83 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -1,8 +1,8 @@ /* - * Based on arch/arm/include/asm/cacheflush.h + * Optimized assembly for low-level CPU operations on ARM64 processors. * - * Copyright (C) 1999-2002 Russell King. - * Copyright (C) 2012 ARM Ltd. + * Copyright (c) 2010 Per Odlund <per.odlund(a)armagedon.se> + * Copyright (c) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,11 +15,77 @@ */ #include <arch/asm.h> -#include <arch/cache_helpers.h> + +.macro dcache_apply_all crm + dsb sy + mrs x0, clidr_el1 // read CLIDR + and w3, w0, #0x07000000 // narrow to LoC + lsr w3, w3, #23 // left align LoC (low 4 bits) + cbz w3, 5f //done + + mov w10, #0 // w10 = 2 * cache level + mov w8, #1 // w8 = constant 0b1 + +1: //next_level + add w2, w10, w10, lsr #1 // calculate 3 * cache level + lsr w1, w0, w2 // extract 3-bit cache type for this level + and w1, w1, #0x7 // w1 = cache type + cmp w1, #2 // is it data or i&d? + b.lt 4f //skip + msr csselr_el1, x10 // select current cache level + isb // sync change of csselr + mrs x1, ccsidr_el1 // w1 = read ccsidr + and w2, w1, #7 // w2 = log2(linelen_bytes) - 4 + add w2, w2, #4 // w2 = log2(linelen_bytes) + ubfx w4, w1, #3, #10 // w4 = associativity - 1 (also + // max way number) + clz w5, w4 // w5 = 32 - log2(ways) + // (bit position of way in DC) + lsl w9, w4, w5 // w9 = max way number + // (aligned for DC) + lsl w16, w8, w5 // w16 = amount to decrement (way + // number per iteration) +2: //next_way + ubfx w7, w1, #13, #15 // w7 = max set #, right aligned + lsl w7, w7, w2 // w7 = max set #, DC aligned + lsl w17, w8, w2 // w17 = amount to decrement (set + // number per iteration) + +3: //next_set + orr w11, w10, w9 // w11 = combine way # & cache # + orr w11, w11, w7 // ... and set # + dc \crm, x11 // clean and/or invalidate line + subs w7, w7, w17 // decrement set number + b.ge 3b //next_set + subs x9, x9, x16 // decrement way number + b.ge 2b //next_way + +4: //skip + add w10, w10, #2 // increment 2 *cache level + cmp w3, w10 // Went beyond LoC? + b.gt 1b //next_level + +5: //done + dsb sy + isb + ret +.endm + +ENTRY(dcache_invalidate_all) + dcache_apply_all crm=isw +ENDPROC(dcache_invalidate_all) + +ENTRY(dcache_clean_all) + dcache_apply_all crm=csw +ENDPROC(dcache_clean_all) + +ENTRY(dcache_clean_invalidate_all) + dcache_apply_all crm=cisw +ENDPROC(dcache_clean_invalidate_all) /* * Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a - * known state regarding caches/SCTLR/PSTATE. Completely cleans and invalidates + * known state regarding caches/SCTLR/PSTATE. Completely invalidates * icache/dcache, disables MMU and dcache (if active), and enables unaligned * accesses, icache and branch prediction (if inactive). Seeds the stack and * initializes SP_EL0. Clobbers R22 and R23. @@ -41,9 +107,8 @@ msr sctlr_el3, x22 isb - /* Flush and invalidate dcache */ - mov x0, #DCCISW - bl flush_dcache_all + /* Invalidate dcache */ + bl dcache_invalidate_all /* Deactivate MMU (0), Alignment Check (1) and DCache (2) */ and x22, x22, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2) diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 9280fc2..55bd703 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -37,7 +37,6 @@ #include <arch/mmu.h> #include <arch/lib_helpers.h> #include <arch/cache.h> -#include <arch/cache_helpers.h> /* This just caches the next free table slot (okay to do since they fill up from * bottom to top and can never be freed up again). It will reset to its initial @@ -295,7 +294,7 @@ */ void mmu_disable(void) { - flush_dcache_all(DCCISW); + dcache_clean_invalidate_all(); uint32_t sctlr = raw_read_sctlr_el3(); sctlr &= ~(SCTLR_C | SCTLR_M); raw_write_sctlr_el3(sctlr); diff --git a/src/arch/arm64/include/arch/cache_helpers.h b/src/arch/arm64/include/arch/cache_helpers.h deleted file mode 100644 index 2919d99..0000000 --- a/src/arch/arm64/include/arch/cache_helpers.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __CACHE_HELPERS_H - -/* CLIDR definitions */ -#define LOUIS_SHIFT 21 -#define LOC_SHIFT 24 -#define CLIDR_FIELD_WIDTH 3 - -/* CSSELR definitions */ -#define LEVEL_SHIFT 1 - -/* D$ set/way op type defines */ -#define DCISW 0x0 -#define DCCISW 0x1 -#define DCCSW 0x2 - -#endif /* __CACHE_HELPERS_H */ diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 84f051d..3647290 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -67,11 +67,10 @@ /* dcache invalidate by virtual address to PoC */ void dcache_invalidate_by_mva(void const *addr, size_t len); -/* dcache invalidate all */ -void flush_dcache_all(int op_type); - -/* flush the dcache up to the Level of Unification Inner Shareable */ -void flush_dcache_louis(int op_type); +/* dcache clean and/or invalidate all sets/ways to PoC */ +void dcache_clean_all(void); +void dcache_invalidate_all(void); +void dcache_clean_invalidate_all(void); /* returns number of bytes per cache line */ unsigned int dcache_line_bytes(void); -- To view, visit https://review.coreboot.org/19785 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: arm64: Align cache maintenance code with libpayload and ARM32
by Julius Werner (Code Review) 30 May '17

30 May '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19785 ) Change subject: arm64: Align cache maintenance code with libpayload and ARM32 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/19785/1/src/arch/arm64/armv8/cache.c File src/arch/arm64/armv8/cache.c: Line 126: else if (sctlr & SCTLR_I) > OK. That makes sense. I was confused by your comment "will just flush those Oh, right... reading that again, that was the wrong explanation. I have to think about how this worked again every time... -- To view, visit https://review.coreboot.org/19785 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

1 0

Change in coreboot[master]: console/flashsconsole: Add spi flash console for debugging
by Youness Alaoui (Code Review) 30 May '17

30 May '17

Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/19849 ) Change subject: console/flashsconsole: Add spi flash console for debugging ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/19849/11/src/drivers/spi/flashconsole.c File src/drivers/spi/flashconsole.c: Line 102: line_buffer[len++] = c; > Ah. Sorry. I misread the flow and completely missed that you were checking Np! Thanks for the review :) -- To view, visit https://review.coreboot.org/19849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2017