coreboot-gerrit May 2017

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Change in coreboot[master]: ec/lenovo/h8: Add BDC detection support
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19809 ) Change subject: ec/lenovo/h8: Add BDC detection support ...................................................................... ec/lenovo/h8: Add BDC detection support Add support for detecting BDC. Allows to turn off power to BDC if no card is installed. Should fix Bluetooth indicator always on. Add the following devicetree values: * has_bdc_detection Set to one to indicate that the following register are sane. * bdc_gpio_num SB GPIO num to read. * bdc_gpio_lvl SB GPIO level for card to be present (usually zero). Don't enable BDC power if no card is detected. As there are no devicetree values yet, the new code doesn't have any effect. Change-Id: I506de2eca4b820e6d82de6b2c48a5440462e1db5 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/ec/lenovo/h8/Makefile.inc A src/ec/lenovo/h8/bluetooth.c M src/ec/lenovo/h8/chip.h M src/ec/lenovo/h8/h8.c M src/ec/lenovo/h8/h8.h 5 files changed, 80 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/19809/1 diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index da9cee1..e989dee 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_EC_LENOVO_H8),y) ramstage-y += h8.c +ramstage-y += bluetooth.c smm-y += smm.c endif diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c new file mode 100644 index 0000000..3e7b1c1 --- /dev/null +++ b/src/ec/lenovo/h8/bluetooth.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> +#include <console/console.h> +#include <device/device.h> +#include <ec/acpi/ec.h> +#include <option.h> + +#include "h8.h" +#include "chip.h" + +/* + * Controls BDC (Bluetooth dauther card) power. + */ +void h8_bluetooth_enable(int on) +{ + if (on) + ec_set_bit(0x3a, 4); + else + ec_clr_bit(0x3a, 4); +} + +/* + * Detect BDC on supported MBs. + */ +bool h8_has_bdc(struct device *dev) +{ + struct ec_lenovo_h8_config *conf = dev->chip_info; + + if (!conf->has_bdc_detection) { + printk(BIOS_INFO, "H8: BDC detection not implemented. " + "Assuming BDC installed.\n"); + return 1; + } + + if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) { + printk(BIOS_INFO, "H8: BDC installed.\n"); + return 1; + } + + printk(BIOS_INFO, "H8: BDC not installed.\n"); + return 0; +} + +/* + * Return BDC NVRAM setting. + */ +bool h8_bluetooth_nv_disable(void) +{ + u8 val; + + if (get_option(&val, "bluetooth") != CB_SUCCESS) + return 0; + + return !val; +} diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index bb6eb05..d62312d 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -46,6 +46,10 @@ u8 has_keyboard_backlight; u8 has_power_management_beeps; u8 has_uwb; + u8 has_bdc_detection; + + u8 bdc_gpio_num; + u8 bdc_gpio_lvl; }; #endif /* EC_LENOVO_H8EC_CHIP_H */ diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index b259d9a..bc0afb8 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -28,14 +28,6 @@ #include "h8.h" #include "chip.h" -static void h8_bluetooth_enable(int on) -{ - if (on) - ec_set_bit(0x3a, 4); - else - ec_clr_bit(0x3a, 4); -} - void h8_trackpoint_enable(int on) { ec_write(H8_TRACKPOINT_CTRL, @@ -284,8 +276,7 @@ if (get_option(&val, "volume") == CB_SUCCESS && !acpi_is_wakeup_s3()) ec_write(H8_VOLUME_CONTROL, val); - if (get_option(&val, "bluetooth") != CB_SUCCESS) - val = 1; + val = h8_has_bdc(dev) && !h8_bluetooth_nv_disable(); h8_bluetooth_enable(val); if (get_option(&val, "wwan") != CB_SUCCESS) diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index 42d279f..6ecc9bc 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -17,6 +17,7 @@ #define EC_LENOVO_H8_H #include <stdint.h> +#include <device/device.h> void h8_trackpoint_enable(int on); void h8_wlan_enable(int on); @@ -30,6 +31,10 @@ void h8_mainboard_init_dock (void); +void h8_bluetooth_enable(int on); +bool h8_bluetooth_nv_disable(void); +bool h8_has_bdc(struct device *dev); + /* EC registers */ #define H8_CONFIG0 0x00 #define H8_CONFIG0_EVENTS_ENABLE 0x02 -- To view, visit https://review.coreboot.org/19809 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I506de2eca4b820e6d82de6b2c48a5440462e1db5 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: src/southbridge/i82801gx: Include a default SeaBIOS config file
by Arthur Heymans (Code Review) 21 May '17

21 May '17

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Change in coreboot[master]: src/southbridge/i82801gx: Include a default SeaBIOS config file
by Arthur Heymans (Code Review) 21 May '17

21 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19690 ) Change subject: src/southbridge/i82801gx: Include a default SeaBIOS config file ...................................................................... Patch Set 1: > > (1 comment) > > > > > Why can’t this be enabled by default for coreboot? > > > > Why isn't it the global default in SeaBIOS? > > The SeaBIOS ATA DMA setting isn't safe on PATA, nor is it safe on > SATA to PATA adapters. On those devices, a complicated controller > specific negotiation must be done to determine the DMA level. The > SeaBIOS ATA DMA support works fine on regular SATA devices, but > almost all new machines use an AHCI controller now. Many boards with this southbridge do feature PATA ports, but don't have ACHI for SATA... -- To view, visit https://review.coreboot.org/19690 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6a6e79ea6cd0a14070b8092aefa477b9e3a0c4b1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/ivybridge: Improve CAS freq selection
by Arthur Heymans (Code Review) 21 May '17

21 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19717 ) Change subject: nb/intel/ivybridge: Improve CAS freq selection ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/19717/1/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_ivy.c: Line 327: ctrl->tCK = 0; > Please set `base_freq` too, to make it clear that the recursion breaks. ok. Line 349: ref_100mhz_support ? "yes" : "no"); > This is now printed everytime this gets called. Why not keep the ok Line 366: ivb_normalize_tclk(ctrl, ref_100mhz_support); > What happens after this line? hmm it should not normalise since this is done at the beginning of the loop... I'll add a comment to clarify the code flow PS1, Line 373: (1000 << 8) > This should be a defined value... ok -- To view, visit https://review.coreboot.org/19717 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1df20a0a723dc515686a766ad1b0567d815f6e89 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: mb/lenvovo/*: Clean mainboard.c and devicetree
by build bot (Jenkins) (Code Review) 21 May '17

21 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19494 ) Change subject: mb/lenvovo/*: Clean mainboard.c and devicetree ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54104/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/9840/ : SUCCESS -- To view, visit https://review.coreboot.org/19494 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenvovo/*: Clean mainboard.c and devicetree
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Hello Paul Menzel, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19494 to look at the new patch set (#6). Change subject: mb/lenvovo/*: Clean mainboard.c and devicetree ...................................................................... mb/lenvovo/*: Clean mainboard.c and devicetree * Move board specific SPI registers to devicetree * Remove unused headers * Remove obsolete methods * Fix coding style * Fix Thinkpad L520 SPI lvscc register Except for Thinkpad L520, no functional change has been done, just moving stuff around. Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/l520/mainboard.c M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/s230u/mainboard.c M src/mainboard/lenovo/t400/mainboard.c M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420/mainboard.c M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t420s/mainboard.c M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/mainboard.c M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t520/mainboard.c M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/t530/mainboard.c M src/mainboard/lenovo/t60/mainboard.c M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/mainboard.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/mainboard.c M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/lenovo/x230/mainboard.c M src/mainboard/lenovo/x60/mainboard.c 25 files changed, 102 insertions(+), 277 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/19494/6 -- To view, visit https://review.coreboot.org/19494 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: ec/lenovo/h8: Add panic method
by build bot (Jenkins) (Code Review) 21 May '17

21 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19695 ) Change subject: ec/lenovo/h8: Add panic method ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9839/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54103/ : SUCCESS -- To view, visit https://review.coreboot.org/19695 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: console: Provide callback in die() path
by build bot (Jenkins) (Code Review) 21 May '17

21 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19696 ) Change subject: console: Provide callback in die() path ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9838/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54102/ : SUCCESS -- To view, visit https://review.coreboot.org/19696 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I71f8ddfc96047e8a0d39f084588db1fe2f251612 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 35: Code-Review+1 -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-PatchSet: 35 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/*/romstage: Remove COM IO port
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/19571 ) Change subject: mb/lenovo/*/romstage: Remove COM IO port ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/19571/1/src/mainboard/lenovo/l520/romstage.c File src/mainboard/lenovo/l520/romstage.c: Line 28: pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c); > maybe use macros defined for both values and register offsets? That can be done in a seperate commit. Line 29: pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611); > Not the scope of this patch, but this decode range may be for the LPC docki That's for HDAPS. -- To view, visit https://review.coreboot.org/19571 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017