coreboot-gerrit May 2017

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Change in coreboot[master]: src/southbridge/i82801gx: Include a default SeaBIOS config file
by Arthur Heymans (Code Review) 21 May '17

21 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19690 ) Change subject: src/southbridge/i82801gx: Include a default SeaBIOS config file ...................................................................... Patch Set 1: I suppose the best thing to do now is to abandon this and document on the wiki/documentation how users can get a speedup if only using sata? -- To view, visit https://review.coreboot.org/19690 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6a6e79ea6cd0a14070b8092aefa477b9e3a0c4b1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: src/southbridge/i82801gx: Include a default SeaBIOS config file
by Kevin O'Connor (Code Review) 21 May '17

21 May '17

Kevin O'Connor has posted comments on this change. ( https://review.coreboot.org/19690 ) Change subject: src/southbridge/i82801gx: Include a default SeaBIOS config file ...................................................................... Patch Set 1: > > The SeaBIOS ATA DMA setting isn't safe on PATA, nor is it safe on > > SATA to PATA adapters. > > Thanks for the clarification. > > How about a whitelist in SeaBIOS then? For the ICH7 that would be > DID > 0x27c0 and 0x27c4 if I read the spec update correctly. If we'd want > to be extra sure, we could check that combined mode is disabled > (PCI+0x90 bits 0..1 should be zero). A whitelist would be fine, but what would we whitelist? How would we know if a port is PATA, SATA, or PATA over SATA bridge? It's been a while since I looked at the ATA specs, so it may be possible to do something sane. My recollection was that enabling DMA on ATA was controller specific and thus too much of a hassle to support in SeaBIOS. -- To view, visit https://review.coreboot.org/19690 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6a6e79ea6cd0a14070b8092aefa477b9e3a0c4b1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: src/southbridge/i82801gx: Include a default SeaBIOS config file
by Kevin O'Connor (Code Review) 21 May '17

21 May '17

Kevin O'Connor has posted comments on this change. ( https://review.coreboot.org/19690 ) Change subject: src/southbridge/i82801gx: Include a default SeaBIOS config file ...................................................................... Patch Set 1: > > > (1 comment) > > > > > > > Why can’t this be enabled by default for coreboot? > > > > > > Why isn't it the global default in SeaBIOS? > > > > The SeaBIOS ATA DMA setting isn't safe on PATA, nor is it safe on > > SATA to PATA adapters. On those devices, a complicated > controller > > specific negotiation must be done to determine the DMA level. > The > > SeaBIOS ATA DMA support works fine on regular SATA devices, but > > almost all new machines use an AHCI controller now. > > Many boards with this southbridge do feature PATA ports, but don't > have ACHI for SATA... If this southbridge has PATA ports, then I would not proceed with this patch. The SeaBIOS DMA support is not complete on real PATA drives. -- To view, visit https://review.coreboot.org/19690 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6a6e79ea6cd0a14070b8092aefa477b9e3a0c4b1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/*/romstage: Remove COM IO port
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/19571 ) Change subject: mb/lenovo/*/romstage: Remove COM IO port ...................................................................... mb/lenovo/*/romstage: Remove COM IO port All those boards do not have a serial port. Don't attempt to decode the COMA/COMB IO range. Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/19571 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c 10 files changed, 9 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 6c93eed..84590ae 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -25,12 +25,11 @@ void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); } void rcba_config(void) diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 610eb89..43a3d52 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -42,7 +42,6 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000); /* Memory map KB9012 EC registers */ diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index 766b019..94b8d62 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -24,14 +24,11 @@ /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index e32337a..d7f1c23 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -27,14 +27,11 @@ /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index a17ec52..89ef10c 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -27,14 +27,11 @@ /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index fd17f21..f84bc0d 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -41,14 +41,11 @@ /* T520 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 050e8cf..c454ec7 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -28,14 +28,11 @@ /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index 574d02b..a07df70 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -42,14 +42,11 @@ /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 15d2c84..fa52778 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -38,14 +38,11 @@ /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index e68843c..4d8f330 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -41,14 +41,11 @@ /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -- To view, visit https://review.coreboot.org/19571 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenvovo/*: Clean mainboard.c and devicetree
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/19494 ) Change subject: mb/lenvovo/*: Clean mainboard.c and devicetree ...................................................................... mb/lenvovo/*: Clean mainboard.c and devicetree * Move board specific SPI registers to devicetree * Remove unused headers * Remove obsolete methods * Fix coding style * Fix Thinkpad L520 SPI lvscc register Except for Thinkpad L520, no functional change has been done, just moving stuff around. Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/19494 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/l520/mainboard.c M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/s230u/mainboard.c M src/mainboard/lenovo/t400/mainboard.c M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420/mainboard.c M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t420s/mainboard.c M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/mainboard.c M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t520/mainboard.c M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/t530/mainboard.c M src/mainboard/lenovo/t60/mainboard.c M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/mainboard.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/mainboard.c M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/lenovo/x230/mainboard.c M src/mainboard/lenovo/x60/mainboard.c 25 files changed, 110 insertions(+), 278 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 2211680..542b06a 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" - # Override fuse bits that hard-code the value to 666 Mhz - register "max_mem_clock_mhz" = "933" + # Override fuse bits that hard-code the value to 666 Mhz + register "max_mem_clock_mhz" = "933" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 @@ -36,14 +36,14 @@ end device domain 0x0 on - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x17aa 0x21dd - end - device pci 01.0 on # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21dd - end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x21dd + end + device pci 01.0 on # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21dd + end chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "1" @@ -58,6 +58,10 @@ register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3b" + + register "spi_uvscc" = "0" + register "spi_lvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 subsystemid 0x17aa 0x21dd end @@ -111,27 +115,27 @@ end end chip ec/lenovo/h8 - register "config0" = "0xa7" - register "config1" = "0x09" - register "config2" = "0xa0" - register "config3" = "0xc2" + register "config0" = "0xa7" + register "config1" = "0x09" + register "config2" = "0xa0" + register "config3" = "0xc2" - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xff" - register "event5_enable" = "0xff" - register "event6_enable" = "0xff" - register "event7_enable" = "0xff" - register "event8_enable" = "0xff" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0xff" + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xff" + register "event5_enable" = "0xff" + register "event6_enable" = "0xff" + register "event7_enable" = "0xff" + register "event8_enable" = "0xff" + register "event9_enable" = "0xff" + register "eventa_enable" = "0xff" + register "eventb_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0xff" device pnp ff.2 on # dummy io 0x60 = 0x62 diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c index f733225..526a173 100644 --- a/src/mainboard/lenovo/l520/mainboard.c +++ b/src/mainboard/lenovo/l520/mainboard.c @@ -17,20 +17,13 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <ec/lenovo/h8/h8.h> - -static void mainboard_init(device_t dev) -{ - RCBA32(0x38c8) = 0x00000000; - RCBA32(0x38c4) = 0x00000000; -} static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } void h8_mainboard_init_dock(void) diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index b9b38dd..35135a9 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -56,6 +56,10 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 14.0 on # USB 3.0 Controller subsystemid 0x17aa 0x2205 end diff --git a/src/mainboard/lenovo/s230u/mainboard.c b/src/mainboard/lenovo/s230u/mainboard.c index ace72e5..a1b63cc 100644 --- a/src/mainboard/lenovo/s230u/mainboard.c +++ b/src/mainboard/lenovo/s230u/mainboard.c @@ -20,19 +20,12 @@ #include <console/console.h> #include <drivers/intel/gma/int15.h> #include <ec/acpi/ec.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <string.h> #include <smbios.h> #include "ec.h" #include <arch/acpi.h> - -static void mainboard_init(device_t dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; -} static u8 mainboard_fill_ec_version(char *buf, u8 buf_len) { @@ -74,7 +67,6 @@ static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; dev->ops->get_smbios_strings = mainboard_smbios_strings, install_intel_vga_int15_handler( diff --git a/src/mainboard/lenovo/t400/mainboard.c b/src/mainboard/lenovo/t400/mainboard.c index 7ce659f..87ed12e 100644 --- a/src/mainboard/lenovo/t400/mainboard.c +++ b/src/mainboard/lenovo/t400/mainboard.c @@ -13,30 +13,14 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <stdlib.h> -#include <arch/io.h> #include <device/device.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/keyboard.h> -#include <ec/acpi/ec.h> -#include <smbios.h> -#include <string.h> -#include <ec/lenovo/pmh7/pmh7.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include "drivers/lenovo/lenovo.h" - -static void fill_ssdt(device_t device) -{ -} static void mainboard_enable(device_t dev) { - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); - - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_CENTERING, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index a921f76..deb62b7 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -75,6 +75,10 @@ register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + # device specific SPI configuration + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c index 8e05056..f3ca67b 100644 --- a/src/mainboard/lenovo/t420/mainboard.c +++ b/src/mainboard/lenovo/t420/mainboard.c @@ -17,20 +17,10 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <ec/lenovo/h8/h8.h> - -static void mainboard_init(device_t dev) -{ - /* init spi */ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; -} static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 24f9ebd..3224322 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -75,6 +75,9 @@ register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c index 059f8e6..f3ca67b 100644 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ b/src/mainboard/lenovo/t420s/mainboard.c @@ -15,32 +15,15 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <arch/acpi.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> - -static void mainboard_init(device_t dev) -{ - /* init spi */ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; -} static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } void h8_mainboard_init_dock(void) diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 54846be..ccee86a 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -78,6 +78,9 @@ register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 14.0 on subsystemid 0x17aa 0x21fb end # USB 3.0 Controller diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c index 77f39f0..f3ca67b 100644 --- a/src/mainboard/lenovo/t430s/mainboard.c +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -15,31 +15,12 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <arch/acpi.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> - -static void mainboard_init(device_t dev) -{ - /* init spi */ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; -} static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 6c638e5..0065799 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -72,6 +72,9 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end device pci 16.2 off end diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index f9a614d..00f365b 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -15,42 +15,21 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <cbfs.h> -#include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> - -static void mainboard_init(device_t dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; -} /* mainboard_enable is executed as first thing after enumerate_buses(). */ static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } void h8_mainboard_init_dock (void) { - return; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 0731251..2047a78 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -75,6 +75,9 @@ register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x4000201" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 358dbed..0114e9b 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -15,39 +15,18 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <cbfs.h> -#include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> - -static void mainboard_init(device_t dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; -} // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } void h8_mainboard_init_dock (void) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index d8256d2..153960a 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -15,23 +15,16 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <device/device.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <delay.h> -#include <string.h> #include <device/pci_def.h> -#include <device/pci_ops.h> +#include <device/device.h> #include <ec/lenovo/pmh7/pmh7.h> -#include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> +#include <ec/acpi/ec.h> #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> -#include <arch/x86/include/arch/acpigen.h> -#include <arch/interrupt.h> -#include <smbios.h> #include <drivers/intel/gma/int15.h> +#include <arch/acpigen.h> + #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT static acpi_cstate_t cst_entries[] = { @@ -51,7 +44,9 @@ struct southbridge_intel_i82801gx_config *config; device_t idedev; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ if (acpi_is_wakeup_s3()) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index e4204dd..ce74d3f 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -77,6 +77,9 @@ register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 14.0 on subsystemid 0x17aa 0x21f9 end # USB 3.0 Controller diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c index a69ebce..a61f12c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c @@ -15,33 +15,15 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <arch/acpi.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> - -static void mainboard_init(device_t dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x38c0) = 0x00000007; -} static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index bcf5f3e..8acbb00 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -13,20 +13,9 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <stdlib.h> -#include <arch/io.h> #include <device/device.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/keyboard.h> -#include <ec/acpi/ec.h> -#include <smbios.h> -#include <string.h> -#include <ec/lenovo/pmh7/pmh7.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include "drivers/lenovo/lenovo.h" +#include <drivers/lenovo/lenovo.h> static void fill_ssdt(device_t device) { @@ -35,7 +24,9 @@ static void mainboard_enable(device_t dev) { - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_CENTERING, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); dev->ops->acpi_fill_ssdt_generator = fill_ssdt; } diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 5998a21..961d76d 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -18,30 +18,19 @@ #include <console/console.h> #include <device/device.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <delay.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> #include <northbridge/intel/nehalem/nehalem.h> #include <southbridge/intel/bd82x6x/pch.h> #include <pc80/mc146818rtc.h> #include "dock.h" -#include <arch/x86/include/arch/acpigen.h> #include <drivers/intel/gma/int15.h> -#include <arch/interrupt.h> #include <pc80/keyboard.h> #include <cpu/x86/lapic.h> #include <device/pci.h> -#include <smbios.h> -#include "drivers/lenovo/lenovo.h" +#include <drivers/lenovo/lenovo.h> +#include <arch/acpigen.h> static acpi_cstate_t cst_entries[] = { {1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}}, @@ -112,8 +101,9 @@ if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); - + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_LFP, 2); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 78a65a8..62ad3b0 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -76,6 +76,9 @@ register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index a28a5a3..0114e9b 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -15,34 +15,18 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <arch/acpi.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> - -static void mainboard_init(device_t dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; -} // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } void h8_mainboard_init_dock (void) diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a8341fc..a1b0662 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -79,6 +79,9 @@ register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 14.0 on subsystemid 0x17aa 0x21fa end # USB 3.0 Controller diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index a9b6392..0114e9b 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -15,35 +15,18 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <arch/acpi.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> - -static void mainboard_init(device_t dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; -} // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } void h8_mainboard_init_dock (void) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 6661a5f..81175ec 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -15,26 +15,17 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <device/device.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <delay.h> -#include <string.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <device/pci_ids.h> -#include <arch/interrupt.h> -#include <ec/lenovo/pmh7/pmh7.h> +#include <device/device.h> +#include <arch/io.h> #include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> #include "dock.h" -#include <arch/x86/include/arch/acpigen.h> -#include <smbios.h> #include <drivers/intel/gma/int15.h> -#include "drivers/lenovo/lenovo.h" +#include <drivers/lenovo/lenovo.h> +#include <arch/acpigen.h> #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT @@ -88,7 +79,9 @@ ec_write(0x0c, 0x88); } - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ if (acpi_is_wakeup_s3()) -- To view, visit https://review.coreboot.org/19494 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2 Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/*/romstage: Don't lock ETR3 CF9GR in early romstage
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/19570 ) Change subject: mb/*/romstage: Don't lock ETR3 CF9GR in early romstage ...................................................................... mb/*/romstage: Don't lock ETR3 CF9GR in early romstage Do not lock ETR3 CF9GR in early romstage. As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done in bd82x6x's finalize handler. Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/19570 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c 12 files changed, 11 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index bb3b223..cbc5592 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -153,7 +153,7 @@ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 4a02790..22a10ae 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -85,7 +85,7 @@ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 47b9fd6..6c93eed 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -31,7 +31,6 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index ad5f021..610eb89 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -43,7 +43,7 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000); /* Memory map KB9012 EC registers */ pci_write_config32( diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index d25ce45..766b019 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -33,7 +33,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 27b45fd..e32337a 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -36,7 +36,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 92f9e62..a17ec52 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -36,7 +36,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 5ba4873..fd17f21 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -50,8 +50,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 3d603c5..050e8cf 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -37,8 +37,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index 3e11324..574d02b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -51,8 +51,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 5a1c90a..15d2c84 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -47,8 +47,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 53ad9ac..e68843c 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -50,8 +50,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) -- To view, visit https://review.coreboot.org/19570 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/19543 ) Change subject: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR ...................................................................... sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf" Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/19543 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/bd82x6x/finalize.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 4e08fc6..9c453e4 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -65,6 +65,9 @@ /* GEN_PMCON Lock */ pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2)); + /* ETR3: CF9GR Lockdown */ + pci_update_config32(PCH_LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); + /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); pci_write_config32(PCI_DEV(0, 27, 0), 0x74, diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index da1f901..f8131da 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -144,6 +144,7 @@ #define ETR3 0xac #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20) +#define ETR3_CF9LOCK (1 << 31) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) -- To view, visit https://review.coreboot.org/19543 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenovo/*/devicetree: Add BDC detection support
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/19810 ) Change subject: mb/lenovo/*/devicetree: Add BDC detection support ...................................................................... Patch Set 1: Tested on T400/T500. Detected the installed BDC. -- To view, visit https://review.coreboot.org/19810 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenvovo/*: Clean mainboard.c and devicetree
by build bot (Jenkins) (Code Review) 21 May '17

21 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19494 ) Change subject: mb/lenvovo/*: Clean mainboard.c and devicetree ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9845/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54109/ : SUCCESS -- To view, visit https://review.coreboot.org/19494 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/*/romstage: Don't lock ETR3 CF9GR in early romstage
by Patrick Rudolph (Code Review) 21 May '17

21 May '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/19570 ) Change subject: mb/*/romstage: Don't lock ETR3 CF9GR in early romstage ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/19570/1/src/mainboard/gigabyte/ga-b75m-d3h/… File src/mainboard/gigabyte/ga-b75m-d3h/romstage.c: PS1, Line 156: 0x10000 > huh? bit16 should be set in ACPI when USB ports are routed to the I could not find any documentation about this bit. Do you have some ? -- To view, visit https://review.coreboot.org/19570 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017