coreboot-gerrit May 2017

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Change in coreboot[master]: mainboard/google/eve: Update VR config settings
by V Sowmya (Code Review) 24 May '17

24 May '17

V Sowmya has uploaded a new change for review. ( https://review.coreboot.org/19826 ) Change subject: mainboard/google/eve: Update VR config settings ...................................................................... mainboard/google/eve: Update VR config settings Update Psi2Threshold, IccMax, AcLoadline, DcLoadline VR config settings as per board design. BUG=b:38415991 BRANCH=none TEST=Build and booted eve Change-Id: I274245821f68fb3151e5563ea0c75eaa1ad32c08 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/eve/devicetree.cb 1 file changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/19826/2 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 1305f9c..02193e8 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -68,36 +68,36 @@ #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 4A | 24A | 24A | 24A | + #| IccMax | 4.1A | 24A | 24A | 24A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 17.9 | 5.9 | 5.7 | 5.7 | - #| DcLoadline | 14 | 4.7 | 4.2 | 4.2 | + #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 | + #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(4), + .icc_max = VR_CFG_AMP(4.1), .voltage_limit = 1520, - .ac_loadline = 1790, - .dc_loadline = 1400, + .ac_loadline = 1490, + .dc_loadline = 1420, }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, @@ -105,14 +105,14 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, - .ac_loadline = 590, - .dc_loadline = 470, + .ac_loadline = 500, + .dc_loadline = 486, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, @@ -127,7 +127,7 @@ register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, @@ -135,8 +135,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, - .ac_loadline = 570, - .dc_loadline = 420, + .ac_loadline = 457, + .dc_loadline = 430, }" # Enable Root port 1 with SRCCLKREQ1# -- To view, visit https://review.coreboot.org/19826 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I274245821f68fb3151e5563ea0c75eaa1ad32c08 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: CBMEM: Clarify CBMEM_TOP_BACKUP function usage
by Philippe Mathieu-Daudé (Code Review) 24 May '17

24 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19377 ) Change subject: CBMEM: Clarify CBMEM_TOP_BACKUP function usage ...................................................................... Patch Set 6: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/19377/6/src/cpu/amd/mtrr/amd_mtrr.c File src/cpu/amd/mtrr/amd_mtrr.c: PS6, Line 83: uint32_t it makes sens to me to use uintptr_t in this function now. -- To view, visit https://review.coreboot.org/19377 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/intel/sandybridge/pcie: Disable unused bridges
by Philippe Mathieu-Daudé (Code Review) 24 May '17

24 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19819 ) Change subject: nb/intel/sandybridge/pcie: Disable unused bridges ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/19819/3/src/northbridge/intel/sandybridge/p… File src/northbridge/intel/sandybridge/pcie.c: PS3, Line 50: 0x94 Can you use/add a define for this value? -- To view, visit https://review.coreboot.org/19819 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If67bafdea6a60986ecca2ecdb93c7f72359c4537 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/intel/bd82x6x: Disable unused bridges
by Philippe Mathieu-Daudé (Code Review) 24 May '17

24 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19818 ) Change subject: sb/intel/bd82x6x: Disable unused bridges ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/19818 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: device/device_util: Add function to determine bridge state
by Philippe Mathieu-Daudé (Code Review) 24 May '17

24 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19817 ) Change subject: device/device_util: Add function to determine bridge state ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/19817 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic8fe539d233031d4d177b03dd2c03edb5ab8c88d Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: enable MONITOR/MWAIT for GLK
by Cole Nelson (Code Review) 24 May '17

24 May '17

Cole Nelson has posted comments on this change. ( https://review.coreboot.org/19718 ) Change subject: soc/intel/apollolake: enable MONITOR/MWAIT for GLK ...................................................................... Patch Set 7: Please leave at -1 until we can fully confirm MWAIT is working for GLK. -- To view, visit https://review.coreboot.org/19718 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If648c25a9b26c04b278dce4af241d439790288ca Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE fur...
by Martin Roth (Code Review) 24 May '17

24 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19784 ) Change subject: rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE further back ...................................................................... rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE further back It seems that the BootROM on the RK3399 overwrites some of the earlier parts of SRAM, including the PRERAM_CBMEM_CONSOLE area. Now that we have a persistent CBMEM console we want that area to survive in case of an early (pre-CBMEM) reboot, so shuffle the layout around a bit to move it further back. (This reduces the stack size to 12KB which should still be way more than enough.) Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/19784 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/soc/rockchip/rk3399/include/soc/memlayout.ld 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index f440dfb..04ffce6 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -29,13 +29,13 @@ SYMBOL(epmu_sram, 0xFF3B2000) SRAM_START(0xFF8C0000) - PRERAM_CBMEM_CONSOLE(0xFF8C0000, 7K) + PRERAM_CBFS_CACHE(0xFF8C0000, 7K) TIMESTAMP(0xFF8C1C00, 1K) BOOTBLOCK(0xFF8C2004, 36K - 4) - PRERAM_CBFS_CACHE(0xFF8CB000, 4K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CC000, 92K) - VBOOT2_WORK(0XFF8E3000, 12K) - TTB(0xFF8E6000, 24K) - STACK(0xFF8EC000, 16K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CB000, 92K) + VBOOT2_WORK(0XFF8E2000, 12K) + TTB(0xFF8E5000, 24K) + PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) + STACK(0xFF8ED000, 12K) SRAM_END(0xFF8F0000) } -- To view, visit https://review.coreboot.org/19784 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/soraka: Update camera sensor for soraka
by Martin Roth (Code Review) 24 May '17

24 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19639 ) Change subject: mb/google/soraka: Update camera sensor for soraka ...................................................................... mb/google/soraka: Update camera sensor for soraka Soraka uses OV 13858 sensor. Hence update the same. Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/19639 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/soraka/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Rajneesh Bhardwaj: Looks good to me, but someone else must approve Sumeet R Pawnikar: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 39739e8..d7fe0e8 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -229,9 +229,9 @@ device i2c 4d on end end chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTID850"" + register "acpi_hid" = ""OVTID858"" register "acpi_name" = ""CAM0"" - register "chip_name" = ""OV 13850 Camera"" + register "chip_name" = ""OV 13858 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" # Camera SSDB buffer -- To view, visit https://review.coreboot.org/19639 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/x4x/raminit: Initialise async variable
by Martin Roth (Code Review) 24 May '17

24 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19736 ) Change subject: nb/intel/x4x/raminit: Initialise async variable ...................................................................... nb/intel/x4x/raminit: Initialise async variable It could end up not initialized which causes it not to build with clang. Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/19736 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/northbridge/intel/x4x/raminit_ddr2.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Philippe Mathieu-Daudé: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index bb5ad61..a4a830d 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -714,7 +714,7 @@ static void dll_ddr2(struct sysinfo *s) { - u8 i, j, r, reg8, clk, async; + u8 i, j, r, reg8, clk, async = 0; u16 reg16 = 0; u32 reg32 = 0; u8 lane; -- To view, visit https://review.coreboot.org/19736 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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Change in coreboot[master]: nb/intel/x4x/raminit: Initialise async variable
by Martin Roth (Code Review) 24 May '17

24 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19736 ) Change subject: nb/intel/x4x/raminit: Initialise async variable ...................................................................... Patch Set 1: Code-Review+2 I agree that the commit message could be worded better, but I don't think it's a big issue. It covers the important part which is that the variable needed to be initialized. -- To view, visit https://review.coreboot.org/19736 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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coreboot-gerrit May 2017