coreboot-gerrit April 2017

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Change in coreboot[master]: cbmem: Add new command line flag to dump console for one boo...
by Julius Werner (Code Review) 29 Apr '17

29 Apr '17

Hello Aaron Durbin, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/19497 to review the following change. Change subject: cbmem: Add new command line flag to dump console for one boot only ...................................................................... cbmem: Add new command line flag to dump console for one boot only Even though the persistent CBMEM console is obviously awesome, there may be cases where we only want to look at console output from the last boot. It's easy to tell where one boot ends and another begins from the banner message that coreboot prints at the start of every stage, but in order to make it easier to find that point (especially for external tools), let's put that functionality straight into the cbmem utility with a new command line flag. Use the POSIX/libc regular expression API to find the banner string for maximum compatilibity, even though it's kinda icky. Change-Id: Ic17383507a884d84de9a2a880380cb15b25708a1 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M util/cbmem/cbmem.c 1 file changed, 37 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/19497/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 7b7f10d..c1b1caa 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -31,6 +31,7 @@ #include <sys/mman.h> #include <libgen.h> #include <assert.h> +#include <regex.h> #include <commonlib/cbmem_id.h> #include <commonlib/timestamp_serialized.h> #include <commonlib/coreboot_tables.h> @@ -611,7 +612,7 @@ #define CBMC_OVERFLOW (1 << 31) /* dump the cbmem console */ -static void dump_console(void) +static void dump_console(int one_boot_only) { struct cbmem_console *console_p; char *console_c; @@ -659,8 +660,32 @@ for (cursor = 0; cursor < size; cursor++) if (!isprint(console_c[cursor]) && !isspace(console_c[cursor])) console_c[cursor] = '?'; - printf("%s\n", console_c); + /* We detect the last boot by looking for a bootblock, romstage or + ramstage banner, in that order (to account for platforms without + CONFIG_BOOTBLOCK_CONSOLE and/or CONFIG_EARLY_CONSOLE). Once we find + a banner, store the last match for that stage in cursor and stop. */ + cursor = 0; + if (one_boot_only) { +#define BANNER_REGEX(stage) "\n\ncoreboot-[^\n]* " stage " starting\\.\\.\\.\n" + const char *regex[] = { BANNER_REGEX("bootblock"), + BANNER_REGEX("romstage"), + BANNER_REGEX("ramstage")}; + int i; + + for (i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { + regex_t re; + regmatch_t match; + assert(!regcomp(&re, regex[i], 0)); + + /* Keep looking for matches so we find the last one. */ + while (!regexec(&re, console_c + cursor, 1, &match, 0)) + cursor += match.rm_so + 1; + regfree(&re); + } + } + + puts(console_c + cursor); free(console_c); unmap_memory(); } @@ -936,6 +961,7 @@ printf("usage: %s [-cCltTxVvh?]\n", name); printf("\n" " -c | --console: print cbmem console\n" + " -1 | --oneboot: print cbmem console for last boot only\n" " -C | --coverage: dump coverage information\n" " -l | --list: print cbmem table of contents\n" " -x | --hexdump: print hexdump of cbmem area\n" @@ -1074,11 +1100,13 @@ int print_rawdump = 0; int print_timestamps = 0; int machine_readable_timestamps = 0; + int one_boot_only = 0; unsigned int rawdump_id = 0; int opt, option_index = 0; static struct option long_options[] = { {"console", 0, 0, 'c'}, + {"oneboot", 0, 0, '1'}, {"coverage", 0, 0, 'C'}, {"list", 0, 0, 'l'}, {"timestamps", 0, 0, 't'}, @@ -1090,11 +1118,16 @@ {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "cCltTxVvh?r:", + while ((opt = getopt_long(argc, argv, "c1CltTxVvh?r:", long_options, &option_index)) != EOF) { switch (opt) { case 'c': print_console = 1; + print_defaults = 0; + break; + case '1': + print_console = 1; + one_boot_only = 1; print_defaults = 0; break; case 'C': @@ -1211,7 +1244,7 @@ #endif if (print_console) - dump_console(); + dump_console(one_boot_only); if (print_coverage) dump_coverage(); -- To view, visit https://review.coreboot.org/19497 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ic17383507a884d84de9a2a880380cb15b25708a1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: google/scarlet: Enable innolux, p079zca MIPI panel
by Julius Werner (Code Review) 28 Apr '17

28 Apr '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19476 ) Change subject: google/scarlet: Enable innolux,p079zca MIPI panel ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/19476 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id5f81867ea50f72cc0bc13074627134e0dc198ba Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: nickey.yang(a)rock-chips.com Gerrit-HasComments: No

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Change in coreboot[master]: rockchip/rk3399: Add MIPI driver
by Julius Werner (Code Review) 28 Apr '17

28 Apr '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19477 ) Change subject: rockchip/rk3399: Add MIPI driver ...................................................................... Patch Set 2: (6 comments) https://review.coreboot.org/#/c/19477/2/src/soc/rockchip/rk3399/display.c File src/soc/rockchip/rk3399/display.c: Line 116: rkclk_configure_vop_aclk(vop_id, 200 * MHz); > I am not sure,because i see it will be 384Mhz when hdmi output. Okay, fair enough, then leave it here. https://review.coreboot.org/#/c/19477/3/src/soc/rockchip/rk3399/display.c File src/soc/rockchip/rk3399/display.c: PS3, Line 63: : > If you're going to remove this (and HDMI down below), you should delete the The header is shared with RK3288 code which still needs them, so please don't. ;) https://review.coreboot.org/#/c/19477/2/src/soc/rockchip/rk3399/mipi.c File src/soc/rockchip/rk3399/mipi.c: Line 68: return dptdin_map[i].testdin; > refer to 《MIPI D-PHY Bidir 4L for TSMC 28-nm HPC /1.8V Databook》 Okay, fair enough. But shouldn't the comparison be (dptdin_map[i].max_mbps >= max_mbps) (not '>' ), then? Line 192: mpclk = DIV_ROUND_UP(edid->mode.pixel_clock, MSEC_PER_SEC); > because i think porting from kernel code, and then we can refer to kernel p That is not a good reason to have bad code, though. You're doing a lot of integer divisions on these numbers and you're loosing a lot of precision all over the place. I didn't review the kernel change so I can't comment on that, but here I can see that it is likely not ideal and I want you to change it. Please change these variables to hold Hz or at least KHz. Line 193: /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ > refer to kernel code Hmm. It would be nice if we could get a better explanation for *why* the margin is not enough if calculations show it should be. (Maybe because you're calculating in MHz everywhere and getting giant rounding errors?) https://review.coreboot.org/#/c/19477/3/src/soc/rockchip/rk3399/mipi.c File src/soc/rockchip/rk3399/mipi.c: PS3, Line 194: si->lanes) * 10 / This is also a bad integer division in the 18bpp case, btw. You should probably write it mpclk / dsi->lanes * bpp / 8 * 10; (Assuming you'll change mpclk to Hz so doing the division first isn't as bad.) -- To view, visit https://review.coreboot.org/19477 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sean Paul <seanpaul(a)chromium.org> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: nickey.yang(a)rock-chips.com Gerrit-HasComments: Yes

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Change in coreboot[master]: cbgfx: Add portrait screen support
by Julius Werner (Code Review) 28 Apr '17

28 Apr '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19474 ) Change subject: cbgfx: Add portrait screen support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/19474 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I66fee6d73654e736a2db4a3d191f030c52a23e0d Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: nickey.yang(a)rock-chips.com Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel/pineview: Include speedstep
by build bot (Jenkins) (Code Review) 28 Apr '17

28 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19496 ) Change subject: cpu/intel/pineview: Include speedstep ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/52964/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8810/ : SUCCESS -- To view, visit https://review.coreboot.org/19496 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel/pineview: Include speedstep
by Arthur Heymans (Code Review) 28 Apr '17

28 Apr '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19496 ) Change subject: cpu/intel/pineview: Include speedstep ...................................................................... cpu/intel/pineview: Include speedstep Needed to generate cpu entries. Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/northbridge/intel/pineview/northbridge.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19496/1 diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 082c472..dbf300b 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -6,6 +6,7 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index b7fd8a1..ea55974 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -153,6 +153,7 @@ .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; static void cpu_bus_init(device_t dev) -- To view, visit https://review.coreboot.org/19496 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mainboard/google/soraka: Add support for memory configs 1, 2, ...
by Furquan Shaikh (Code Review) 28 Apr '17

28 Apr '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19472 ) Change subject: mainboard/google/soraka: Add support for memory configs 1,2,7 and 8 ...................................................................... mainboard/google/soraka: Add support for memory configs 1,2,7 and 8 BUG=b:37712455 Change-Id: I3209aaef774712edab5e9f656ee84bfb6917b1c1 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/19472 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) --- A src/mainboard/google/poppy/spd/samsung_dimm_K3QF3F30BM-AGCF.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K3QF4F40BM-AGCF.spd.hex M src/mainboard/google/poppy/variants/soraka/Makefile.inc 3 files changed, 37 insertions(+), 2 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K3QF3F30BM-AGCF.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K3QF3F30BM-AGCF.spd.hex new file mode 100644 index 0000000..f50a92d --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K3QF3F30BM-AGCF.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 33 51 46 33 46 33 30 42 4D 2D 41 47 43 46 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K3QF4F40BM-AGCF.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K3QF4F40BM-AGCF.spd.hex new file mode 100644 index 0000000..6c0a04d --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K3QF4F40BM-AGCF.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 33 51 46 34 46 34 30 42 4D 2D 41 47 43 46 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/soraka/Makefile.inc b/src/mainboard/google/poppy/variants/soraka/Makefile.inc index 41e40f7..d757c56 100644 --- a/src/mainboard/google/poppy/variants/soraka/Makefile.inc +++ b/src/mainboard/google/poppy/variants/soraka/Makefile.inc @@ -1,8 +1,11 @@ SPD_SOURCES = empty # 0b0000 -SPD_SOURCES += empty # 0b0001 -SPD_SOURCES += empty # 0b0010 +SPD_SOURCES += micron_dimm_MT52L256M64D2PP-107 # 0b0001 +SPD_SOURCES += hynix_dimm_H9CCNNNBKTALBR-NUD # 0b0010 SPD_SOURCES += micron_dimm_MT52L512M64D4PQ-107 # 0b0011 SPD_SOURCES += hynix_dimm_H9CCNNNCPTALBR-NUD # 0b0100 SPD_SOURCES += micron_dimm_MT52L1G64D8QC-107 # 0b0101 SPD_SOURCES += hynix_dimm_H9CCNNNFAGMLLR-NUD # 0b0110 +SPD_SOURCES += samsung_dimm_K3QF3F30BM-AGCF # 0b0111 +SPD_SOURCES += samsung_dimm_K3QF4F40BM-AGCF # 0b1000 +SPD_SOURCEs += empty # 0b1001 -- To view, visit https://review.coreboot.org/19472 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I3209aaef774712edab5e9f656ee84bfb6917b1c1 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: mainboard/google/poppy: Add SPDs for memory config 1 and 2
by Furquan Shaikh (Code Review) 28 Apr '17

28 Apr '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19471 ) Change subject: mainboard/google/poppy: Add SPDs for memory config 1 and 2 ...................................................................... mainboard/google/poppy: Add SPDs for memory config 1 and 2 BUG=b:37712790 Change-Id: I7764b4ec55b0beea82eeb6c379ef38ceeb1fb04e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/19471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L256M64D2PP-107.spd.hex M src/mainboard/google/poppy/variants/poppy/Makefile.inc 3 files changed, 34 insertions(+), 2 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.hex new file mode 100644 index 0000000..95716be --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 50 54 41 4C 42 52 2D 4E +54 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L256M64D2PP-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L256M64D2PP-107.spd.hex new file mode 100644 index 0000000..aa1b01e --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L256M64D2PP-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 21 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 E6 7D +4D 54 35 32 4C 32 35 36 4D 36 34 44 32 50 50 2D +31 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/poppy/Makefile.inc b/src/mainboard/google/poppy/variants/poppy/Makefile.inc index 41e40f7..ecd1451 100644 --- a/src/mainboard/google/poppy/variants/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/variants/poppy/Makefile.inc @@ -1,7 +1,7 @@ SPD_SOURCES = empty # 0b0000 -SPD_SOURCES += empty # 0b0001 -SPD_SOURCES += empty # 0b0010 +SPD_SOURCES += micron_dimm_MT52L256M64D2PP-107 # 0b0001 +SPD_SOURCES += hynix_dimm_H9CCNNNBKTALBR-NUD # 0b0010 SPD_SOURCES += micron_dimm_MT52L512M64D4PQ-107 # 0b0011 SPD_SOURCES += hynix_dimm_H9CCNNNCPTALBR-NUD # 0b0100 SPD_SOURCES += micron_dimm_MT52L1G64D8QC-107 # 0b0101 -- To view, visit https://review.coreboot.org/19471 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I7764b4ec55b0beea82eeb6c379ef38ceeb1fb04e Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: mainboard/google/poppy: Enable separate MRC cache for recove...
by Furquan Shaikh (Code Review) 28 Apr '17

28 Apr '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19457 ) Change subject: mainboard/google/poppy: Enable separate MRC cache for recovery mode ...................................................................... mainboard/google/poppy: Enable separate MRC cache for recovery mode Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:37682566 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: I4c748a316436001c5a33754084ab4a74243e21df Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/19457 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/chromeos.fmd 2 files changed, 20 insertions(+), 13 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index fa0c6b6..ce32081 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -72,6 +72,8 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH config DRIVER_TPM_SPI_BUS diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd index 58b6127..bdadcf7 100644 --- a/src/mainboard/google/poppy/chromeos.fmd +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -4,24 +4,29 @@ SI_ME@0x1000 0x1ff000 } SI_BIOS@0x200000 0xe00000 { - RW_SECTION_A@0x0 0x3f0000 { + RW_SECTION_A@0x0 0x3e8000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x3d7fc0 + RW_FWID_A@0x3e7fc0 0x40 } - RW_SECTION_B@0x3f0000 0x3f0000 { + RW_SECTION_B@0x3e8000 0x3e8000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x3d7fc0 + RW_FWID_B@0x3e7fc0 0x40 } - RW_MRC_CACHE@0x7e0000 0x10000 - RW_ELOG@0x7f0000 0x4000 - RW_SHARED@0x7f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_MISC@0x7d0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 } - RW_VPD@0x7f8000 0x2000 - RW_NVRAM@0x7fa000 0x6000 RW_LEGACY(CBFS)@0x800000 0x200000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000 -- To view, visit https://review.coreboot.org/19457 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I4c748a316436001c5a33754084ab4a74243e21df Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/skylake: Use common I2C code from intelblocks
by build bot (Jenkins) (Code Review) 28 Apr '17

28 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19469 ) Change subject: soc/intel/skylake: Use common I2C code from intelblocks ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/52961/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/8808/ : SUCCESS -- To view, visit https://review.coreboot.org/19469 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iae7d13303090c72380534618741858502cc9ee33 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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coreboot-gerrit April 2017