Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18340
-gerrit
commit 1be8bad03a87125df3a67e5cbc454cd5935ca8ce
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Sat Feb 11 10:57:23 2017 -0800
device: Add a new "SPI" device type
Add support for a new "SPI" device type in the devicetree to bind a
device on the SPI bus. Allow device to provide chip select number for
the device as a parameter.
Add spi_bus_operations with operation dev_to_bus which allows SoCs to
define a translation method for converting "struct device" into a unique
SPI bus number.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
src/device/device_util.c | 10 ++++++++++
src/include/device/device.h | 2 ++
src/include/device/path.h | 10 +++++++++-
src/include/device/spi.h | 30 ++++++++++++++++++++++++++++++
4 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/src/device/device_util.c b/src/device/device_util.c
index 1a0a60f..e31ade5 100644
--- a/src/device/device_util.c
+++ b/src/device/device_util.c
@@ -250,6 +250,9 @@ u32 dev_path_encode(device_t dev)
case DEVICE_PATH_GENERIC:
ret |= dev->path.generic.subid << 8 | dev->path.generic.id;
break;
+ case DEVICE_PATH_SPI:
+ ret |= dev->path.spi.cs;
+ break;
case DEVICE_PATH_NONE:
default:
break;
@@ -319,6 +322,10 @@ const char *dev_path(device_t dev)
"GENERIC: %d.%d", dev->path.generic.id,
dev->path.generic.subid);
break;
+ case DEVICE_PATH_SPI:
+ snprintf(buffer, sizeof (buffer), "SPI: %02x",
+ dev->path.spi.cs);
+ break;
default:
printk(BIOS_ERR, "Unknown device path type: %d\n",
dev->path.type);
@@ -390,6 +397,9 @@ int path_eq(struct device_path *path1, struct device_path *path2)
equal = (path1->generic.id == path2->generic.id) &&
(path1->generic.subid == path2->generic.subid);
break;
+ case DEVICE_PATH_SPI:
+ equal = (path1->spi.cs == path2->spi.cs);
+ break;
default:
printk(BIOS_ERR, "Unknown device type: %d\n", path1->type);
break;
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 47509f7..e21384b 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -23,6 +23,7 @@ struct pci_bus_operations;
struct i2c_bus_operations;
struct smbus_bus_operations;
struct pnp_mode_ops;
+struct spi_bus_operations;
/* Chip operations */
struct chip_operations {
@@ -64,6 +65,7 @@ struct device_operations {
#endif
const struct pci_operations *ops_pci;
const struct i2c_bus_operations *ops_i2c_bus;
+ const struct spi_bus_operations *ops_spi_bus;
const struct smbus_bus_operations *ops_smbus_bus;
const struct pci_bus_operations * (*ops_pci_bus)(device_t dev);
const struct pnp_mode_ops *ops_pnp_mode;
diff --git a/src/include/device/path.h b/src/include/device/path.h
index 9d7fb38..849b579 100644
--- a/src/include/device/path.h
+++ b/src/include/device/path.h
@@ -14,6 +14,7 @@ enum device_path_type {
DEVICE_PATH_CPU_BUS,
DEVICE_PATH_IOAPIC,
DEVICE_PATH_GENERIC,
+ DEVICE_PATH_SPI,
/*
* When adding path types to this table, please also update the
@@ -33,7 +34,8 @@ enum device_path_type {
"DEVICE_PATH_CPU", \
"DEVICE_PATH_CPU_BUS", \
"DEVICE_PATH_IOAPIC", \
- "DEVICE_PATH_GENERIC" \
+ "DEVICE_PATH_GENERIC", \
+ "DEVICE_PATH_SPI", \
}
struct domain_path
@@ -58,6 +60,11 @@ struct i2c_path
unsigned mode_10bit;
};
+struct spi_path
+{
+ unsigned cs;
+};
+
struct apic_path
{
unsigned apic_id;
@@ -107,6 +114,7 @@ struct device_path {
struct cpu_path cpu;
struct cpu_bus_path cpu_bus;
struct generic_path generic;
+ struct spi_path spi;
};
};
diff --git a/src/include/device/spi.h b/src/include/device/spi.h
new file mode 100644
index 0000000..4315ebc
--- /dev/null
+++ b/src/include/device/spi.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DEVICE_SPI_H__
+#define __DEVICE_SPI_H__
+
+struct device;
+struct spi_bus_operations {
+ /*
+ * This is a SoC-specific method that can be provided to translate the
+ * 'struct device' for a SPI controller into a unique SPI bus
+ * number. Returns -1 if the bus number for this bus cannot be
+ * determined.
+ */
+ int (*dev_to_bus)(struct device *dev);
+};
+
+#endif /* __DEVICE_SPI_H__ */
Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18336
-gerrit
commit 398c079057eb746657c871dcb01c34d79651369f
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Sat Feb 11 22:47:04 2017 +0100
libpayload: x86/head - implement argc/argv handling
Implement the argc/argv passing as described in coreboot’s payload API:
http://www.coreboot.org/Payload_API
While at it, give the code some love by not needlessly trashing register
values.
Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
---
payloads/libpayload/arch/x86/head.S | 41 +++++++++++++++++++++----------------
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/payloads/libpayload/arch/x86/head.S b/payloads/libpayload/arch/x86/head.S
index fa9bb73..94a4d41 100644
--- a/payloads/libpayload/arch/x86/head.S
+++ b/payloads/libpayload/arch/x86/head.S
@@ -28,7 +28,7 @@
*/
.code32
- .global _entry, _leave
+ .global _entry
.text
.align 4
@@ -55,6 +55,11 @@ mb_header:
.long _end
.long _init
+#define CB_MAGIC_VALUE 0x12345678
+#define CB_MAGIC 0x04
+#define CB_ARGV 0x08
+#define CB_ARGC 0x10
+
/*
* This function saves off the previous stack and switches us to our
* own execution environment.
@@ -63,34 +68,34 @@ _init:
/* No interrupts, please. */
cli
- /* There is a bunch of stuff missing here to take arguments on the stack
- * See http://www.coreboot.org/Payload_API and exec.S.
- */
- /* Store current stack pointer. */
- movl %esp, %esi
-
/* Store EAX and EBX */
- movl %eax,loader_eax
- movl %ebx,loader_ebx
+ movl %eax, loader_eax
+ movl %ebx, loader_ebx
- /* Setup new stack. */
- movl $_stack, %ebx
+ /* Copy argv[] and argc as demanded by the Payload API,
+ * see http://www.coreboot.org/Payload_API and exec.S.
+ */
+ cmpl $CB_MAGIC_VALUE, CB_MAGIC(%esp)
+ jne 1f
- movl %ebx, %esp
+ movl CB_ARGV(%esp), %eax
+ movl %eax, main_argv
- /* Save old stack pointer. */
- pushl %esi
+ movl CB_ARGC(%esp), %eax
+ movl %eax, main_argc
+1:
+ /* Store current stack pointer and set up new stack. */
+ movl %esp, %eax
+ movl $_stack, %esp
+ pushl %eax
/* Let's rock. */
call start_main
/* %eax has the return value - pass it on unmolested */
_leave:
- /* Get old stack pointer. */
- popl %ebx
-
/* Restore old stack. */
- movl %ebx, %esp
+ popl %esp
/* Return to the original context. */
ret
Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18335
-gerrit
commit b8df53bcbdaf7200a2a93caf042578b0f3fbfa49
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Sat Feb 11 21:02:08 2017 +0100
libpayload: x86/exec - simplify and robustify the code
Simplify the code by directly using the arguments on the stack as base
pointer relative memory references, instead of loading them into
intermediate registers first.
Make it more robust by preserving all callee saved registers mandated by
the C calling convention (and only those), namely EBP, EBX, ESI and EDI.
Don't assume anything about the register state when the called function
returns -- beside the segment registers and the stack pointer to be
still the same as before the call.
Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
---
payloads/libpayload/arch/x86/exec.S | 59 +++++++++++++------------------------
1 file changed, 20 insertions(+), 39 deletions(-)
diff --git a/payloads/libpayload/arch/x86/exec.S b/payloads/libpayload/arch/x86/exec.S
index 54c83f6..f5cb0e3 100644
--- a/payloads/libpayload/arch/x86/exec.S
+++ b/payloads/libpayload/arch/x86/exec.S
@@ -37,67 +37,48 @@
.text
.global i386_do_exec
- .type i386_do_exec,@function
+ .type i386_do_exec,@function
i386_do_exec:
pushl %ebp
movl %esp, %ebp
- pushl %eax
-
- /* Put the run address in %eax */
- movl 8(%ebp), %eax
-
- /* Save off the rest of the registers */
+ /* Save the remaining callee preserved registers */
+ pushl %ebx
pushl %esi
- pushl %ecx
- pushl %ebp
+ pushl %edi
/* Push argc and argv on to the stack.
*
* We need to put a dummy value inbetween, as argc should be at offset
* 0x10, according to the payload API.
*/
-
- movl 12(%ebp), %esi
- movl 16(%ebp), %ecx
-
- pushl %esi
+ pushl 12(%ebp)
pushl $0
- pushl %ecx
+ pushl 16(%ebp)
- /* Move a "magic" number on the stack - the other
- * payload will use this as a clue that the argc
- * and argv are sane
+ /* Push a "magic" number on the stack - the other payload will use this
+ * as a clue that the argc and argv values on the stack are sane.
*/
-
- movl $0x12345678, %ecx
- pushl %ecx
+ pushl $0x12345678
/* Jump to the code */
- call *%eax
-
+ call *8(%ebp)
/* %eax has the return value */
- /* Skip over the argc/argv stuff still on the stack */
- addl $12, %esp
+ /* Skip over the argc/argv stuff still on the stack.
+ * Don't assume %ebp is sane, here. Restore it from the stack.
+ */
+ addl $0x10, %esp
- /* Get back %ebp */
+ /* Restore the saved registers */
+ popl %edi
+ popl %esi
+ popl %ebx
popl %ebp
- /* Get the pointer to the return value
- * and save the return value in it
- */
-
- movl 20(%ebp), %ecx
+ /* Get pointer to return value and save the return value in it. */
+ movl 16(%esp), %ecx
movl %eax, (%ecx)
- /* Get the rest of the saved registers */
- popl %ecx
- popl %esi
- popl %eax
-
- /* Restore the stack pointer */
- movl %ebp,%esp
- popl %ebp
ret
Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18334
-gerrit
commit 91a8f07cdcbe745d22e94728ae48e565b2ab8d7c
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Tue Feb 7 19:03:29 2017 +0100
libpayload: x86/main - propagate return value of main()
According to coreboot’s payload API [1], the called payload should be
able to return a value via %eax. Support this by changing the prototype
of start_main() and pass on the return value of main() to the caller
instead of discarding it.
[1] https://www.coreboot.org/Payload_API
Change-Id: I8442faea19cc8e04487092f8e61aa4e5cba3ba76
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
---
payloads/libpayload/arch/x86/main.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c
index fbd4dc4..f9a5e2c 100644
--- a/payloads/libpayload/arch/x86/main.c
+++ b/payloads/libpayload/arch/x86/main.c
@@ -42,8 +42,8 @@ char *main_argv[MAX_ARGC_COUNT];
* This is our C entry function - set up the system
* and jump into the payload entry point.
*/
-void start_main(void);
-void start_main(void)
+int start_main(void);
+int start_main(void)
{
extern int main(int argc, char **argv);
@@ -67,10 +67,9 @@ void start_main(void)
* In the future we may care about the return value.
*/
- (void) main(main_argc, (main_argc != 0) ? main_argv : NULL);
-
/*
- * Returning here will go to the _leave function to return
+ * Returning from main() will go to the _leave function to return
* us to the original context.
*/
+ return main(main_argc, (main_argc != 0) ? main_argv : NULL);
}
Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18333
-gerrit
commit 1792649db5603436a135e3d04480043645d366df
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Sat Feb 11 22:34:46 2017 +0100
libpayload: x86/exec - fix argc/argv value passing
According to coreboot’s payload API [1] the argc value should be passed
at stack offset 0x10, so we need to push a dummy value to comply to the
API.
[1] https://www.coreboot.org/Payload_API
Change-Id: Id20424185a5bf7e4d94de1886a2cece3f3968371
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
---
payloads/libpayload/arch/x86/exec.S | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/payloads/libpayload/arch/x86/exec.S b/payloads/libpayload/arch/x86/exec.S
index 7d89cc0..54c83f6 100644
--- a/payloads/libpayload/arch/x86/exec.S
+++ b/payloads/libpayload/arch/x86/exec.S
@@ -53,12 +53,17 @@ i386_do_exec:
pushl %ecx
pushl %ebp
- /* Push the argc and argv pointers on to the stack */
+ /* Push argc and argv on to the stack.
+ *
+ * We need to put a dummy value inbetween, as argc should be at offset
+ * 0x10, according to the payload API.
+ */
movl 12(%ebp), %esi
movl 16(%ebp), %ecx
pushl %esi
+ pushl $0
pushl %ecx
/* Move a "magic" number on the stack - the other
Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18332
-gerrit
commit e81a2fd36f9a45797879996ce2ecbdd734b2cf18
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Tue Feb 7 19:47:16 2017 +0100
libpayload: x86/exec - fix return value passing
The pointer to write the return value to is in %ecx, not %eax. Writing
to (%eax) leads to memory corruptions as %eax holds the return value,
e.g. would write zero to address zero for a "successful" returning
payload.
Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
---
payloads/libpayload/arch/x86/exec.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/payloads/libpayload/arch/x86/exec.S b/payloads/libpayload/arch/x86/exec.S
index c7595e9..7d89cc0 100644
--- a/payloads/libpayload/arch/x86/exec.S
+++ b/payloads/libpayload/arch/x86/exec.S
@@ -85,7 +85,7 @@ i386_do_exec:
*/
movl 20(%ebp), %ecx
- movl %eax, (%eax)
+ movl %eax, (%ecx)
/* Get the rest of the saved registers */
popl %ecx
Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18331
-gerrit
commit beabce4f71291e99e02b06f8d449d0624a363897
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Tue Feb 7 18:59:27 2017 +0100
libpayload: x86/exec - fix libpayload API magic value
According to coreboot’s payload API [1] the magic value passed to the
payload should be 0x12345678, not 12345678. Fix that.
[1] https://www.coreboot.org/Payload_API
Change-Id: I10a7f7b1a4aec100416c5e7e4ba7f8add10ef5c5
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
---
payloads/libpayload/arch/x86/exec.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/payloads/libpayload/arch/x86/exec.S b/payloads/libpayload/arch/x86/exec.S
index b632a55..c7595e9 100644
--- a/payloads/libpayload/arch/x86/exec.S
+++ b/payloads/libpayload/arch/x86/exec.S
@@ -66,7 +66,7 @@ i386_do_exec:
* and argv are sane
*/
- movl $12345678, %ecx
+ movl $0x12345678, %ecx
pushl %ecx
/* Jump to the code */
Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18362
-gerrit
commit 590c1c9e962b0f8babcd4e1d6ba74c8ecdbb1f30
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Mon Feb 13 13:44:14 2017 -0800
arch/x86: add library function for coreboot to generate random number
using x86 RDRAND instruction.
Two functions are supplied to generate 32bit or 64bit number.
One potential usage is the sealing key generation for SGX.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve to generate a 64bit random number.
Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
---
src/arch/x86/Makefile.inc | 1 +
src/arch/x86/include/arch/rdrand.h | 27 ++++++++++++
src/arch/x86/rdrand.c | 84 ++++++++++++++++++++++++++++++++++++++
3 files changed, 112 insertions(+)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index c4bb1cc..332e8ec 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -334,6 +334,7 @@ ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
ramstage-y += pci_ops_conf1.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
+ramstage-y += rdrand.c
ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
ramstage-y += tables.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
diff --git a/src/arch/x86/include/arch/rdrand.h b/src/arch/x86/include/arch/rdrand.h
new file mode 100644
index 0000000..74166d9
--- /dev/null
+++ b/src/arch/x86/include/arch/rdrand.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef ARCH_RDRAND_H
+#define ARCH_RDRAND_H
+
+#include <stdint.h>
+
+/*
+ * Generates a 32/64 bit random number respectively.
+ * return 0 on success and -1 on error.
+ */
+int get_random_number_32(uint32_t *rand);
+int get_random_number_64(uint64_t *rand);
+
+#endif /* ARCH_RDRAND_H */
diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c
new file mode 100644
index 0000000..51bf1e1
--- /dev/null
+++ b/src/arch/x86/rdrand.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/rdrand.h>
+
+#define RDRAND_RETRY_LOOPS 10
+
+/*
+ * Generates a 32-bit random number through RDRAND instruction.
+ */
+static inline uint8_t rdrand_32(uint32_t *rand)
+{
+ uint8_t carry;
+
+ __asm__ __volatile__(
+ ".byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1"
+ : "=a" (*rand), "=qm" (carry));
+ return carry;
+}
+
+#ifdef __x86_64__
+/*
+ * Generates a 64-bit random number through RDRAND instruction.
+ */
+static inline uint8_t rdrand_64(uint64_t *rand)
+{
+ uint8_t carry;
+
+ __asm__ __volatile__(
+ ".byte 0x48; .byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1"
+ : "=a" (*rand), "=qm" (carry));
+ return carry;
+}
+#endif
+
+int get_random_number_32(uint32_t *rand)
+{
+ int i;
+
+ /*
+ * Perform a loop call until RDRAND succeeds or returns failure
+ */
+ for (i = 0; i < RDRAND_RETRY_LOOPS; i++) {
+ if (rdrand_32(rand))
+ return 0;
+ }
+ return -1;
+}
+
+int get_random_number_64(uint64_t *rand)
+{
+ int i;
+#ifndef __x86_64__
+ uint32_t rand_high, rand_low;
+#endif
+
+ /*
+ * Perform a loop call until RDRAND succeeds or returns failure
+ */
+ for (i = 0; i < RDRAND_RETRY_LOOPS; i++) {
+#ifdef __x86_64__
+ if (rdrand_64(rand))
+ return 0;
+#else
+ if (rdrand_32(&rand_high) && rdrand_32(&rand_low)) {
+ *rand = ((uint64_t)rand_high << 32) | (uint64_t)rand_low;
+ return 0;
+ }
+#endif
+ }
+ return -1;
+}
Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18353
-gerrit
commit 8b5decaa195a87fad4c329b70ee073b1e854fec1
Author: Tobias Diedrich <ranma+openocd(a)tdiedrich.de>
Date: Sun Feb 12 22:58:37 2017 +0100
southbridge/intel/bd82x6x: Use correct EHCI address for USBDEBUG
The bd82x6x hardcoded EHCI bar adresses (0xe8000[04]00) don't match the
CONFIG_EHCI_BAR default of 0xfef00000.
This copies the defines from southbridge/intel/lynxpoint/early_usb.c
so that the early EHCI bar setup is using CONFIG_EHCI_BAR and
CONFIG_USBDEBUG_HCD_INDEX to determine the correct bar addresses.
Change-Id: I6ee6089c9e5f3bc5f457eae47c18c2473fa42571
Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
---
src/southbridge/intel/bd82x6x/early_usb_mrc.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
index 8fac3c7..01d7692 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
@@ -20,8 +20,17 @@
#include <device/pci_def.h>
#include "pch.h"
-#define PCH_EHCI1_TEMP_BAR0 0xe8000000
-#define PCH_EHCI2_TEMP_BAR0 0xe8000400
+/*
+ * HCD_INDEX==2 selects 0:1a.0 (PCH_EHCI2), any other index
+ * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
+ */
+#if CONFIG_USBDEBUG_HCD_INDEX != 2
+#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
+#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
+#else
+#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
+#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
+#endif
/*
* Setup USB controller MMIO BAR to prevent the