coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: drivers/i2c/tps68470: Add TPS68470 PMIC SSDT generator
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18063 -gerrit commit 062321ee5d2e495d30b15f6cfd82f5dc29b34d34 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Mon Jan 9 19:00:06 2017 +0530 drivers/i2c/tps68470: Add TPS68470 PMIC SSDT generator Add TPS68470 PMIC SSDT generator. Change-Id: Iaa1dba094a7f791d5b624e545b03b510a4306337 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/drivers/i2c/tps68470/Kconfig | 2 + src/drivers/i2c/tps68470/Makefile.inc | 1 + src/drivers/i2c/tps68470/chip.h | 26 ++++++++++ src/drivers/i2c/tps68470/tps68470.c | 94 +++++++++++++++++++++++++++++++++++ 4 files changed, 123 insertions(+) diff --git a/src/drivers/i2c/tps68470/Kconfig b/src/drivers/i2c/tps68470/Kconfig new file mode 100644 index 0000000..75d81dc --- /dev/null +++ b/src/drivers/i2c/tps68470/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_TPS68470 + bool diff --git a/src/drivers/i2c/tps68470/Makefile.inc b/src/drivers/i2c/tps68470/Makefile.inc new file mode 100644 index 0000000..3fa4412 --- /dev/null +++ b/src/drivers/i2c/tps68470/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_TPS68470) += tps68470.c diff --git a/src/drivers/i2c/tps68470/chip.h b/src/drivers/i2c/tps68470/chip.h new file mode 100644 index 0000000..d82d9bd --- /dev/null +++ b/src/drivers/i2c/tps68470/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> + +#define TPS68470_MAX_CLDB_BUF 32 + +struct drivers_i2c_tps68470_config { + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned bus_speed; + + uint8_t cldb_buf[TPS68470_MAX_CLDB_BUF]; +}; diff --git a/src/drivers/i2c/tps68470/tps68470.c b/src/drivers/i2c/tps68470/tps68470.c new file mode 100644 index 0000000..f7c2ce1 --- /dev/null +++ b/src/drivers/i2c/tps68470/tps68470.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define TPS68470_ACPI_NAME "PMIC" + +static void tps68470_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_tps68470_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", "INT3472"); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + acpigen_write_method_serialized("CLDB",0); + acpigen_write_return_byte_buffer(config->cldb_buf, + TPS68470_MAX_CLDB_BUF); + + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + +} + +static const char *tps68470_acpi_name(struct device *dev) +{ + return TPS68470_ACPI_NAME; +} +#endif + +static struct device_operations tps68470_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &tps68470_acpi_name, + .acpi_fill_ssdt_generator = &tps68470_fill_ssdt, +#endif +}; + +static void tps68470_enable(struct device *dev) +{ + dev->ops = &tps68470_ops; +} + +struct chip_operations drivers_i2c_tps68470_ops = { + CHIP_NAME("TPS 68470 PMIC") + .enable_dev = &tps68470_enable +};

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Patch set updated for coreboot: drivers/i2c/ov_camera: Add generic i2c driver for OV cameras
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18066 -gerrit commit fd9bb00a8015891814c79c0f637344ef85c8d710 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Mon Jan 9 22:58:04 2017 +0530 drivers/i2c/ov_camera: Add generic i2c driver for OV cameras Add generic i2c driver for OV cameras Change-Id: I64afc42b898c866f81ed00bbca99e191f7d48c5a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/drivers/i2c/ov_camera/Kconfig | 2 + src/drivers/i2c/ov_camera/Makefile.inc | 1 + src/drivers/i2c/ov_camera/chip.h | 70 +++++++++++++++++++++ src/drivers/i2c/ov_camera/ov_camera.c | 112 +++++++++++++++++++++++++++++++++ 4 files changed, 185 insertions(+) diff --git a/src/drivers/i2c/ov_camera/Kconfig b/src/drivers/i2c/ov_camera/Kconfig new file mode 100644 index 0000000..0d90e98 --- /dev/null +++ b/src/drivers/i2c/ov_camera/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_OV_CAMERA + bool diff --git a/src/drivers/i2c/ov_camera/Makefile.inc b/src/drivers/i2c/ov_camera/Makefile.inc new file mode 100644 index 0000000..13e3c48 --- /dev/null +++ b/src/drivers/i2c/ov_camera/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_OV_CAMERA) += ov_camera.c diff --git a/src/drivers/i2c/ov_camera/chip.h b/src/drivers/i2c/ov_camera/chip.h new file mode 100644 index 0000000..7c1bc9d --- /dev/null +++ b/src/drivers/i2c/ov_camera/chip.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> + +#define MAX_SSDB_BUF 94 + +typedef union { + uint8_t ssdb_arr[MAX_SSDB_BUF]; + struct { + uint8_t version; + uint8_t sensor_card_sku; + uint8_t csi2_data_stream_interface[16]; + uint16_t bdf_value; + uint32_t dphy_link_en_fuses; + uint32_t lanes_clock_division; + uint8_t link_used; + uint8_t lanes_used; + uint32_t csi_rx_dly_cnt_termen_clane; + uint32_t csi_rx_dly_cnt_settle_clane; + uint32_t csi_rx_dly_cnt_termen_dlane0; + uint32_t csi_rx_dly_cnt_settle_dlane0; + uint32_t csi_rx_dly_cnt_termen_dlane1; + uint32_t csi_rx_dly_cnt_settle_dlane1; + uint32_t csi_rx_dly_cnt_termen_dlane2; + uint32_t csi_rx_dly_cnt_settle_dlane2; + uint32_t csi_rx_dly_cnt_termen_dlane3; + uint32_t csi_rx_dly_cnt_settle_dlane3; + uint32_t max_lane_speed; + uint8_t sensor_calibration_file_index; + uint8_t sensor_calibration_file_index_mbz[3]; + uint8_t rom_type; + uint8_t vcm_type; + uint8_t platform; + uint8_t platform_sub; + uint8_t flash_support; + uint8_t privacy_led; + uint8_t degree; /* Camera module rotation */ + uint8_t mipi_define; + uint32_t mclk; + uint8_t control_logic_id; + uint8_t mipi_data_format; + uint8_t silicon_version; + uint8_t customer_id; + }ssdb; +}__attribute__((packed))ov_camera_ssdb; + +struct drivers_i2c_ov_camera_config { + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned bus_speed; + ov_camera_ssdb buf; + uint8_t vcm_addr; + uint8_t eeprom0_addr; + const char acpi_hid[8]; + const char acpi_name[5]; + uint64_t acpi_uid; +}; diff --git a/src/drivers/i2c/ov_camera/ov_camera.c b/src/drivers/i2c/ov_camera/ov_camera.c new file mode 100644 index 0000000..02bcda6 --- /dev/null +++ b/src/drivers/i2c/ov_camera/ov_camera.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static void ov_camera_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_ov_camera_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_i2c i2c_vcm = { + .address = config->vcm_addr, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", config->acpi_hid); + acpigen_write_name_integer("_UID", config->acpi_uid); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ +// acpigen_write_method("_CRS", 0) + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpi_device_write_i2c(&i2c_vcm); +/* + int i; + for (i = 0; i < 4; i++) { + struct acpi_i2c i2c_eeprom = { + .address = config->eeprom0_addr + i, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + acpi_device_write_i2c(&i2c_eeprom); + } +*/ + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + acpigen_write_method_serialized("SSDB",0); + acpigen_write_return_byte_buffer((uint8_t *)&config->buf, + MAX_SSDB_BUF); + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + +} + +static const char *ov_camera_acpi_name(struct device *dev) +{ + struct drivers_i2c_ov_camera_config *config = dev->chip_info; + return config->acpi_name; +} +#endif + +static struct device_operations ov_camera_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &ov_camera_acpi_name, + .acpi_fill_ssdt_generator = &ov_camera_fill_ssdt, +#endif +}; + +static void ov_camera_enable(struct device *dev) +{ + dev->ops = &ov_camera_ops; +} + +struct chip_operations drivers_i2c_ov_camera_ops = { + CHIP_NAME("OV CAMERA") + .enable_dev = &ov_camera_enable +};

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Patch set updated for coreboot: mainboard/google/poppy: Enable Realtek 5663 support
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18216 -gerrit commit 5fcb593d5b7b046e0b4045709c9f0a5cfdbd7bcf Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Feb 7 21:11:45 2017 +0530 mainboard/google/poppy: Enable Realtek 5663 support Enable Realtek RT5663 codec i2c device and add required SSDT parameters. BUG=None BRANCH=None TEST=With required driver support in kernel verify audio on headset Change-Id: I9b9eb1e7edca56870f5be0e4fd603c9b0dc7f9de Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 88ee84f..38d58c7 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -231,6 +231,14 @@ chip soc/intel/skylake register "name" = ""MAXL"" device i2c 3A on end end + chip drivers/i2c/generic + register "hid" = ""10EC5663"" + register "name" = ""RT53"" + register "desc" = ""Realtek RT5663"" + register "irq" = "IRQ_LEVEL_LOW(GPP_D9_IRQ)" + register "probed" = "1" + device i2c 13 on end + end end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on

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Patch set updated for coreboot: mainboard/google/poppy: Enable Maxim 98927 codec
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18215 -gerrit commit c995de33f4f6d651705cf0eca5e0094fe555f63b Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:22:42 2017 +0530 mainboard/google/poppy: Enable Maxim 98927 codec Enable Maxim 98927 codec i2c device and add required SSDT parameters. BUG=None BRANCH=None TEST=with required driver support in kernel verfy audio on poppy on-board speakers. Change-Id: Id731de42d77204d59f32ac4c33a245837d6e2107 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Dylan Reid <dgreid(a)chromium.org> --- src/mainboard/google/poppy/Kconfig | 3 +++ src/mainboard/google/poppy/devicetree.cb | 17 ++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index bd25589..3e00f9c 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -21,6 +21,9 @@ config CHROMEOS config DRIVERS_I2C_GENERIC def_bool y +config DRIVERS_I2C_MAX98927 + def_bool y + config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index a9e0cef..88ee84f 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -216,7 +216,22 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 + device pci 19.1 on + chip drivers/i2c/max98927 + register "interleave_mode" = "1" + register "uid" = "0" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 39 on end + end + chip drivers/i2c/max98927 + register "interleave_mode" = "1" + register "uid" = "1" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 3A on end + end + end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi

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Patch set updated for coreboot: mainboard/google/poppy: Generate required nhlt table
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18214 -gerrit commit eb8640513d1a02c2a8017058c8bd6809a9e4c35d Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:30:01 2017 +0530 mainboard/google/poppy: Generate required nhlt table poppy board uses Maxim 98927 speaker codec and Realtek RT5663 for heaset. Select the apropriate NHLT blobs to be packaged in CBFS. Also, generate the required ACPI NHLT table for codec and the supported topology in poppy. BUG=None BRANCH=None TEST=With the required driver support in kernel verify that the Audio plays on on-board speakers and headset, recording works from on-boards mics and headset mics. Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed Signed-off-by: M Naveen <naveen.m(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 6 ++++ src/mainboard/google/poppy/mainboard.c | 53 ++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 3625fc9..bd25589 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -42,4 +42,10 @@ config MAX_CPUS int default 8 +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH + select NHLT_DMIC_4CH + select NHLT_RT5663 + select NHLT_MAX98927 endif diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 29559b3..6931a30 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -14,19 +14,72 @@ */ #include <arch/acpi.h> +#include <console/console.h> #include <device/device.h> #include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <soc/nhlt.h> + +static const char *oem_id_maxim = "GOOGLE"; +static const char *oem_table_id_maxim = "POPPYMAX"; static void mainboard_init(device_t dev) { mainboard_ec_init(); } + +static unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + const char *oem_id = NULL; + const char *oem_table_id = NULL; + uint32_t oem_revision = 0; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); + + /* MAXIM98927 Smart Amps for left and right channel */ + if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add max98927\n"); + + /* RT5663 Headset codec. */ + if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + oem_id = oem_id_maxim; + oem_table_id = oem_table_id_maxim; + + end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, + oem_id, oem_table_id, oem_revision); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } struct chip_operations mainboard_ops = {

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Patch set updated for coreboot: soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18213 -gerrit commit c9b1c68af73f6a1df98e45c0ebb3f460d7769018 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Sat Jan 14 06:08:21 2017 +0530 soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support Add APIs and required parameters for creating Maxim 98927 and Realtek 5336 SSP endpoints in NHLT table. Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: M Naveen <naveen.m(a)intel.com> --- src/soc/intel/skylake/Kconfig | 13 ++++++ src/soc/intel/skylake/include/soc/nhlt.h | 12 ++++++ src/soc/intel/skylake/nhlt/Makefile.inc | 19 ++++++++- src/soc/intel/skylake/nhlt/max98927.c | 47 +++++++++++++++++++++ src/soc/intel/skylake/nhlt/rt5663.c | 71 ++++++++++++++++++++++++++++++++ 5 files changed, 161 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9dcafe6..725a25d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -59,6 +59,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC + select ACPI_NHLT config MAINBOARD_USES_FSP2_0 bool @@ -234,6 +235,18 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. +config NHLT_RT5663 + bool + default n + help + Include DSP firmware settings for rt5663 headset codec. + +config NHLT_MAX98927 + bool + default n + help + Include DSP firmware settings for max98927 amplifier. + config SKIP_FSP_CAR bool "Skip cache as RAM setup in FSP" default y diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 008dd0d..3993003 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -60,4 +60,16 @@ int nhlt_soc_add_ssm4567(struct nhlt *nhlt, int hwlink); */ int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +/* + * Add rt5663 headset codec on provided SSP link. Return 0 on success, < 0 + * on error. + */ +int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink); + +/* + * Add max98927 amplifier in stereo configuration on provided SSP link. + * Return 0 on success, < 0 on error. + */ +int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink); + #endif diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index e022482..743a931 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -2,9 +2,16 @@ ramstage-y += dmic.c ramstage-y += nau88l25.c ramstage-y += max98357.c ramstage-y += ssm4567.c +ramstage-y += rt5663.c +ramstage-y += max98927.c # DSP firmware settings files. -NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/skylake +ifeq ($(CONFIG_SOC_INTEL_KABYLAKE),y) +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/kabylake/nhlt-blobs +else +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/skylake/nhlt-blobs +endif + DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin @@ -13,6 +20,8 @@ NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin SSM4567_RENDER = ssm4567-render-2ch-48khz-24b.bin SSM4567_CAPTURE = ssm4567-capture-4ch-48khz-32b.bin +RT5663 = rt5663-2ch-48khz-24b.bin +MAX98927_RENDER = max98927-render-2ch-48khz-24b.bin cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) @@ -45,3 +54,11 @@ $(SSM4567_RENDER)-type := raw cbfs-files-$(CONFIG_NHLT_SSM4567) += $(SSM4567_CAPTURE) $(SSM4567_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(SSM4567_CAPTURE) $(SSM4567_CAPTURE)-type := raw + +cbfs-files-$(CONFIG_NHLT_RT5663) += $(RT5663) +$(RT5663)-file := $(NHLT_BLOB_PATH)/$(RT5663) +$(RT5663)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98927) += $(MAX98927_RENDER) +$(MAX98927_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98927_RENDER) +$(MAX98927_RENDER)-type := raw diff --git a/src/soc/intel/skylake/nhlt/max98927.c b/src/soc/intel/skylake/nhlt/max98927.c new file mode 100644 index 0000000..77b72aa --- /dev/null +++ b/src/soc/intel/skylake/nhlt/max98927.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/nhlt.h> + +static const struct nhlt_format_config max98927_render_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "max98927-render-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_endp_descriptor max98927_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98927_render_formats, + .num_formats = ARRAY_SIZE(max98927_render_formats), + }, +}; + +int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98927_descriptors, + ARRAY_SIZE(max98927_descriptors)); +} diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c new file mode 100644 index 0000000..ab361de --- /dev/null +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/nhlt.h> + +/* The same DSP firmware settings are used for both the capture and + * render endpoints. */ +static const struct nhlt_format_config rt5663_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "rt5663-2ch-48khz-24b.bin", + }, +}; + +/* The rt5663 just has headphones and a mic. Both the capture and render + * endpoints occupy the same virtual slot. */ +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_endp_descriptor rt5663_descriptors[] = { + /* Render Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = rt5663_formats, + .num_formats = ARRAY_SIZE(rt5663_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = rt5663_formats, + .num_formats = ARRAY_SIZE(rt5663_formats), + }, +}; + +int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5663_descriptors, + ARRAY_SIZE(rt5663_descriptors)); +}

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Patch set updated for coreboot: driver/i2c/max98927: add i2c driver for Maxim 98927 codec
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18211 -gerrit commit 011205f0548119f3cd623658c09d1e9650858466 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:17:01 2017 +0530 driver/i2c/max98927: add i2c driver for Maxim 98927 codec Maxim 98927 kernel driver requires entries in the ACPI SSDT table, add a SSDT generator as part of this driver. BUG=None BRANCH=None TEST=After boot, dump and verify that the generated SSDT ACPI table has the required entries. Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: M Naveen <naveen.m(a)intel.com> Signed-off-by: Dylan Reid <dgreid(a)chromium.org> --- src/drivers/i2c/max98927/Kconfig | 2 + src/drivers/i2c/max98927/Makefile.inc | 1 + src/drivers/i2c/max98927/chip.h | 30 ++++++++++ src/drivers/i2c/max98927/max98927.c | 108 ++++++++++++++++++++++++++++++++++ 4 files changed, 141 insertions(+) diff --git a/src/drivers/i2c/max98927/Kconfig b/src/drivers/i2c/max98927/Kconfig new file mode 100644 index 0000000..1007442 --- /dev/null +++ b/src/drivers/i2c/max98927/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_MAX98927 + bool diff --git a/src/drivers/i2c/max98927/Makefile.inc b/src/drivers/i2c/max98927/Makefile.inc new file mode 100644 index 0000000..3bafee1 --- /dev/null +++ b/src/drivers/i2c/max98927/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_MAX98927) += max98927.c diff --git a/src/drivers/i2c/max98927/chip.h b/src/drivers/i2c/max98927/chip.h new file mode 100644 index 0000000..d63244f --- /dev/null +++ b/src/drivers/i2c/max98927/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Maxim MAX98927 audio codec devicetree bindings + */ +struct drivers_i2c_max98927_config { + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned int bus_speed; + /* Set ‘1’ if I2S channel size is not 32bit. */ + unsigned int interleave_mode; + /*Identifier for chips*/ + unsigned int uid; + /* Device Description */ + const char *desc; + /* ACPI Device Name */ + const char *name; +}; diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c new file mode 100644 index 0000000..1f5fabf --- /dev/null +++ b/src/drivers/i2c/max98927/max98927.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define MAX98927_ACPI_NAME "MAXI" +#define MAX98927_ACPI_HID "MX98927" + +#define MAX98927_DP_INT(key, val) \ + acpi_dp_add_integer(dp, "maxim," key, (val)) + +static void max98927_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_max98927_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dp = NULL; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", MAX98927_ACPI_HID); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + dp = acpi_dp_new_table("_DSD"); + + acpi_dp_add_integer(dp, "interleave_mode", config->interleave_mode); + + acpi_dp_write(dp); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh\n", + acpi_device_path(dev), dev->chip_ops->name, + dev->path.i2c.device); +} + +static const char *max98927_acpi_name(struct device *dev) +{ + struct drivers_i2c_max98927_config *config = dev->chip_info; + + if (config->name) + return config->name; + + return MAX98927_ACPI_NAME; +} +#endif + +static struct device_operations max98927_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &max98927_acpi_name, + .acpi_fill_ssdt_generator = &max98927_fill_ssdt, +#endif +}; + +static void max98927_enable(struct device *dev) +{ + dev->ops = &max98927_ops; +} + +struct chip_operations drivers_i2c_max98927_ops = { + CHIP_NAME("Maxim MAX98927 Codec") + .enable_dev = &max98927_enable +};

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Patch set updated for coreboot: mainboard/eve: select SOC_INTEL_KABYLAKE
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18314 -gerrit commit 74bb4c16016b7738560680e9028b7a826e50f48d Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 9 16:34:08 2017 +0530 mainboard/eve: select SOC_INTEL_KABYLAKE eve is based on Kabylake SoC hence select the appropriate config. Change-Id: I756dda5a1924e83a02ac1cebb1907884f436a13f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/eve/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index e83e7d9..95ad4de 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_FSP2_0 - select SOC_INTEL_SKYLAKE + select SOC_INTEL_KABYLAKE select TPM2 config CHROMEOS

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Patch set updated for coreboot: mainboard/poppy: select SOC_INTEL_KABYLAKE
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18313 -gerrit commit 5f7554003fc54441ccf49dd33a0871adabd5d1f6 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 9 16:32:20 2017 +0530 mainboard/poppy: select SOC_INTEL_KABYLAKE poppy is based on Kabylake SoC hence select the appropriate config. Change-Id: Ie339a3991eeccb8a7dba983a2b5ab5d1c996ce9d Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index db0ebb1..3625fc9 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -10,8 +10,8 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select MAINBOARD_USES_FSP2_0 - select SOC_INTEL_SKYLAKE select NO_FADT_8042 + select SOC_INTEL_KABYLAKE config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES

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Patch set updated for coreboot: soc/intel/skylake: Add config option for Kabylake
by Rizwan Qureshi 13 Feb '17

13 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18312 -gerrit commit 970e9e0b3f0a3f202fbbf4cb8b9e89d2662603b4 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 9 15:57:45 2017 +0530 soc/intel/skylake: Add config option for Kabylake Currently there is no distinction between mainboards using Skylake or Kabylake SoC, Add a config option for Kabylake SoC to allow mainboards to explicitly select if they are using it. Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 090fa2a..9dcafe6 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -3,6 +3,13 @@ config SOC_INTEL_SKYLAKE help Intel Skylake support +config SOC_INTEL_KABYLAKE + bool + default n + select SOC_INTEL_SKYLAKE + help + Intel Kabylake support + if SOC_INTEL_SKYLAKE config CPU_SPECIFIC_OPTIONS

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coreboot-gerrit February 2017