Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18364
-gerrit
commit 45a1809b9a15e92c78229bec6ff5f80f55fa0357
Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com>
Date: Tue Feb 14 22:16:58 2017 +0800
soc/intel/skylake: Expand USB OC pins definition to support PCH-H
Currently the USB OC pins definition only being defined up to OC3.
For PCH-H, OC4 and OC5 are needed, without these, it will causes
boot fail in FspSiliconInit
Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb
Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com>
---
src/soc/intel/skylake/include/soc/usb.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h
index 77a94a8..d4f7cc5 100644
--- a/src/soc/intel/skylake/include/soc/usb.h
+++ b/src/soc/intel/skylake/include/soc/usb.h
@@ -51,6 +51,8 @@ enum {
OC1,
OC2,
OC3,
+ OC4,
+ OC5,
OC_SKIP = 8, /* Skip OC programming */
};
Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18362
-gerrit
commit 7b8aea595a32a2a26322224f7c3004bb37db96d3
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Mon Feb 13 13:44:14 2017 -0800
arch/x86: add library function for coreboot to generate random number
using x86 RDRAND instruction.
Two functions are supplied to generate 32bit or 64bit number.
One potential usage is the sealing key generation for SGX.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve to generate a 64bit random number.
Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
---
src/arch/x86/Makefile.inc | 1 +
src/arch/x86/include/arch/rdrand.h | 27 ++++++++++++++
src/arch/x86/rdrand.c | 76 ++++++++++++++++++++++++++++++++++++++
3 files changed, 104 insertions(+)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index c4bb1cc..332e8ec 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -334,6 +334,7 @@ ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
ramstage-y += pci_ops_conf1.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
+ramstage-y += rdrand.c
ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
ramstage-y += tables.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
diff --git a/src/arch/x86/include/arch/rdrand.h b/src/arch/x86/include/arch/rdrand.h
new file mode 100644
index 0000000..74166d9
--- /dev/null
+++ b/src/arch/x86/include/arch/rdrand.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef ARCH_RDRAND_H
+#define ARCH_RDRAND_H
+
+#include <stdint.h>
+
+/*
+ * Generates a 32/64 bit random number respectively.
+ * return 0 on success and -1 on error.
+ */
+int get_random_number_32(uint32_t *rand);
+int get_random_number_64(uint64_t *rand);
+
+#endif /* ARCH_RDRAND_H */
diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c
new file mode 100644
index 0000000..9f7ed81
--- /dev/null
+++ b/src/arch/x86/rdrand.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/rdrand.h>
+
+#define RDRAND_RETRY_LOOPS 10
+
+/* Generate a 32-bit random number through RDRAND instruction. */
+static inline uint8_t rdrand_32(uint32_t *rand)
+{
+ uint8_t carry;
+
+ __asm__ __volatile__(
+ ".byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1"
+ : "=a" (*rand), "=qm" (carry));
+ return carry;
+}
+
+#ifdef __x86_64__
+/* Generate a 64-bit random number through RDRAND instruction. */
+static inline uint8_t rdrand_64(uint64_t *rand)
+{
+ uint8_t carry;
+
+ __asm__ __volatile__(
+ ".byte 0x48; .byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1"
+ : "=a" (*rand), "=qm" (carry));
+ return carry;
+}
+#endif
+
+int get_random_number_32(uint32_t *rand)
+{
+ int i;
+
+ /* Perform a loop call until RDRAND succeeds or returns failure. */
+ for (i = 0; i < RDRAND_RETRY_LOOPS; i++) {
+ if (rdrand_32(rand))
+ return 0;
+ }
+ return -1;
+}
+
+int get_random_number_64(uint64_t *rand)
+{
+ int i;
+#ifndef __x86_64__
+ uint32_t rand_high, rand_low;
+#endif
+
+ /* Perform a loop call until RDRAND succeeds or returns failure. */
+ for (i = 0; i < RDRAND_RETRY_LOOPS; i++) {
+#ifdef __x86_64__
+ if (rdrand_64(rand))
+ return 0;
+#else
+ if (rdrand_32(&rand_high) && rdrand_32(&rand_low)) {
+ *rand = ((uint64_t)rand_high << 32) | (uint64_t)rand_low;
+ return 0;
+ }
+#endif
+ }
+ return -1;
+}
the following patch was just integrated into master:
commit b07d266042621e050962bb9ce814f1106d0a8bcf
Author: Jenny TC <jenny.tc(a)intel.com>
Date: Thu Feb 9 16:16:20 2017 +0530
google/poppy: select NO_FADT_8042
Poppy doesn't support 8042 keyboard. Select
NO_FADT_8042 to disable 8042 in FADT header.
Kernel will not try to access 8042 region
if 8042.FADT=0
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: I00182eb4b059d4d9f0705d349dc98651e3955f0d
Signed-off-by: Jenny TC <jenny.tc(a)intel.com>
Reviewed-on: https://review.coreboot.org/18311
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18311 for details.
-gerrit
the following patch was just integrated into master:
commit 2864f85725e517ece5d5ce985c51b4561f81dab6
Author: Jenny TC <jenny.tc(a)intel.com>
Date: Thu Feb 9 16:01:59 2017 +0530
intel/skylake: Disable FADT.8042 if NO_FADT_8042 is set
Kernel relies on FADT 8042 flag to enable/disable
8042 interface. If FADT reports 8042 capability and
8042 (/PS2) capability is actually disabled by coreboot,
kernel would assume the presence of 8042 based on the
FADT flag. This results in undesired system power off when
kernel tries to access the 8042 memory region. To address
this, CONFIG_NO_FADT_8042 was added to selectively
disable 8042 on FADT.
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc
Signed-off-by: Jenny TC <jenny.tc(a)intel.com>
Reviewed-on: https://review.coreboot.org/18307
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18307 for details.
-gerrit
Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18342
-gerrit
commit 912a8856a740505e9ecd55302f553c2f4193242b
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Sat Feb 11 11:16:18 2017 -0800
drivers/spi: Add support for generating SPI device in SSDT
Similar to I2C driver, add support for generating SPI device and
required properties in SSDT for ACPI.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles succesfully. Verified SPI device generated in SSDT on
poppy.
Change-Id: Ic4da79c823131d54d9eb3652b86f6e40fe643ab5
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
src/drivers/spi/acpi/Kconfig | 18 +++++
src/drivers/spi/acpi/Makefile.inc | 16 +++++
src/drivers/spi/acpi/acpi.c | 146 ++++++++++++++++++++++++++++++++++++++
src/drivers/spi/acpi/chip.h | 32 +++++++++
4 files changed, 212 insertions(+)
diff --git a/src/drivers/spi/acpi/Kconfig b/src/drivers/spi/acpi/Kconfig
new file mode 100644
index 0000000..c1653d5
--- /dev/null
+++ b/src/drivers/spi/acpi/Kconfig
@@ -0,0 +1,18 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2017 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+config DRIVERS_SPI_ACPI
+ bool
+ depends on HAVE_ACPI_TABLES
diff --git a/src/drivers/spi/acpi/Makefile.inc b/src/drivers/spi/acpi/Makefile.inc
new file mode 100644
index 0000000..7ae6e45
--- /dev/null
+++ b/src/drivers/spi/acpi/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2017 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ramstage-$(CONFIG_DRIVERS_SPI_ACPI) += acpi.c
diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c
new file mode 100644
index 0000000..0d7d2aa
--- /dev/null
+++ b/src/drivers/spi/acpi/acpi.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi_device.h>
+#include <arch/acpigen.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <device/spi.h>
+#include <spi-generic.h>
+#include <stdint.h>
+#include <string.h>
+#include "chip.h"
+
+static int spi_acpi_get_bus(struct device *dev)
+{
+ struct device *spi_dev;
+ struct device_operations *ops;
+
+ if (!dev->bus || !dev->bus->dev)
+ return -1;
+
+ spi_dev = dev->bus->dev;
+ ops = spi_dev->ops;
+
+ if (ops && ops->ops_spi_bus &&
+ ops->ops_spi_bus->dev_to_bus)
+ return ops->ops_spi_bus->dev_to_bus(spi_dev);
+
+ return -1;
+}
+
+static void spi_acpi_fill_ssdt_generator(struct device *dev)
+{
+ struct drivers_spi_acpi_config *config = dev->chip_info;
+ const char *scope = acpi_device_scope(dev);
+ struct spi_cfg spi_cfg;
+ struct spi_slave slave;
+ int bus = -1, cs = dev->path.spi.cs;
+ struct acpi_spi spi = {
+ .device_select = cs,
+ .speed = config->speed ? : 1 * MHz,
+ .resource = scope,
+ };
+
+ if (!dev->enabled || !scope)
+ return;
+
+ bus = spi_acpi_get_bus(dev);
+ if (bus == -1) {
+ printk(BIOS_ERR, "%s: ERROR: Cannot get bus for device.\n",
+ dev_path(dev));
+ return;
+ }
+
+ if (!config->hid) {
+ printk(BIOS_ERR, "%s: ERROR: HID required.\n", dev_path(dev));
+ return;
+ }
+
+ if (spi_setup_slave(bus, cs, &slave)) {
+ printk(BIOS_ERR, "%s: ERROR: SPI setup failed.\n",
+ dev_path(dev));
+ return;
+ }
+
+ if (spi_get_config(&slave, &spi_cfg)) {
+ printk(BIOS_ERR, "%s: ERROR: SPI get config failed.\n",
+ dev_path(dev));
+ return;
+ }
+
+ spi.device_select_polarity = spi_cfg.cs_polarity;
+ spi.wire_mode = spi_cfg.wire_mode;
+ spi.data_bit_length = spi_cfg.data_bit_length;
+ spi.clock_phase = spi_cfg.clk_phase;
+
+ /* Device */
+ acpigen_write_scope(scope);
+ acpigen_write_device(acpi_device_name(dev));
+ acpigen_write_name_string("_HID", config->hid);
+ if (config->cid)
+ acpigen_write_name_string("_CID", config->cid);
+ acpigen_write_name_integer("_UID", config->uid);
+ if (config->desc)
+ acpigen_write_name_string("_DDN", config->desc);
+
+ /* Resources */
+ acpigen_write_name("_CRS");
+ acpigen_write_resourcetemplate_header();
+ acpi_device_write_spi(&spi);
+ acpi_device_write_interrupt(&config->irq);
+ acpigen_write_resourcetemplate_footer();
+
+ if (config->compat_string) {
+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+ acpi_dp_add_string(dsd, "compatible", config->compat_string);
+ acpi_dp_write(dsd);
+ }
+
+ acpigen_pop_len(); /* Device */
+ acpigen_pop_len(); /* Scope */
+}
+
+static const char *spi_acpi_name(struct device *dev)
+{
+ struct drivers_spi_acpi_config *config = dev->chip_info;
+ static char name[5];
+
+ if (config->name)
+ return config->name;
+
+ snprintf(name, sizeof(name), "S%03.3X", spi_acpi_get_bus(dev));
+ name[4] = '\0';
+ return name;
+}
+
+static struct device_operations spi_acpi_ops = {
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .acpi_name = &spi_acpi_name,
+ .acpi_fill_ssdt_generator = &spi_acpi_fill_ssdt_generator,
+};
+
+static void spi_acpi_enable(struct device *dev)
+{
+ dev->ops = &spi_acpi_ops;
+}
+
+struct chip_operations drivers_spi_acpi_ops = {
+ CHIP_NAME("SPI Device")
+ .enable_dev = &spi_acpi_enable
+};
diff --git a/src/drivers/spi/acpi/chip.h b/src/drivers/spi/acpi/chip.h
new file mode 100644
index 0000000..f0cc941
--- /dev/null
+++ b/src/drivers/spi/acpi/chip.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SPI_ACPI_CHIP_H__
+#define __SPI_ACPI_CHIP_H__
+
+#include <arch/acpi_device.h>
+
+struct drivers_spi_acpi_config {
+ const char *hid; /* ACPI _HID (required) */
+ const char *cid; /* ACPI _CID */
+ const char *name; /* ACPI Device Name */
+ const char *desc; /* Device Description */
+ unsigned uid; /* ACPI _UID */
+ unsigned speed; /* Bus speed in Hz (default 1MHz) */
+ const char *compat_string; /* Compatible string for _HID=PRP0001 */
+ struct acpi_irq irq; /* Interrupt */
+};
+
+#endif /* __SPI_ACPI_CHIP_H__ */