coreboot-gerrit December 2017

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Change in libgfxinit[master]: gma: Reverse meaning of GTT_Rotation_Offset
by Nico Huber (Code Review) 14 Dec '17

14 Dec '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/22864 ) Change subject: gma: Reverse meaning of GTT_Rotation_Offset ...................................................................... Patch Set 1: Verified+1 -- To view, visit https://review.coreboot.org/22864 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I321a3db3af4b21eefbfc1bf0c2a7005feaf83c7a Gerrit-Change-Number: 22864 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 14 Dec 2017 20:07:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/common/psp: Assume PSP command register already set up
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22846 ) Change subject: amd/common/psp: Assume PSP command register already set up ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19324/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64535/ : SUCCESS -- To view, visit https://review.coreboot.org/22846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666 Gerrit-Change-Number: 22846 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 20:03:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: include/cpu/x86: Add clflush inline function
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22848 ) Change subject: include/cpu/x86: Add clflush inline function ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19327/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64538/ : SUCCESS -- To view, visit https://review.coreboot.org/22848 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I74c5cc22f02302314ba010bc599051c1495a13cb Gerrit-Change-Number: 22848 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 20:02:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/common/psp: Add BootDone command
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22787 ) Change subject: amd/common/psp: Add BootDone command ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19326/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64537/ : SUCCESS -- To view, visit https://review.coreboot.org/22787 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88 Gerrit-Change-Number: 22787 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 20:02:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Force PSP command reg settings in bootblock
by Marshall Dawson (Code Review) 14 Dec '17

14 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22876 Change subject: amd/stoneyridge: Force PSP command reg settings in bootblock ...................................................................... amd/stoneyridge: Force PSP command reg settings in bootblock A subsequent patch to the PSP library will rely on the device already having its PCI command register set to allow memory decoding and mastering enabled. Program the command register ahead of loading the SMU FW1 blob in bootblock. When the device has not been set up (e.g. when SMU FW is not selectable), AGESA sets up the device. As a result, a similar change is not required before sending the DRAM ready command. Change-Id: Id586106751286c4767b5c16ed7e1604523635492 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/bootblock/bootblock.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22876/1 diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 030c990..9f3827d 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -88,7 +88,7 @@ */ static void load_smu_fw1(void) { - u32 base, limit; + u32 base, limit, cmd; /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ base = 0x80000000; @@ -101,6 +101,11 @@ pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); + /* Enable memory access and master */ + cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); + psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); } -- To view, visit https://review.coreboot.org/22876 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id586106751286c4767b5c16ed7e1604523635492 Gerrit-Change-Number: 22876 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Disable SATA controller
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22875 ) Change subject: mainboard/intel/cannonlake_rvp: Disable SATA controller ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19323/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64534/ : SUCCESS -- To view, visit https://review.coreboot.org/22875 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8 Gerrit-Change-Number: 22875 Gerrit-PatchSet: 2 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 19:43:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Disable SATA controller
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22875 ) Change subject: mainboard/intel/cannonlake_rvp: Disable SATA controller ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19322/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64533/ : SUCCESS -- To view, visit https://review.coreboot.org/22875 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8 Gerrit-Change-Number: 22875 Gerrit-PatchSet: 1 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 19:30:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: security/crypto: Add crypto primitives for hashing data
by Martin Roth (Code Review) 14 Dec '17

14 Dec '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/22872 ) Change subject: security/crypto: Add crypto primitives for hashing data ...................................................................... Patch Set 5: (5 comments) https://review.coreboot.org/#/c/22872/5/.checkpatch.conf File .checkpatch.conf: https://review.coreboot.org/#/c/22872/5/.checkpatch.conf@31 PS5, Line 31: --exclude src/security/crypto/hash Add a comment: # Exclude hashing library https://review.coreboot.org/#/c/22872/5/src/security/crypto/Kconfig File src/security/crypto/Kconfig: https://review.coreboot.org/#/c/22872/5/src/security/crypto/Kconfig@3 PS5, Line 3: ## Copyright (C) 2017 Philipp Deppenwiese, Facebook, Inc. Maybe: Copyright (C) 2017 Facebook, Inc. (Written by Philipp Deppenwiese <zaolin(a)das-labor.org> for Facebook, Inc.) Up to you. https://review.coreboot.org/#/c/22872/5/src/security/crypto/Kconfig@15 PS5, Line 15: menu "Cryptographic Primitives" remove if prompt is removed. https://review.coreboot.org/#/c/22872/5/src/security/crypto/Kconfig@18 PS5, Line 18: "Enable hashing primitives" Leave out the prompt - I'd think this would be selected by some other feature that uses it. By itself it doesn't do anything, so probably shouldn't be user facing. https://review.coreboot.org/#/c/22872/5/src/security/crypto/Kconfig@23 PS5, Line 23: : If unsure, say N. remove if prompt is removed. -- To view, visit https://review.coreboot.org/22872 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I807084ebfffdc159fe95c45b4e5f0820bbfee5e1 Gerrit-Change-Number: 22872 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 19:23:28 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Disable SATA controller
by Vaibhav Shankar (Code Review) 14 Dec '17

14 Dec '17

Vaibhav Shankar has uploaded this change for review. ( https://review.coreboot.org/22875 Change subject: mainboard/intel/cannonlake_rvp: Disable SATA controller ...................................................................... mainboard/intel/cannonlake_rvp: Disable SATA controller SATA was enabled only for internal testing. Since we do not use SATA on chrome platforms, it can be disabled. Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/22875/1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 2f472e2..a874f4c 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -30,9 +30,9 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "SataEnable" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "SataEnable" = "0" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "0" register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" @@ -95,7 +95,7 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 off end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index ca46d36..0d29a98 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -30,9 +30,9 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "SataEnable" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "SataEnable" = "0" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "0" register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" @@ -93,7 +93,7 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 off end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 -- To view, visit https://review.coreboot.org/22875 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8 Gerrit-Change-Number: 22875 Gerrit-PatchSet: 1 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Fix UART2 serial log broken issue
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22862 ) Change subject: soc/intel/cannonlake: Fix UART2 serial log broken issue ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64532/ : SUCCESS -- To view, visit https://review.coreboot.org/22862 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a Gerrit-Change-Number: 22862 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 14 Dec 2017 18:37:29 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017