coreboot-gerrit December 2017

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Change in coreboot[master]: soc/amd/common: Add S3 supporting functions
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22727 Change subject: soc/amd/common: Add S3 supporting functions ...................................................................... soc/amd/common: Add S3 supporting functions Add functions that the wrapper will call to get and save the S3 data. The wrapper requires two types of data saved: * Non-volatile: information that is the minimum required for bringing the memory controller back online * Volatile: may be stored in DRAM; information required to complete the system restoration process. For each type, the code stores AGESA's reported size followed by the data itself. AGESA does not save and restore MTRR settings, so this patch saves the current register settings and adds a function to restore them on a per-core basis. (It is assumed each core is properly in sync during a suspend.) AGESA restores the Top Of Memory and TOM2 registers. Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/Makefile.inc M src/soc/amd/common/s3_resume.c M src/soc/amd/common/s3_resume.h 3 files changed, 287 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/22727/1 diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index 926262c..fe46233 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -9,6 +9,7 @@ romstage-y += agesawrapper.c romstage-y += def_callouts.c romstage-y += heapmanager.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-y += agesawrapper.c ramstage-y += amd_late_init.c diff --git a/src/soc/amd/common/s3_resume.c b/src/soc/amd/common/s3_resume.c index 44c86e6..678f65b 100644 --- a/src/soc/amd/common/s3_resume.c +++ b/src/soc/amd/common/s3_resume.c @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012-2017 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,27 +14,283 @@ * GNU General Public License for more details. */ +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/cache.h> +#include <cbmem.h> +#include <fmap.h> #include <console/console.h> #include <spi-generic.h> #include <spi_flash.h> +#include <region_file.h> +#include <security/vboot/vboot_common.h> +#include <string.h> +#include <soc/iomap.h> #include "s3_resume.h" +#include <BiosCallOuts.h> +#include <agesa_headers.h> -void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) +#if !IS_ENABLED(CONFIG_SPI_FLASH) +#error "CONFIG_SPI_FLASH must be enabled" +#endif + +int spi_save_s3_info(struct region dst, struct region src) { struct spi_flash flash; + int status; + + if (src.size == 0) + return 0; spi_init(); if (spi_flash_probe(0, 0, &flash)) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - /* Dont make flow stop. */ + printk(BIOS_DEBUG, "S3 SPI: couldn't find SPI device\n"); + return -1; + } + + /* need to write the data plus the size below */ + if (src.size + sizeof(src.size) > dst.size) { + printk(BIOS_DEBUG, "S3 SPI: src is larger than dest.\n"); + return -1; + } + + status = spi_flash_volatile_group_begin(&flash); + if (status) + goto error; + + status = spi_flash_erase(&flash, dst.offset, dst.size); + if (status) + goto error; + + /* write size first */ + status = spi_flash_write(&flash, dst.offset, sizeof(src.size), + (void *)&src.size); + if (status) + goto error; + + /* write buffer */ + status = spi_flash_write(&flash, dst.offset + sizeof(dst.size), + src.size, (void *)src.offset); + +error: + spi_flash_volatile_group_end(&flash); + return status; +} + +static int lookup_region_by_name(const char *name, struct region *r) +{ + /* todo: make Intel MRC cache location common, convert AMD to use it. */ + if (fmap_locate_area(name, r) == 0) + return 0; + + if (IS_ENABLED(CONFIG_VBOOT)) { + printk(BIOS_ERR, "Error: vboot requires flash map for S3\n"); + return -1; + } + + /* Fall back to Kconfig values */ + if (!CONFIG_S3_DATA_POS || !CONFIG_S3_DATA_SIZE) + return -1; + + r->offset = CONFIG_S3_DATA_POS; + r->size = CONFIG_S3_DATA_SIZE; + return 0; +} + +static void get_s3nv_region(struct region *nv) +{ + int status = lookup_region_by_name("RW_MRC_CACHE", nv); + if (status) { + nv->offset = 0; + nv->size = 0; + return; + } +} + +static void get_s3vol_region(struct region *vol) +{ + struct cbmem_usage *heap = (struct cbmem_usage *)GetHeapBase(); + if (!heap) { + printk(BIOS_ERR, "Error locating CBMEM_ID_RESUME_SCRATCH\n"); + return; + } + vol->offset = (size_t)heap->s3_vol_data; + vol->size = S3_VOLATILE_SIZE; +} + +static void get_s3mtrr_region(struct region *mtrr) +{ + struct cbmem_usage *heap = (struct cbmem_usage *)GetHeapBase(); + if (!heap) { + printk(BIOS_ERR, "Error locating CBMEM_ID_RESUME_SCRATCH\n"); + return; + } + mtrr->offset = (size_t)&heap->s3_mtrrs; + mtrr->size = sizeof(struct all_mtrrs); +} + +void restore_mtrr(void) +{ + u32 i; + msr_t msr; + struct all_mtrrs *mtrrs; + int num_vmtrrs; + + struct cbmem_usage *heap = (struct cbmem_usage *)GetHeapBase(); + if (!heap) { + printk(BIOS_ERR, "Error locating CBMEM_ID_RESUME_SCRATCH\n"); + return; + } + mtrrs = (struct all_mtrrs *)&heap->s3_mtrrs; + + msr = rdmsr(MTRR_CAP_MSR); + num_vmtrrs = msr.lo & MTRR_CAP_VCNT; + + disable_cache(); + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + /* Now restore the Fixed MTRRs */ + wrmsr(MTRR_FIX_64K_00000, mtrrs->_64k_00); + wrmsr(MTRR_FIX_16K_80000, mtrrs->_16k_80); + wrmsr(MTRR_FIX_16K_A0000, mtrrs->_16k_a0); + wrmsr(MTRR_FIX_4K_C0000, mtrrs->_4k_c0); + wrmsr(MTRR_FIX_4K_C8000, mtrrs->_4k_c8); + wrmsr(MTRR_FIX_4K_D0000, mtrrs->_4k_d0); + wrmsr(MTRR_FIX_4K_D8000, mtrrs->_4k_d8); + wrmsr(MTRR_FIX_4K_E0000, mtrrs->_4k_e0); + wrmsr(MTRR_FIX_4K_E8000, mtrrs->_4k_e8); + wrmsr(MTRR_FIX_4K_F0000, mtrrs->_4k_f0); + wrmsr(MTRR_FIX_4K_F8000, mtrrs->_4k_f8); + + for (i = 0 ; i < num_vmtrrs ; i++) { + wrmsr(MTRR_PHYS_BASE(i), mtrrs->vmtrr[i].base); + wrmsr(MTRR_PHYS_MASK(i), mtrrs->vmtrr[i].mask); + } + + wrmsr(SYSCFG_MSR, mtrrs->sys_cfg); +} + +static int save_mtrr(struct all_mtrrs *mtrrs) +{ + u32 i; + msr_t msr; + int num_vmtrrs; + + msr = rdmsr(MTRR_CAP_MSR); + num_vmtrrs = msr.lo & MTRR_CAP_VCNT; /* no. of supported var. MTRRs */ + + if (num_vmtrrs > MAX_VAR_MTRRS) { + printk(BIOS_ERR, "Error: Increase MAX_VAR_MTRRS for S3\n"); + return -1; + } + + /* Start saving */ + mtrrs->sys_cfg = rdmsr(SYSCFG_MSR); + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + /* Save the Fixed MTRRs */ + mtrrs->_64k_00 = rdmsr(MTRR_FIX_64K_00000); + mtrrs->_16k_80 = rdmsr(MTRR_FIX_16K_80000); + mtrrs->_16k_a0 = rdmsr(MTRR_FIX_16K_A0000); + mtrrs->_4k_c0 = rdmsr(MTRR_FIX_4K_C0000); + mtrrs->_4k_c8 = rdmsr(MTRR_FIX_4K_C8000); + mtrrs->_4k_d0 = rdmsr(MTRR_FIX_4K_D0000); + mtrrs->_4k_d8 = rdmsr(MTRR_FIX_4K_D8000); + mtrrs->_4k_e0 = rdmsr(MTRR_FIX_4K_E0000); + mtrrs->_4k_e8 = rdmsr(MTRR_FIX_4K_E8000); + mtrrs->_4k_f0 = rdmsr(MTRR_FIX_4K_F0000); + mtrrs->_4k_f8 = rdmsr(MTRR_FIX_4K_F8000); + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + for (i = 0 ; i < num_vmtrrs ; i++) { + mtrrs->vmtrr[i].base = rdmsr(MTRR_PHYS_BASE(i)); + mtrrs->vmtrr[i].mask = rdmsr(MTRR_PHYS_MASK(i)); + } + + /* AGESA restores TOM and TOM2 */ + + return 0; +} + +void get_s3_info(S3_DATA_TYPE type, struct region *info) +{ + struct region rgn = { .offset = 0, .size = 0 }; + + switch (type) { + case S3_DATA_TYPE_NV: + get_s3nv_region(&rgn); + rgn.offset += FLASH_BASE_ADDR; + printk(BIOS_SPEW, "S3 NV data @0x%zx\n", rgn.offset); + break; + case S3_DATA_TYPE_VOLATILE: + get_s3vol_region(&rgn); + printk(BIOS_SPEW, "S3 volatile data @0x%zx\n", rgn.offset); + break; + default: + printk(BIOS_ERR, "Error: %s called with bad type %d\n", + __func__, type); return; } - spi_flash_volatile_group_begin(&flash); + info->size = *(size_t *)rgn.offset; + info->offset = rgn.offset + sizeof(info->size); +} - spi_flash_erase(&flash, pos, size); - spi_flash_write(&flash, pos, sizeof(len), &len); - spi_flash_write(&flash, pos + sizeof(len), len, buf); +int save_s3_info(struct region nv, struct region vol) +{ + struct region dst; + void *data; - spi_flash_volatile_group_end(&flash); + printk(BIOS_SPEW, "%s(): S3 NV data @0x%zx (0x%zx bytes)" + " volatile data @0x%zx (0x%zx bytes)\n", + __func__, nv.offset, nv.size, + vol.offset, vol.size); + + get_s3vol_region(&dst); + if (vol.size && (dst.offset == 0 || dst.size == 0)) { + printk(BIOS_ERR, "Error: can't access S3 volatile save area\n"); + return -1; + } + + /* write size followed by AGESA's volatile data */ + data = (void *)(dst.offset + sizeof(size_t)); + memset((void *)dst.offset, 0, S3_VOLATILE_SIZE); + + *(size_t *)dst.offset = vol.size; + memcpy(data, (void *)vol.offset, vol.size); + + get_s3mtrr_region(&dst); + if (!dst.offset || !dst.size) { + printk(BIOS_ERR, "Error: can't access S3 MTRR save area\n"); + return -1; + } + + if (save_mtrr((void *)dst.offset)) + return -1; + + get_s3nv_region(&dst); + if (!dst.offset || !dst.size) { + printk(BIOS_ERR, "Error: can't find S3 NV save area\n"); + return -1; + } + + if (spi_save_s3_info(dst, nv)) { + printk(BIOS_ERR, "Error: can't save S3 NV data\n"); + return -1; + } + + return 0; } diff --git a/src/soc/amd/common/s3_resume.h b/src/soc/amd/common/s3_resume.h index 8dc60da..1abb79d 100644 --- a/src/soc/amd/common/s3_resume.h +++ b/src/soc/amd/common/s3_resume.h @@ -17,6 +17,20 @@ #define __S3_RESUME_H__ #include <cpu/x86/msr.h> +#include <commonlib/region.h> + +/* todo: Make the Intel MRC flash region management common and then use that + * instead of redefining it here. + */ +#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" +#define VARIABLE_MRC_CACHE "RW_VAR_MRC_CACHE" +#define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" +#define UNIFIED_MRC_CACHE "UNIFIED_MRC_CACHE" + +typedef enum { + S3_DATA_TYPE_NV = 0, + S3_DATA_TYPE_VOLATILE, +} S3_DATA_TYPE; #define S3_VOLATILE_SIZE 0x1000 @@ -42,6 +56,11 @@ struct vmtrr_pair vmtrr[MAX_VAR_MTRRS]; }; -void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); +void restore_mtrr(void); + +int save_s3_info(struct region nv, struct region vol); +void get_s3_info(S3_DATA_TYPE type, struct region *info); + +int spi_save_s3_info(struct region dst, struct region src); #endif /* __S3_RESUME_H__ */ -- To view, visit https://review.coreboot.org/22727 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63 Gerrit-Change-Number: 22727 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add NV storage to ramtop
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22726 Change subject: amd/stoneyridge: Add NV storage to ramtop ...................................................................... amd/stoneyridge: Add NV storage to ramtop The scratch registers in northbridge used for storing the top of cacheable memory are volatile. Add a mechanism to save and retrieve the value from the BiosRam storage in the FCH. These values remain valid until RSMRST# is asserted or S5 power is lost. The accesses to the FCH are substantially slower than the northbridge, however, so continue using the volatile copy when determining cbmem_top. Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/ramtop.c 2 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/22726/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 1b41292..b46c60b 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -46,6 +46,7 @@ bootblock-y += sb_util.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c +bootblock-y += sb_util.c romstage-y += BiosCallOuts.c romstage-y += romstage.c @@ -71,6 +72,7 @@ postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += ramtop.c +postcar-y += sb_util.c ramstage-y += BiosCallOuts.c ramstage-y += chip.c diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 8268477..5681691 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -22,20 +22,32 @@ #include <cpu/amd/mtrr.h> #include <cbmem.h> #include <soc/northbridge.h> +#include <soc/southbridge.h> #define CBMEM_TOP_SCRATCHPAD 0x78 +#define CBMEM_TOP_BIOSRAM 0xf0 void backup_top_of_low_cacheable(uintptr_t ramtop) { + /* save a volatile copy */ uint16_t top_cache = ramtop >> 16; pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); + + /* and a much slower to access NV copy */ + biosram_write32(CBMEM_TOP_BIOSRAM, ramtop); } uintptr_t restore_top_of_low_cacheable(void) { - uint16_t top_cache; + uintptr_t top_cache; top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); - return (top_cache << 16); + if (top_cache) + return (top_cache << 16); + + /* top_cache == 0 means we lost our volatile copy. Restore it now. */ + top_cache = biosram_read32(CBMEM_TOP_BIOSRAM); + backup_top_of_low_cacheable(top_cache); + return top_cache; } void *cbmem_top(void) -- To view, visit https://review.coreboot.org/22726 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30 Gerrit-Change-Number: 22726 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Remove unused S3 NVRAM save/restore
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22725 Change subject: amd/stoneyridge: Remove unused S3 NVRAM save/restore ...................................................................... amd/stoneyridge: Remove unused S3 NVRAM save/restore Remove the BiosRam read and write functions that were brought over from the hudson source. The functionality will be superseded later with new general-purpose functions. Change-Id: Ib80c66b838fdbdd388a392b4fedaac36bf0bbb0c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 0 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/22725/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index bdd5895..afe8e3c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -311,8 +311,6 @@ void biosram_write32(uint8_t offset, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); uint16_t pm_acpi_pm_evt_blk(void); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); void bootblock_fch_early_init(void); #endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 5010e9b..49a69e1 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -245,37 +245,6 @@ sb_lpc_decode(); } -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - int i; - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", - dword, size, nvram_pos); - - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } - - return nvram_pos; -} - -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - u32 data = *old_dword; - int i; - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i * 8); - nvram_pos++; - } - *old_dword = data; - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", - *old_dword, size, nvram_pos-size); - return nvram_pos; -} - void sb_enable(device_t dev) { printk(BIOS_DEBUG, "%s\n", __func__); -- To view, visit https://review.coreboot.org/22725 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib80c66b838fdbdd388a392b4fedaac36bf0bbb0c Gerrit-Change-Number: 22725 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add BIOS RAM R/W functions
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22724 Change subject: amd/stoneyridge: Add BIOS RAM R/W functions ...................................................................... amd/stoneyridge: Add BIOS RAM R/W functions The internal FCH contains 256 bytes of "BiosRam" that maintains its state until RSMRST# is asserted or standby power is lost. Add functions to support read and write operations. Change-Id: I2ddf58a63e69b2775de9a8163534b13dad2ea2fe Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c 2 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/22724/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index c7d0dda..bdd5895 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -303,6 +303,12 @@ void smi_write8(uint8_t offset, uint8_t value); void smi_write16(uint8_t offset, uint16_t value); void smi_write32(uint8_t offset, uint32_t value); +uint8_t biosram_read8(uint8_t offset); +void biosram_write8(uint8_t offset, uint8_t value); +uint32_t biosram_read16(uint8_t offset); +void biosram_write16(uint8_t offset, uint16_t value); +uint32_t biosram_read32(uint8_t offset); +void biosram_write32(uint8_t offset, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); uint16_t pm_acpi_pm_evt_blk(void); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 36dccaa..0774eae 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -71,11 +71,60 @@ return read8((void *)(APU_SMI_BASE + offset)); } + void smi_write8(uint8_t offset, uint8_t value) { write8((void *)(APU_SMI_BASE + offset), value); } +uint8_t biosram_read8(uint8_t offset) +{ + outb(offset, BIOSRAM_INDEX); + return inb(BIOSRAM_DATA); +} + +void biosram_write8(uint8_t offset, uint8_t value) +{ + outb(offset, BIOSRAM_INDEX); + outb(value, BIOSRAM_DATA); +} + +uint32_t biosram_read16(uint8_t offset) +{ + int i; + uint32_t value = 0; + for (i = 1 ; i >= 0 ; i--) + value = (value << 8) | biosram_read8(offset + i); + return value; +} + +uint32_t biosram_read32(uint8_t offset) +{ + int i; + uint32_t value = 0; + for (i = 3 ; i >= 0 ; i--) + value = (value << 8) | biosram_read8(offset + i); + return value; +} + +void biosram_write16(uint8_t offset, uint16_t value) +{ + int i; + for (i = 0 ; i < 2 ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + +void biosram_write32(uint8_t offset, uint32_t value) +{ + int i; + for (i = 0 ; i < 4 ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + uint16_t pm_acpi_pm_cnt_blk(void) { return pm_read16(PM1_CNT_BLK); -- To view, visit https://review.coreboot.org/22724 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2ddf58a63e69b2775de9a8163534b13dad2ea2fe Gerrit-Change-Number: 22724 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Move SB index/data pairs to iomap.h
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22723 Change subject: amd/stoneyridge: Move SB index/data pairs to iomap.h ...................................................................... amd/stoneyridge: Move SB index/data pairs to iomap.h Relocate the I/O registers to the iomap for PM, PM2, and BIOSRAM. Change-Id: I3a59adc974a8a90bfc586188b829a7252356b3cb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 2 files changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/22723/1 diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 53eb712..d7b94c4 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -45,6 +45,12 @@ #define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ #define SMB_BASE_ADDR 0xb00 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) #define SYS_RESET 0xcf9 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index d911472..c7d0dda 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -30,14 +30,7 @@ #define PSP_BAR_ENABLES 0x48 #define PSP_MAILBOX_BAR_EN 0x10 -/* Power management index/data registers */ -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 -#define PM2_INDEX 0xcd0 -#define PM2_DATA 0xcd1 - +/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) #define FORCE_STPCLK_RETRY BIT(24) -- To view, visit https://review.coreboot.org/22723 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3a59adc974a8a90bfc586188b829a7252356b3cb Gerrit-Change-Number: 22723 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyrige: Move acpi_get_sleep_type to sb_util
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22722 Change subject: amd/stoneyrige: Move acpi_get_sleep_type to sb_util ...................................................................... amd/stoneyrige: Move acpi_get_sleep_type to sb_util Relocate the acpi_get_sleep_type() function out of the southbridge ramstage file. This will make it more convenient for using elsewhere. Change-Id: Id7ba709bb867fb00ed6c7fa7526de087a3b9b3ca Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/22722/1 diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index f7c6b45..36dccaa 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <soc/southbridge.h> void pm_write8(u8 reg, u8 value) @@ -84,3 +85,8 @@ { return pm_read16(PM_EVT_BLK); } + +int acpi_get_sleep_type(void) +{ + return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk())); +} diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index dbf27bc..5010e9b 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <arch/io.h> -#include <arch/acpi.h> #include <bootstate.h> #include <cpu/x86/smm.h> #include <device/device.h> @@ -275,11 +274,6 @@ printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, nvram_pos-size); return nvram_pos; -} - -int acpi_get_sleep_type(void) -{ - return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk())); } void sb_enable(device_t dev) -- To view, visit https://review.coreboot.org/22722 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id7ba709bb867fb00ed6c7fa7526de087a3b9b3ca Gerrit-Change-Number: 22722 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Make GetHeapBase non-static
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22721 Change subject: soc/amd/common: Make GetHeapBase non-static ...................................................................... soc/amd/common: Make GetHeapBase non-static The cbmem location holding the heap will be used to store additional information in subsequent patches. Remove the static designation from GetHeapBase. Change-Id: Ic607432fd6500ef69b5d47793896cf12a699d8b7 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/agesawrapper.h M src/soc/amd/common/heapmanager.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/22721/1 diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h index 6ddc658..a000328 100644 --- a/src/soc/amd/common/agesawrapper.h +++ b/src/soc/amd/common/agesawrapper.h @@ -55,4 +55,6 @@ void OemPostParams(AMD_POST_PARAMS *PostParams); void SetMemParams(AMD_POST_PARAMS *PostParams); +void *GetHeapBase(void); + #endif /* __AGESAWRAPPER_H__ */ diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/heapmanager.c index 22d95f0..f679648 100644 --- a/src/soc/amd/common/heapmanager.c +++ b/src/soc/amd/common/heapmanager.c @@ -19,7 +19,7 @@ #include <cbmem.h> #include <string.h> -static void *GetHeapBase(void) +void *GetHeapBase(void) { struct cbmem_usage *heap; heap = (struct cbmem_usage *)cbmem_add(CBMEM_ID_RESUME_SCRATCH, -- To view, visit https://review.coreboot.org/22721 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic607432fd6500ef69b5d47793896cf12a699d8b7 Gerrit-Change-Number: 22721 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Define MTRR structures for S3 save
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22719 Change subject: amd/stoneyridge: Define MTRR structures for S3 save ...................................................................... amd/stoneyridge: Define MTRR structures for S3 save In subsequent S3 patches, MTRR settings will be stored in DRAM. This is a departure from other examples of AMD support, including the binaryPI S3 support that was stripped out earlier. Create structures to simplify saving and restoring the MTRR settings. Change-Id: I33a0be676d44baf53f57cc27244ea1faf06e3bdd Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/s3_resume.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/22719/1 diff --git a/src/soc/amd/common/s3_resume.h b/src/soc/amd/common/s3_resume.h index 39a0712..3e80d72 100644 --- a/src/soc/amd/common/s3_resume.h +++ b/src/soc/amd/common/s3_resume.h @@ -16,6 +16,30 @@ #ifndef __S3_RESUME_H__ #define __S3_RESUME_H__ +#include <cpu/x86/msr.h> + +struct vmtrr_pair { + msr_t base; + msr_t mask; +}; + +#define MAX_VAR_MTRRS 0x20 +struct all_mtrrs { + msr_t sys_cfg; + msr_t _64k_00; + msr_t _16k_80; + msr_t _16k_a0; + msr_t _4k_c0; + msr_t _4k_c8; + msr_t _4k_d0; + msr_t _4k_d8; + msr_t _4k_e0; + msr_t _4k_e8; + msr_t _4k_f0; + msr_t _4k_f8; + struct vmtrr_pair vmtrr[MAX_VAR_MTRRS]; +}; + void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); #endif /* __S3_RESUME_H__ */ -- To view, visit https://review.coreboot.org/22719 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I33a0be676d44baf53f57cc27244ea1faf06e3bdd Gerrit-Change-Number: 22719 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Define regions in AGESA cbmem
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22720 Change subject: soc/amd/common: Define regions in AGESA cbmem ...................................................................... soc/amd/common: Define regions in AGESA cbmem In 6c747068 "amd/stoneyridge: Put AGESA heap into cbmem" the AGESA heap was moved completely into cbmem. This was a departure from the "late cbmem init" method of adding it late in post, then storing the S3 volatile data to the region. To prepare for S3 support, split the region into subregions for heap, AGESA's S3 volatile storage, and an MTRR save area. Change-Id: I06c137f56516f3a04091d1191cd657a0aa07320b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/BiosCallOuts.h M src/soc/amd/common/heapmanager.c M src/soc/amd/common/s3_resume.h 3 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/22720/1 diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/BiosCallOuts.h index 5237d52..53fc46f 100644 --- a/src/soc/amd/common/BiosCallOuts.h +++ b/src/soc/amd/common/BiosCallOuts.h @@ -17,12 +17,20 @@ #ifndef __CALLOUTS_AMD_AGESA_H__ #define __CALLOUTS_AMD_AGESA_H__ +#include "s3_resume.h" #include "agesawrapper.h" -#define BIOS_HEAP_START_ADDRESS 0x010000000 #define BIOS_HEAP_SIZE 0x30000 #define BSP_STACK_BASE_ADDR 0x30000 +struct cbmem_usage { + uint8_t heap_base[BIOS_HEAP_SIZE]; +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + uint8_t s3_vol_data[S3_VOLATILE_SIZE]; + struct all_mtrrs s3_mtrrs; +#endif +}; + typedef struct _BIOS_HEAP_MANAGER { UINT32 StartOfAllocatedNodes; UINT32 StartOfFreedNodes; diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/heapmanager.c index b991514..22d95f0 100644 --- a/src/soc/amd/common/heapmanager.c +++ b/src/soc/amd/common/heapmanager.c @@ -21,7 +21,10 @@ static void *GetHeapBase(void) { - return cbmem_add(CBMEM_ID_RESUME_SCRATCH, BIOS_HEAP_SIZE); + struct cbmem_usage *heap; + heap = (struct cbmem_usage *)cbmem_add(CBMEM_ID_RESUME_SCRATCH, + sizeof(struct cbmem_usage)); + return (void *)heap->heap_base; } static void EmptyHeap(int unused) diff --git a/src/soc/amd/common/s3_resume.h b/src/soc/amd/common/s3_resume.h index 3e80d72..8dc60da 100644 --- a/src/soc/amd/common/s3_resume.h +++ b/src/soc/amd/common/s3_resume.h @@ -18,6 +18,8 @@ #include <cpu/x86/msr.h> +#define S3_VOLATILE_SIZE 0x1000 + struct vmtrr_pair { msr_t base; msr_t mask; -- To view, visit https://review.coreboot.org/22720 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I06c137f56516f3a04091d1191cd657a0aa07320b Gerrit-Change-Number: 22720 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Add S3 region to Kconfig
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22717 Change subject: soc/amd/common: Add S3 region to Kconfig ...................................................................... soc/amd/common: Add S3 region to Kconfig Add default values for the S3 position and size symbols to Kconfig. These are already defined by AMD platforms and this patch gives them non-zero values when soc/amd/common is used. The primary choice for the S3 save location will be determined by the FMAP. These values will form the "backup" region for storing S3 data when no FMAP file is specified. The values are typical for all AMD platforms and should allow adequate room for rotation (the Stoney Ridge NV size is 0x4c1 currently). Change-Id: I0cc8c6a9dbf0e76d41e94d535c6afd9b93f2eb32 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/Kconfig 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/22717/1 diff --git a/src/soc/amd/common/Kconfig b/src/soc/amd/common/Kconfig index debedac..33713f9 100644 --- a/src/soc/amd/common/Kconfig +++ b/src/soc/amd/common/Kconfig @@ -11,4 +11,24 @@ source "src/soc/amd/common/block/Kconfig" +config S3_DATA_POS + hex + depends on HAVE_ACPI_RESUME + default 0xffff0000 + help + For designs not using a flash map, this is the physical address where + S3 resume data is stored in the SPI flash. Place this on a 4KB + boundary for best results. The designer must ensure the region does + not interfere with anything else in the image. + +config S3_DATA_SIZE + int + depends on HAVE_ACPI_RESUME + default 32768 + help + For designs not using a flash map, this is the total size of the + region to be used for S3 resume data in the SPI flash. Make this + a multiple of 4KB for best results. The designer must ensure the + region does not interfere with anything else in the image. + endif # SOC_AMD_COMMON -- To view, visit https://review.coreboot.org/22717 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0cc8c6a9dbf0e76d41e94d535c6afd9b93f2eb32 Gerrit-Change-Number: 22717 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit December 2017