coreboot-gerrit December 2017

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Change in coreboot[master]: soc/amd/common: Define regions in AGESA cbmem
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22720 ) Change subject: soc/amd/common: Define regions in AGESA cbmem ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64096/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18930/ : SUCCESS -- To view, visit https://review.coreboot.org/22720 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06c137f56516f3a04091d1191cd657a0aa07320b Gerrit-Change-Number: 22720 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 17:22:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Skip VGA initialization on S3 resume
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22718 ) Change subject: amd/stoneyridge: Skip VGA initialization on S3 resume ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64094/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18928/ : SUCCESS -- To view, visit https://review.coreboot.org/22718 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I222cc7fcf5e58f451cee9621a1b876346226af09 Gerrit-Change-Number: 22718 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 17:20:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/common: Rename spi.c and add prototype
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22716 ) Change subject: soc/amd/common: Rename spi.c and add prototype ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64093/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18926/ : SUCCESS -- To view, visit https://review.coreboot.org/22716 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6545ac1c0a04202af63be269d88c091121358bc9 Gerrit-Change-Number: 22716 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 17:17:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/common: Add S3 region to Kconfig
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22717 ) Change subject: soc/amd/common: Add S3 region to Kconfig ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64091/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18925/ : SUCCESS -- To view, visit https://review.coreboot.org/22717 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0cc8c6a9dbf0e76d41e94d535c6afd9b93f2eb32 Gerrit-Change-Number: 22717 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 17:15:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Select fanless SMU firmware
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22251 ) Change subject: google/kahlee: Select fanless SMU firmware ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64092/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18927/ : SUCCESS -- To view, visit https://review.coreboot.org/22251 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0761266f2a4026ebc251b64074c10481118734a2 Gerrit-Change-Number: 22251 Gerrit-PatchSet: 10 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 17:15:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Select HAVE_ACPI_RESUME
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22732 Change subject: google/kahlee: Select HAVE_ACPI_RESUME ...................................................................... google/kahlee: Select HAVE_ACPI_RESUME Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/kahlee/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/22732/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 13c949d..ed2d11c 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -33,6 +33,7 @@ select STONEYRIDGE_UART select SOC_AMD_PSP_SELECTABLE_SMU_FW select SOC_AMD_SMU_FANLESS + select HAVE_ACPI_RESUME if BOARD_GOOGLE_BASEBOARD_KAHLEE -- To view, visit https://review.coreboot.org/22732 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea Gerrit-Change-Number: 22732 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add S3 support to POST
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22731 Change subject: amd/stoneyridge: Add S3 support to POST ...................................................................... amd/stoneyridge: Add S3 support to POST Add/update the romstage and ramstage paths to check for S3 resume and call the appropriate AGESA functions. Add a call to mtrr_restore during each core's initialization. Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/model_15_init.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 65 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/22731/1 diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 8e4ab2e..06d50c0 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -20,6 +20,7 @@ #include <cpu/cpu.h> #include <device/device.h> #include <device/pci.h> +#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/southbridge.h> @@ -81,12 +82,20 @@ static void earliest_ramstage(void *unused) { - post_code(0x46); - if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); + if (!romstage_handoff_is_resume()) { + post_code(0x46); + if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) + psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); - post_code(0x47); - AGESAWRAPPER(amdinitenv); + post_code(0x47); + AGESAWRAPPER(amdinitenv); + } else { + post_code(0x46); + AGESAWRAPPER(amds3laterestore); + + post_code(0x47); + AGESAWRAPPER(fchs3earlyrestore); + } } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL); diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c index 930e395..d420e22 100644 --- a/src/soc/amd/stoneyridge/model_15_init.c +++ b/src/soc/amd/stoneyridge/model_15_init.c @@ -22,12 +22,13 @@ #include <cpu/x86/msr.h> #include <cpu/x86/pae.h> #include <pc80/mc146818rtc.h> - #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> +#include <romstage_handoff.h> #include <arch/acpi.h> +#include <s3_resume.h> static void msr_rw_dram(unsigned int reg) { @@ -69,6 +70,9 @@ msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); + if (acpi_s3_resume_allowed() && romstage_handoff_is_resume()) + restore_mtrr(); + x86_enable_cache(); /* zero the machine check error status registers */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 3eb8e8d..304030b 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -28,6 +28,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <romstage_handoff.h> #include <agesawrapper.h> #include <agesawrapper_call.h> #include <soc/northbridge.h> @@ -423,12 +424,11 @@ void domain_enable_resources(device_t dev) { - if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) + if (!romstage_handoff_is_resume()) AGESAWRAPPER(amdinitmid); + else + AGESAWRAPPER(fchs3laterestore); printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 32dee5a..25cbc39 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -15,6 +15,7 @@ */ #include <arch/cpu.h> +#include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -24,6 +25,7 @@ #include <device/device.h> #include <chip.h> #include <program_loading.h> +#include <romstage_handoff.h> #include <agesawrapper.h> #include <agesawrapper_call.h> #include <soc/northbridge.h> @@ -40,45 +42,59 @@ msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; + int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); +; int i; console_init(); - post_code(0x40); - AGESAWRAPPER(amdinitpost); + if (!s3_resume) { + post_code(0x40); + AGESAWRAPPER(amdinitpost); - post_code(0x41); - /* - * TODO: This is a hack to work around current AGESA behavior. AGESA - * needs to change to reflect that coreboot owns the MTRRs. - * - * After setting up DRAM, AGESA also completes the configuration of the - * MTRRs, setting regions to WB. Anything written to memory between - * now and and when CAR is dismantled will be in cache and lost. For - * now, set the regions UC to ensure the writes get to DRAM. - */ - for (i = 0 ; i < vmtrrs ; i++) { - base = rdmsr(MTRR_PHYS_BASE(i)); - mask = rdmsr(MTRR_PHYS_MASK(i)); - if (!(mask.lo & MTRR_PHYS_MASK_VALID)) - continue; + post_code(0x41); + /* + * TODO: This is a hack to work around current AGESA behavior. + * AGESA needs to change to reflect that coreboot owns + * the MTRRs. + * + * After setting up DRAM, AGESA also completes the configuration + * of the MTRRs, setting regions to WB. Anything written to + * memory between now and and when CAR is dismantled will be + * in cache and lost. For now, set the regions UC to ensure + * the writes get to DRAM. + */ + for (i = 0 ; i < vmtrrs ; i++) { + base = rdmsr(MTRR_PHYS_BASE(i)); + mask = rdmsr(MTRR_PHYS_MASK(i)); + if (!(mask.lo & MTRR_PHYS_MASK_VALID)) + continue; - if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { - base.lo &= ~0x7; - base.lo |= MTRR_TYPE_UNCACHEABLE; - wrmsr(MTRR_PHYS_BASE(i), base); + if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { + base.lo &= ~0x7; + base.lo |= MTRR_TYPE_UNCACHEABLE; + wrmsr(MTRR_PHYS_BASE(i), base); + } } + /* Disable WB from to region 4GB-TOM2. */ + msr_t sys_cfg = rdmsr(SYSCFG_MSR); + sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; + wrmsr(SYSCFG_MSR, sys_cfg); + } else { + printk(BIOS_INFO, "S3 detected\n"); + post_code(0x60); + AGESAWRAPPER(amdinitresume); + restore_top_of_low_cacheable(); + + post_code(0x61); } - /* Disable WB from to region 4GB-TOM2. */ - msr_t sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; - wrmsr(SYSCFG_MSR, sys_cfg); post_code(0x42); psp_notify_dram(); post_code(0x43); - cbmem_initialize_empty(); + cbmem_recovery(s3_resume); + romstage_handoff_init(s3_resume); post_code(0x44); if (postcar_frame_init(&pcf, 1 * KiB)) -- To view, visit https://review.coreboot.org/22731 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2 Gerrit-Change-Number: 22731 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: WIP soc/amd/common: Add S3 resume functions to wrapper
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22730 Change subject: WIP soc/amd/common: Add S3 resume functions to wrapper ...................................................................... WIP soc/amd/common: Add S3 resume functions to wrapper Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/agesawrapper.c 1 file changed, 146 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/22730/1 diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index 28c290b..87e1550 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -21,6 +21,7 @@ #include <cpu/x86/mtrr.h> #include <BiosCallOuts.h> #include <string.h> +#include "s3_resume.h" void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {} void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} @@ -382,6 +383,151 @@ return Status; } +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + struct region nv_data; + + if (!acpi_s3_resume_allowed()) + return AGESA_UNSUPPORTED; + + memset(&AmdParamStruct, 0, sizeof(AmdParamStruct)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + get_s3_info(S3_DATA_TYPE_NV, &nv_data); + AmdResumeParamsPtr->S3DataBlock.NvStorage = (void *)nv_data.offset; + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = nv_data.size; + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + struct region vol_data; + + if (!acpi_s3_resume_allowed()) + return AGESA_UNSUPPORTED; + + amd_initcpuio(); + + memset(&AmdS3LateParams, 0, sizeof(AmdS3LateParams)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + get_s3_info(S3_DATA_TYPE_VOLATILE, &vol_data); + AmdS3LateParamsPtr->S3DataBlock.VolatileStorage = (void *)vol_data.offset; + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = vol_data.size; + + Status = AmdS3LateRestore(AmdS3LateParamsPtr); + /* todo: debug status of UNSUPPORTED */ + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + return Status; +} + +AGESA_STATUS agesawrapper_fchs3earlyrestore(void) +{ + AGESA_STATUS status = AGESA_SUCCESS; + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + struct cbmem_usage *amd_cbmem; + + if (!acpi_s3_resume_allowed()) + return AGESA_UNSUPPORTED; + + amd_cbmem = (struct cbmem_usage *)GetHeapBase(); + if (!amd_cbmem) { + printk(BIOS_ERR, "Error locating CBMEM_ID_RESUME_SCRATCH\n"); + return AGESA_ERROR; + } + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = (uintptr_t)&amd_cbmem->heap_base; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + memset(&FchParams, 0, sizeof(FchParams)); + + FchParams.StdHeader = &StdHeader; +// todo +// see example in southbridge/amd/agesa/hudson/resume.c +// s3_resume_init_data(&FchParams); + + FchInitS3EarlyRestore(&FchParams); + + return status; +} + +AGESA_STATUS agesawrapper_fchs3laterestore(void) +{ + AGESA_STATUS status = AGESA_SUCCESS; + AMD_CONFIG_PARAMS StdHeader; + FCH_DATA_BLOCK FchParams; + struct cbmem_usage *amd_cbmem; + + if (!acpi_s3_resume_allowed()) + return AGESA_UNSUPPORTED; + + amd_cbmem = (struct cbmem_usage *)GetHeapBase(); + if (!amd_cbmem) { + printk(BIOS_ERR, "Error locating CBMEM_ID_RESUME_SCRATCH\n"); + return AGESA_ERROR; + } + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = (uintptr_t)&amd_cbmem->heap_base; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + memset(&FchParams, 0, sizeof(FchParams)); + + FchParams.StdHeader = &StdHeader; +// todo +// see example in southbridge/amd/agesa/hudson/resume.c +// s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + + // todo: still need to reload interrupt values? native agesa doesn't + // but old PI code used to. + + return status; +} + AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) { AGESA_STATUS Status; -- To view, visit https://review.coreboot.org/22730 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01 Gerrit-Change-Number: 22730 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: WIP vc/amd/pi/00670F00: Reintroduce FCH restore functions
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22729 Change subject: WIP vc/amd/pi/00670F00: Reintroduce FCH restore functions ...................................................................... WIP vc/amd/pi/00670F00: Reintroduce FCH restore functions Recover the source that had been stripped out when S3 wasn't supported. Change-Id: I08c028eadd55ac014fafdd2be71a4b9ce5598119 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/agesawrapper.h M src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/22729/1 diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h index a9ba3e6..a6983ad 100644 --- a/src/soc/amd/common/agesawrapper.h +++ b/src/soc/amd/common/agesawrapper.h @@ -52,6 +52,9 @@ VOID amd_initcpuio(void); const void *agesawrapper_locate_module(const CHAR8 name[8]); +VOID FchInitS3EarlyRestore(IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitS3LateRestore(IN FCH_DATA_BLOCK *FchDataPtr); + void OemPostParams(AMD_POST_PARAMS *PostParams); void SetMemParams(AMD_POST_PARAMS *PostParams); diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c index ec414b4..bf74df2 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c @@ -367,3 +367,33 @@ Dispatcher = module->ModuleDispatcher; return Dispatcher(AmdGetDataEye); } + +/********************************************************************** + * FCH Functions + **********************************************************************/ + +VOID +FchInitS3EarlyRestore ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + MODULE_ENTRY Dispatcher = NULL; + const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); + FchDataPtr->StdHeader->Func = FCH_INIT_S3_EARLY_RESTORE; + if (!module) return; + Dispatcher = module->ModuleDispatcher; + Dispatcher(FchDataPtr); +} + +VOID +FchInitS3LateRestore ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + MODULE_ENTRY Dispatcher = NULL; + const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); + FchDataPtr->StdHeader->Func = FCH_INIT_S3_LATE_RESTORE; + if (!module) return; + Dispatcher = module->ModuleDispatcher; + Dispatcher(FchDataPtr); +} -- To view, visit https://review.coreboot.org/22729 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I08c028eadd55ac014fafdd2be71a4b9ce5598119 Gerrit-Change-Number: 22729 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Add AmdInitRtb call
by Marshall Dawson (Code Review) 05 Dec '17

05 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22728 Change subject: soc/amd/common: Add AmdInitRtb call ...................................................................... soc/amd/common: Add AmdInitRtb call Add support for the AmdInitRtb() function which asks AGESA for the S3 save data. Change-Id: I93336ca7e85cb4eff7140d4caab92591f921304a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/agesawrapper.c M src/soc/amd/common/agesawrapper.h M src/soc/amd/common/amd_late_init.c 3 files changed, 46 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/22728/1 diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index b939183..28c290b 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include "agesawrapper.h" #include <cbfs.h> #include <cbmem.h> @@ -338,6 +339,49 @@ return Status; } +AGESA_STATUS agesawrapper_amdinitrtb(void) +{ + AGESA_STATUS Status; + AMD_RTB_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + struct region nv_data, vol_data; + + if (!acpi_s3_resume_allowed()) + return AGESA_UNSUPPORTED; + + memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_INIT_RTB; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_RTB_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdInitRtb(AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + nv_data.offset = (size_t)AmdS3SaveParamsPtr->S3DataBlock.NvStorage; + nv_data.size = (size_t)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize; + vol_data.offset = (size_t)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage; + vol_data.size = (size_t)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize; + + if (save_s3_info(nv_data, vol_data)) + printk(BIOS_ERR, "Error saving S3 data, resume is impossible\n"); + + AmdReleaseStruct(&AmdInterfaceParams); + + return Status; +} + AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) { AGESA_STATUS Status; diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h index a000328..a9ba3e6 100644 --- a/src/soc/amd/common/agesawrapper.h +++ b/src/soc/amd/common/agesawrapper.h @@ -41,7 +41,7 @@ void *agesawrapper_getlateinitptr(int pick); AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINTN Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amdinitrtb(void); AGESA_STATUS agesawrapper_amdinitresume(void); AGESA_STATUS agesawrapper_amds3laterestore(void); diff --git a/src/soc/amd/common/amd_late_init.c b/src/soc/amd/common/amd_late_init.c index 3aee23c..d57de26 100644 --- a/src/soc/amd/common/amd_late_init.c +++ b/src/soc/amd/common/amd_late_init.c @@ -27,13 +27,12 @@ { if (acpi_is_wakeup_s3()) return; - AGESAWRAPPER(amdinitlate); if (!acpi_s3_resume_allowed()) return; - AGESAWRAPPER(amdS3Save); + AGESAWRAPPER(amdinitrtb); } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, -- To view, visit https://review.coreboot.org/22728 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I93336ca7e85cb4eff7140d4caab92591f921304a Gerrit-Change-Number: 22728 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit December 2017