coreboot-gerrit December 2017

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Change in coreboot[master]: mainboard/compulab: enable SuperIO UART
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22737 ) Change subject: mainboard/compulab: enable SuperIO UART ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64126/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18957/ : SUCCESS -- To view, visit https://review.coreboot.org/22737 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567 Gerrit-Change-Number: 22737 Gerrit-PatchSet: 2 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 21:00:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/compulab: remove EC replay for Intense-PC
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22736 ) Change subject: mainboard/compulab: remove EC replay for Intense-PC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64124/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18955/ : SUCCESS -- To view, visit https://review.coreboot.org/22736 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05fb6358b40f442337f5768afa6253cd9bc32ee1 Gerrit-Change-Number: 22736 Gerrit-PatchSet: 1 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 20:53:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/compulab: enable SuperIO UART
by Hal Martin (Code Review) 05 Dec '17

05 Dec '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22737 to look at the new patch set (#2). Change subject: mainboard/compulab: enable SuperIO UART ...................................................................... mainboard/compulab: enable SuperIO UART Enable the UART via SMSC SIO1007 SuperIO, this allows you to see boot messages from coreboot over the integrated RS-232 port (requires use of included dongle). Also changed devicetree to use the correct CPU socket. Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567 Signed-off-by: Hal Martin <hal.martin(a)gmail.com> --- M src/mainboard/compulab/intense_pc/Kconfig M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/compulab/intense_pc/romstage.c 3 files changed, 54 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/22737/2 -- To view, visit https://review.coreboot.org/22737 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567 Gerrit-Change-Number: 22737 Gerrit-PatchSet: 2 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cr50: Make EC clear AP_OFF before hibnernate
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22657 ) Change subject: cr50: Make EC clear AP_OFF before hibnernate ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64123/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18954/ : SUCCESS -- To view, visit https://review.coreboot.org/22657 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba Gerrit-Change-Number: 22657 Gerrit-PatchSet: 7 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 20:51:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/compulab: enable SuperIO UART
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22737 ) Change subject: mainboard/compulab: enable SuperIO UART ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64125/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/18956/ : SUCCESS -- To view, visit https://review.coreboot.org/22737 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567 Gerrit-Change-Number: 22737 Gerrit-PatchSet: 1 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 20:49:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/compulab: enable SuperIO UART
by Hal Martin (Code Review) 05 Dec '17

05 Dec '17

Hal Martin has uploaded this change for review. ( https://review.coreboot.org/22737 Change subject: mainboard/compulab: enable SuperIO UART ...................................................................... mainboard/compulab: enable SuperIO UART Enable the UART via SMSC SIO1007 SuperIO, this allows you to see boot messages from coreboot over the integrated RS-232 port (requires use of included dongle). Also changed devicetree to use the correct CPU socket. Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567 Signed-off-by: Hal Martin <hal.martin(a)gmail.com> --- M src/mainboard/compulab/intense_pc/Kconfig M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/compulab/intense_pc/romstage.c 3 files changed, 60 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/22737/1 diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig index 283d63a..6375495 100644 --- a/src/mainboard/compulab/intense_pc/Kconfig +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -14,6 +14,7 @@ select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT + select SUPERIO_SMSC_SIO1007 config HAVE_IFD_BIN bool diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 8b1deb3..6d01892 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -28,7 +28,7 @@ register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on - chip cpu/intel/socket_rPGA989 + chip cpu/intel/socket_FCBGA1023 device lapic 0x0 on end end diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 8ef3f3e..1df8495 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -17,7 +17,9 @@ #include <lib.h> #include <arch/io.h> #include "northbridge/intel/sandybridge/raminit_native.h" +#include <superio/smsc/sio1007/chip.h> +/* void pch_enable_lpc(void) { pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); @@ -27,6 +29,33 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); +} +*/ + +#define SIO_PORT 0x164e + +void pch_enable_lpc(void) +{ + device_t dev = PCH_LPC_DEV; + + /* Set COM1/COM2 decode range */ + pci_write_config16(dev, LPC_IO_DEC, 0x0010); + + /* Enable SuperIO + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; + pci_write_config16(dev, LPC_EN, lpc_config); + + /* Map 256 bytes at 0x1600 to the LPC bus. */ + pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); + + /* Map a range for the runtime_port registers to the LPC bus. */ + pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); + + /* Enable COM1 */ + if (sio1007_enable_uart_at(SIO_PORT)) { + pci_write_config16(dev, LPC_EN, + lpc_config | COMA_LPC_EN); + } } void rcba_config(void) @@ -59,6 +88,35 @@ void mainboard_config_superio(void) { + const u16 port = SIO_PORT; + const u16 runtime_port = 0x180; + + /* Turn on configuration mode. */ + outb(0x55, port); + + /* Set the GPIO direction, polarity, and type. */ + sio1007_setreg(port, 0x31, 1 << 0, 1 << 0); + sio1007_setreg(port, 0x32, 0 << 0, 1 << 0); + sio1007_setreg(port, 0x33, 0 << 0, 1 << 0); + + /* Set the base address for the runtime register block. */ + sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff); + sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff); + + /* Turn on address decoding for it. */ + sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1); + + /* Set the value of GPIO 10 by changing GP1, bit 0. */ + u8 byte; + byte = inb(runtime_port + 0xc); + byte |= (1 << 0); + outb(byte, runtime_port + 0xc); + + /* Turn off address decoding for it. */ + sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1); + + /* Turn off configuration mode. */ + outb(0xaa, port); } void mainboard_get_spd(spd_raw_data *spd, bool id_only) -- To view, visit https://review.coreboot.org/22737 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567 Gerrit-Change-Number: 22737 Gerrit-PatchSet: 1 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com>

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Change in coreboot[master]: mainboard/compulab: remove EC replay for Intense-PC
by Hal Martin (Code Review) 05 Dec '17

05 Dec '17

Hal Martin has uploaded this change for review. ( https://review.coreboot.org/22736 Change subject: mainboard/compulab: remove EC replay for Intense-PC ...................................................................... mainboard/compulab: remove EC replay for Intense-PC coreboot console output during POST shows that the EC replay fails to communicate with the EC. Since the replay has no effect, it should be removed from the boot process. coreboot log: Replaying EC dump .......Timeout while sending command 0x81 to EC! .......Timeout while sending data 0x00 to EC! (snip) .......Timeout while sending command 0x81 to EC! .......Timeout while sending data 0xff to EC! .......Timeout while sending data 0xff to EC! done Change-Id: I05fb6358b40f442337f5768afa6253cd9bc32ee1 Signed-off-by: Hal Martin <hal.martin(a)gmail.com> --- M src/mainboard/compulab/intense_pc/mainboard.c 1 file changed, 0 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/22736/1 diff --git a/src/mainboard/compulab/intense_pc/mainboard.c b/src/mainboard/compulab/intense_pc/mainboard.c index f91e44a..f06e900 100644 --- a/src/mainboard/compulab/intense_pc/mainboard.c +++ b/src/mainboard/compulab/intense_pc/mainboard.c @@ -22,49 +22,6 @@ static void mainboard_init(device_t dev) { - /* FIXME: trim this down or remove if necessary */ - { - int i; - const u8 dmp[256] = { - /* 00 */ 0x00, 0x28, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, - /* 08 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 18 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 28 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x3c, 0x6e, - /* 30 */ 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 38 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, - /* 48 */ 0xff, 0x42, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 58 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 68 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x41, - /* 70 */ 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, - /* 78 */ 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, - /* 80 */ 0x28, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, - /* 88 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 98 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* a8 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* b8 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* c0 */ 0x00, 0x00, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - /* c8 */ 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - /* d0 */ 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - /* d8 */ 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - /* e0 */ 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - /* e8 */ 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - /* f0 */ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - /* f8 */ 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - - printk(BIOS_DEBUG, "Replaying EC dump ..."); - for (i = 0; i < 256; i++) - ec_write (i, dmp[i]); - printk(BIOS_DEBUG, "done\n"); - } pc_keyboard_init(NO_AUX_DEVICE); } -- To view, visit https://review.coreboot.org/22736 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I05fb6358b40f442337f5768afa6253cd9bc32ee1 Gerrit-Change-Number: 22736 Gerrit-PatchSet: 1 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Create new wide IO functions
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22590 ) Change subject: amd/stoneyridge: Create new wide IO functions ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64122/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18952/ : SUCCESS -- To view, visit https://review.coreboot.org/22590 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 Gerrit-Change-Number: 22590 Gerrit-PatchSet: 5 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 20:29:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cr50: Make EC clear AP_OFF before hibnernate
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22657 ) Change subject: cr50: Make EC clear AP_OFF before hibnernate ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64121/ : SUCCESS -- To view, visit https://review.coreboot.org/22657 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba Gerrit-Change-Number: 22657 Gerrit-PatchSet: 6 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 20:19:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cbfstool: Add '-p' option for padding
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22239 ) Change subject: cbfstool: Add '-p' option for padding ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64120/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18953/ : SUCCESS -- To view, visit https://review.coreboot.org/22239 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I64bc54fd10a453b4da467bc69d9590e61b0f7ead Gerrit-Change-Number: 22239 Gerrit-PatchSet: 2 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 20:05:46 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017