coreboot-gerrit December 2017

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Change in coreboot[master]: boardid: Switch from Kconfig to weak functions
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22695 ) Change subject: boardid: Switch from Kconfig to weak functions ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64132/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18962/ : SUCCESS -- To view, visit https://review.coreboot.org/22695 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Gerrit-Change-Number: 22695 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 22:13:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: libpayload: Add SKU ID coreboot table support
by Julius Werner (Code Review) 05 Dec '17

05 Dec '17

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/22743 Change subject: libpayload: Add SKU ID coreboot table support ...................................................................... libpayload: Add SKU ID coreboot table support This patch adds support to read the SKU ID entry from the coreboot table that was recently added in coreboot. Change-Id: I1c3b375da6119a4f8e8e7e25a11644becb90f927 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/22743/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 5bc56d0..6b6d1b4 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -239,6 +239,7 @@ #define CB_TAG_BOARD_ID 0x0025 #define CB_TAG_RAM_CODE 0x0028 +#define CB_TAG_SKU_ID 0x002d struct cb_strapping_id { uint32_t tag; uint32_t size; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index b46d4b1..f221a15 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -112,6 +112,7 @@ #define UNDEFINED_STRAPPING_ID (~0) u32 board_id; u32 ram_code; + u32 sku_id; void *wifi_calibration; uint64_t ramoops_buffer; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 1efde9a..d831b96 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -157,6 +157,12 @@ info->ram_code = ram_code->id_code; } +static void cb_parse_sku_id(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_strapping_id *const sku_id = (struct cb_strapping_id *)ptr; + info->sku_id = sku_id->id_code; +} + #if IS_ENABLED(CONFIG_LP_NVRAM) static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { @@ -280,6 +286,7 @@ /* Initialize IDs as undefined in case they don't show up in table. */ info->board_id = UNDEFINED_STRAPPING_ID; info->ram_code = UNDEFINED_STRAPPING_ID; + info->sku_id = UNDEFINED_STRAPPING_ID; /* Now, walk the tables. */ ptr += header->header_bytes; @@ -380,6 +387,9 @@ case CB_TAG_RAM_CODE: cb_parse_ram_code(ptr, info); break; + case CB_TAG_SKU_ID: + cb_parse_sku_id(ptr, info); + break; case CB_TAG_WIFI_CALIBRATION: cb_parse_wifi_calibration(ptr, info); break; -- To view, visit https://review.coreboot.org/22743 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1c3b375da6119a4f8e8e7e25a11644becb90f927 Gerrit-Change-Number: 22743 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: libpayload: Minor board ID / RAM code cleanups
by Julius Werner (Code Review) 05 Dec '17

05 Dec '17

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/22742 Change subject: libpayload: Minor board ID / RAM code cleanups ...................................................................... libpayload: Minor board ID / RAM code cleanups This patch mirrors recent cleanups in coreboot regarding the strapping ID entries in the coreboot table. Change-Id: Ia5c3728daf2cb317f8e2bc72c6f1714d6cb4d080 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c 3 files changed, 14 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/22742/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 842f206..5bc56d0 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -225,14 +225,6 @@ uint64_t cbmem_tab; }; -#define CB_TAG_BOARD_ID 0x0025 -struct cb_board_id { - uint32_t tag; - uint32_t size; - /* Board ID as retrieved from the board revision GPIOs. */ - uint32_t board_id; -}; - #define CB_TAG_X86_ROM_MTRR 0x0021 struct cb_x86_rom_mtrr { uint32_t tag; @@ -244,11 +236,13 @@ uint32_t index; }; + +#define CB_TAG_BOARD_ID 0x0025 #define CB_TAG_RAM_CODE 0x0028 -struct cb_ram_code { +struct cb_strapping_id { uint32_t tag; uint32_t size; - uint32_t ram_code; + uint32_t id_code; }; #define CB_TAG_SPI_FLASH 0x0029 diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 2e5a837..b46d4b1 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -108,8 +108,11 @@ void *cbmem_cons; void *mrc_cache; void *acpi_gnvs; + +#define UNDEFINED_STRAPPING_ID (~0) u32 board_id; u32 ram_code; + void *wifi_calibration; uint64_t ramoops_buffer; uint32_t ramoops_buffer_size; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 10b801c..1efde9a 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -147,14 +147,14 @@ static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_board_id *const cbbid = (struct cb_board_id *)ptr; - info->board_id = cbbid->board_id; + struct cb_strapping_id *const cbbid = (struct cb_strapping_id *)ptr; + info->board_id = cbbid->id_code; } static void cb_parse_ram_code(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_ram_code *const ram_code = (struct cb_ram_code *)ptr; - info->ram_code = ram_code->ram_code; + struct cb_strapping_id *const ram_code = (struct cb_strapping_id *)ptr; + info->ram_code = ram_code->id_code; } #if IS_ENABLED(CONFIG_LP_NVRAM) @@ -277,13 +277,9 @@ info->header = header; - /* - * Board straps represented by numerical values are small numbers. - * Preset them to an invalid value in case the firmware does not - * supply the info. - */ - info->board_id = ~0; - info->ram_code = ~0; + /* Initialize IDs as undefined in case they don't show up in table. */ + info->board_id = UNDEFINED_STRAPPING_ID; + info->ram_code = UNDEFINED_STRAPPING_ID; /* Now, walk the tables. */ ptr += header->header_bytes; -- To view, visit https://review.coreboot.org/22742 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia5c3728daf2cb317f8e2bc72c6f1714d6cb4d080 Gerrit-Change-Number: 22742 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: boardid: Minor clean up and standardization
by Julius Werner (Code Review) 05 Dec '17

05 Dec '17

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/22741 Change subject: boardid: Minor clean up and standardization ...................................................................... boardid: Minor clean up and standardization Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/intel/fsp1_1/romstage.c M src/ec/google/chromeec/ec_boardid.c M src/include/boardid.h M src/lib/coreboot_table.c M src/mainboard/amd/bettong/boardid.c M src/mainboard/google/foster/boardid.c M src/mainboard/google/gale/boardid.c M src/mainboard/google/gru/boardid.c M src/mainboard/google/kahlee/boardid.c M src/mainboard/google/nyan/boardid.c M src/mainboard/google/nyan_big/boardid.c M src/mainboard/google/nyan_blaze/boardid.c M src/mainboard/google/oak/boardid.c M src/mainboard/google/purin/boardid.c M src/mainboard/google/smaug/boardid.c M src/mainboard/google/storm/boardid.c M src/mainboard/google/urara/boardid.c M src/mainboard/google/veyron/boardid.c M src/mainboard/google/veyron_mickey/boardid.c M src/mainboard/google/veyron_rialto/boardid.c M src/mainboard/google/zoombini/boardid.c M src/mainboard/intel/glkrvp/boardid.c 23 files changed, 41 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/22741/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 4b3f787..feee172 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -289,18 +289,12 @@ }; #define LB_TAG_BOARD_ID 0x0025 -struct lb_board_id { - uint32_t tag; - uint32_t size; - /* Board ID as retrieved from the board revision GPIOs. */ - uint32_t board_id; -}; - #define LB_TAG_RAM_CODE 0x0028 -struct lb_ram_code { + +struct lb_strapping_id { uint32_t tag; uint32_t size; - uint32_t ram_code; + uint32_t id_code; }; #define LB_TAG_SPI_FLASH 0x0029 diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index d79bc2f..e6dec25 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -20,7 +20,6 @@ #include <arch/cbfs.h> #include <arch/early_variables.h> #include <assert.h> -#include <boardid.h> #include <console/console.h> #include <cbmem.h> #include <cpu/intel/microcode.h> @@ -73,13 +72,6 @@ /* Get power state */ params.power_state = fill_power_state(); - - /* - * Read and print board version. Done after SOC romstage - * in case PCH needs to be configured to talk to the EC. - */ - if (IS_ENABLED(CONFIG_BOARD_ID_AUTO)) - printk(BIOS_INFO, "MLB: board version %d\n", board_id()); /* Call into mainboard. */ mainboard_romstage_entry(&params); diff --git a/src/ec/google/chromeec/ec_boardid.c b/src/ec/google/chromeec/ec_boardid.c index 440a5a9..9ec058d 100644 --- a/src/ec/google/chromeec/ec_boardid.c +++ b/src/ec/google/chromeec/ec_boardid.c @@ -16,7 +16,7 @@ #include <boardid.h> #include <ec/google/chromeec/ec.h> -uint8_t board_id(void) +uint32_t board_id(void) { MAYBE_STATIC int id = -1; diff --git a/src/include/boardid.h b/src/include/boardid.h index 121d052..4324a72 100644 --- a/src/include/boardid.h +++ b/src/include/boardid.h @@ -18,7 +18,9 @@ #include <stdint.h> -uint8_t board_id(void); +#define UNDEFINED_STRAPPING_ID (~0) + +uint32_t board_id(void); uint32_t ram_code(void); #endif /* __INCLUDE_BOARDID_H__ */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 29dd53a..571d1ba 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -247,13 +247,16 @@ static void lb_board_id(struct lb_header *header) { #if IS_ENABLED(CONFIG_BOARD_ID_AUTO) - struct lb_board_id *bid; + struct lb_strapping_id *rec; + uint32_t bid = board_id(); - bid = (struct lb_board_id *)lb_new_record(header); + rec = (struct lb_strapping_id *)lb_new_record(header); - bid->tag = LB_TAG_BOARD_ID; - bid->size = sizeof(*bid); - bid->board_id = board_id(); + rec->tag = LB_TAG_BOARD_ID; + rec->size = sizeof(*rec); + rec->id_code = bid; + + printk(BIOS_INFO, "Board ID: %d\n", bid); #endif } @@ -289,13 +292,16 @@ static void lb_ram_code(struct lb_header *header) { #if IS_ENABLED(CONFIG_RAM_CODE_SUPPORT) - struct lb_ram_code *code; + struct lb_strapping_id *rec; + uint32_t code = ram_code(); - code = (struct lb_ram_code *)lb_new_record(header); + rec = (struct lb_strapping_id *)lb_new_record(header); - code->tag = LB_TAG_RAM_CODE; - code->size = sizeof(*code); - code->ram_code = ram_code(); + rec->tag = LB_TAG_RAM_CODE; + rec->size = sizeof(*rec); + rec->id_code = code; + + printk(BIOS_INFO, "RAM code: %d\n", code); #endif } diff --git a/src/mainboard/amd/bettong/boardid.c b/src/mainboard/amd/bettong/boardid.c index 4b2dceb..a78f9f6 100644 --- a/src/mainboard/amd/bettong/boardid.c +++ b/src/mainboard/amd/bettong/boardid.c @@ -28,7 +28,7 @@ * ...... * 1 1 1 H */ -uint8_t board_id(void) +uint32_t board_id(void) { void *gpiommioaddr; u8 value = 0; diff --git a/src/mainboard/google/foster/boardid.c b/src/mainboard/google/foster/boardid.c index 7e99e2a..ff58695 100644 --- a/src/mainboard/google/foster/boardid.c +++ b/src/mainboard/google/foster/boardid.c @@ -18,7 +18,7 @@ #include <console/console.h> #include <gpio.h> -uint8_t board_id(void) +uint32_t board_id(void) { return 0; } diff --git a/src/mainboard/google/gale/boardid.c b/src/mainboard/google/gale/boardid.c index c8d42a9..96fc936 100644 --- a/src/mainboard/google/gale/boardid.c +++ b/src/mainboard/google/gale/boardid.c @@ -37,7 +37,7 @@ return bid; } -uint8_t board_id(void) +uint32_t board_id(void) { if (board_id_value < 0) board_id_value = get_board_id(); diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index 683ac39..8158124 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -66,7 +66,7 @@ die("Read impossible value ( > 1023) from 10-bit ADC!"); } -uint8_t board_id(void) +uint32_t board_id(void) { return get_index(1, &cached_board_id); } diff --git a/src/mainboard/google/kahlee/boardid.c b/src/mainboard/google/kahlee/boardid.c index 5b59f32..d40514d 100644 --- a/src/mainboard/google/kahlee/boardid.c +++ b/src/mainboard/google/kahlee/boardid.c @@ -19,7 +19,7 @@ #include <variant/gpio.h> #include <baseboard/variants.h> -uint8_t board_id(void) +uint32_t board_id(void) { MAYBE_STATIC int id = -1; diff --git a/src/mainboard/google/nyan/boardid.c b/src/mainboard/google/nyan/boardid.c index e833d90..57b75da 100644 --- a/src/mainboard/google/nyan/boardid.c +++ b/src/mainboard/google/nyan/boardid.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <gpio.h> -uint8_t board_id(void) +uint32_t board_id(void) { static int id = -1; diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index ac361e2..2a2911c 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -18,7 +18,7 @@ #include <gpio.h> #include <stdlib.h> -uint8_t board_id(void) +uint32_t board_id(void) { static int id = -1; gpio_t gpio[] = {[3] = GPIO(X4), [2] = GPIO(X1), /* X4 is MSB */ diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index ac361e2..2a2911c 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -18,7 +18,7 @@ #include <gpio.h> #include <stdlib.h> -uint8_t board_id(void) +uint32_t board_id(void) { static int id = -1; gpio_t gpio[] = {[3] = GPIO(X4), [2] = GPIO(X1), /* X4 is MSB */ diff --git a/src/mainboard/google/oak/boardid.c b/src/mainboard/google/oak/boardid.c index 1136f46..91e2df3 100644 --- a/src/mainboard/google/oak/boardid.c +++ b/src/mainboard/google/oak/boardid.c @@ -34,7 +34,7 @@ return bid; } -uint8_t board_id(void) +uint32_t board_id(void) { if (board_id_value < 0) board_id_value = get_board_id(); diff --git a/src/mainboard/google/purin/boardid.c b/src/mainboard/google/purin/boardid.c index f54d6af..901d837 100644 --- a/src/mainboard/google/purin/boardid.c +++ b/src/mainboard/google/purin/boardid.c @@ -15,7 +15,7 @@ #include <boardid.h> -uint8_t board_id(void) +uint32_t board_id(void) { return -1; } diff --git a/src/mainboard/google/smaug/boardid.c b/src/mainboard/google/smaug/boardid.c index 265e75a..208a045 100644 --- a/src/mainboard/google/smaug/boardid.c +++ b/src/mainboard/google/smaug/boardid.c @@ -20,7 +20,7 @@ #include "gpio.h" -uint8_t board_id(void) +uint32_t board_id(void) { static int id = -1; diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 295550f..87f6d2a 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -48,7 +48,7 @@ return bid; } -uint8_t board_id(void) +uint32_t board_id(void) { if (board_id_value < 0) board_id_value = get_board_id(); diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c index 5923d34..9a6b64e 100644 --- a/src/mainboard/google/urara/boardid.c +++ b/src/mainboard/google/urara/boardid.c @@ -89,7 +89,7 @@ return 0; } -uint8_t board_id(void) +uint32_t board_id(void) { if (cached_board_id == -1) cached_board_id = retrieve_board_id(); diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c index 8bd1d76..604b399 100644 --- a/src/mainboard/google/veyron/boardid.c +++ b/src/mainboard/google/veyron/boardid.c @@ -18,7 +18,7 @@ #include <gpio.h> #include <stdlib.h> -uint8_t board_id(void) +uint32_t board_id(void) { static int id = -1; gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c index 47e946e..3833dbe 100644 --- a/src/mainboard/google/veyron_mickey/boardid.c +++ b/src/mainboard/google/veyron_mickey/boardid.c @@ -18,7 +18,7 @@ #include <gpio.h> #include <stdlib.h> -uint8_t board_id(void) +uint32_t board_id(void) { static int id = -1; gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c index 47e946e..3833dbe 100644 --- a/src/mainboard/google/veyron_rialto/boardid.c +++ b/src/mainboard/google/veyron_rialto/boardid.c @@ -18,7 +18,7 @@ #include <gpio.h> #include <stdlib.h> -uint8_t board_id(void) +uint32_t board_id(void) { static int id = -1; gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), diff --git a/src/mainboard/google/zoombini/boardid.c b/src/mainboard/google/zoombini/boardid.c index bd9afde..4b05c52 100644 --- a/src/mainboard/google/zoombini/boardid.c +++ b/src/mainboard/google/zoombini/boardid.c @@ -17,7 +17,7 @@ #include <boardid.h> #include <stddef.h> -uint8_t board_id(void) +uint32_t board_id(void) { MAYBE_STATIC int id = -1; diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c index 6e2ef0b..9c5aa6d 100644 --- a/src/mainboard/intel/glkrvp/boardid.c +++ b/src/mainboard/intel/glkrvp/boardid.c @@ -23,7 +23,7 @@ #define BOARD_ID_GLK_RVP2_LP4 0x8 /* RVP2 - LP4 Socket */ #define EC_FAB_ID_CMD 0x0D /* Get the board fab ID in the lower 3 bits */ -uint8_t board_id(void) +uint32_t board_id(void) { MAYBE_STATIC int id = -1; if (id < 0) { -- To view, visit https://review.coreboot.org/22741 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Gerrit-Change-Number: 22741 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: device/pciexp_device: Set values numerically instead of as bitmask
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22740 ) Change subject: device/pciexp_device: Set values numerically instead of as bitmask ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64131/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18961/ : SUCCESS -- To view, visit https://review.coreboot.org/22740 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2 Gerrit-Change-Number: 22740 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 21:50:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/pciexp_device: Set values numerically instead of as bitmask
by Patrick Georgi (Code Review) 05 Dec '17

05 Dec '17

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/22740 Change subject: device/pciexp_device: Set values numerically instead of as bitmask ...................................................................... device/pciexp_device: Set values numerically instead of as bitmask As noted on linux-pci, we have a weird way to handling "value" and "scale" fields that are supposed to contain numerical values: we encode them as a bitfield. Instead define the two fields (offset and mask) and use numbers. Another issue, not fixed in this CL, is that we write hard-coded values while these fields really need to contain the max() of acceptable delays of the downstream devices. That way the controller can decide whether or not to enter a deeper power management state. It's noted as a TODO. Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Found-by: Bjorn Helgaas <bhelgaas(a)google.com> --- M src/device/pciexp_device.c M src/include/device/pciexp.h 2 files changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/22740/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index a177204..c020159 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -277,8 +277,14 @@ pci_update_config32(root, root_cap + 0x0c , 0xffffff04, (endp_power_on_value << 3) | (power_on_scale)); - pci_update_config32(root, root_cap + 0x08, ~0xe3ff0000, - (1 << 21) | (1 << 23) | (1 << 30)); + /* TODO: 0xa0, 2 are values that work on some chipsets but really + * should be determined dynamically by looking at downstream devices. + */ + pci_update_config32(root, root_cap + 0x08, + ~(ASPM_LTR_L12_THRESHOLD_VALUE_MASK | + ASPM_LTR_L12_THRESHOLD_SCALE_MASK), + (0xa0 << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET) | + (2 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)); pci_update_config32(root, root_cap + 0x08, ~0x1f, L1SubStateSupport); @@ -287,8 +293,11 @@ pci_update_config32(dev_t, end_cap + 0x0c , 0xffffff04, (endp_power_on_value << 3) | (power_on_scale)); - pci_update_config32(dev_t, end_cap + 0x08, ~0xe3ff0000, - (1 << 21) | (1 << 23) | (1 << 30)); + pci_update_config32(dev_t, end_cap + 0x08, + ~(ASPM_LTR_L12_THRESHOLD_VALUE_MASK | + ASPM_LTR_L12_THRESHOLD_SCALE_MASK), + (0xa0 << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET) | + (2 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)); pci_update_config32(dev_t, end_cap + 0x08, ~0x1f, L1SubStateSupport); diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index f3df1a5..e7f2120 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -9,6 +9,11 @@ PCIE_ASPM_BOTH = 3, }; +#define ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET 16 +#define ASPM_LTR_L12_THRESHOLD_VALUE_MASK (0x3ff << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET) +#define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29 +#define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET) + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); -- To view, visit https://review.coreboot.org/22740 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2 Gerrit-Change-Number: 22740 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: cbfstool: Add '-p' option for padding
by build bot (Jenkins) (Code Review) 05 Dec '17

05 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22239 ) Change subject: cbfstool: Add '-p' option for padding ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64129/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18960/ : SUCCESS -- To view, visit https://review.coreboot.org/22239 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I64bc54fd10a453b4da467bc69d9590e61b0f7ead Gerrit-Change-Number: 22239 Gerrit-PatchSet: 3 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 21:32:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Revert "crossgcc: Build libelf from elfutils 0.170"
by Nico Huber (Code Review) 05 Dec '17

05 Dec '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/22739 ) Change subject: Revert "crossgcc: Build libelf from elfutils 0.170" ...................................................................... Patch Set 1: Not tested yet. -- To view, visit https://review.coreboot.org/22739 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib2b3603de40fdb95ca8c5f7489acf034749499dd Gerrit-Change-Number: 22739 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 05 Dec 2017 21:08:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: buildgcc: Hide stderr output of getopt test
by Nico Huber (Code Review) 05 Dec '17

05 Dec '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22738 Change subject: buildgcc: Hide stderr output of getopt test ...................................................................... buildgcc: Hide stderr output of getopt test Change-Id: I03c38de3a3b88d569d629be7483eb53164cf136a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/crossgcc/buildgcc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/22738/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 780d87a..76ed1be 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -899,7 +899,7 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c # parse parameters.. try to find out whether we're running GNU getopt -getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" +getoptbrand="$(getopt -V 2>/dev/null | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. args=$(getopt -l version,help,clean,directory:,bootstrap,bootstrap-only,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:,urls,nocolor -o Vhcd:bBp:l:P:j:D:tSys:un -- "$@") -- To view, visit https://review.coreboot.org/22738 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I03c38de3a3b88d569d629be7483eb53164cf136a Gerrit-Change-Number: 22738 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: Revert "crossgcc: Build libelf from elfutils 0.170"
by Nico Huber (Code Review) 05 Dec '17

05 Dec '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22739 Change subject: Revert "crossgcc: Build libelf from elfutils 0.170" ...................................................................... Revert "crossgcc: Build libelf from elfutils 0.170" This reverts commit 4cde9a752aca6aa75c6e028d301b276a53c2a472. The version from elfutils has very different build dependencies and breaks building on many platforms. Also, we accidentally build the whole elfutils package instead of libelf only. Let's revert until somebody has the time to do it properly. Change-Id: Ib2b3603de40fdb95ca8c5f7489acf034749499dd --- M util/crossgcc/buildgcc A util/crossgcc/patches/libelf-0.8.14_64bit_detection.patch D util/crossgcc/sum/elfutils-0.170.tar.bz2.cksum A util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum 4 files changed, 34 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22739/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 76ed1be..2efe1ac 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="October 15th, 2017" -CROSSGCC_VERSION="1.50" +CROSSGCC_DATE="December 5th, 2017" +CROSSGCC_VERSION="1.51" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -38,7 +38,7 @@ GMP_VERSION=6.1.2 MPFR_VERSION=3.1.5 MPC_VERSION=1.0.3 -LIBELF_VERSION=0.170 +LIBELF_VERSION=0.8.13 GCC_VERSION=6.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.29.1 @@ -58,7 +58,7 @@ GMP_ARCHIVE="https://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz" MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz" MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" -LIBELF_ARCHIVE="https://sourceware.org/elfutils/ftp/${LIBELF_VERSION}/elfutils-${LIBELF_VER…" +LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2" BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz" GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz" @@ -82,7 +82,7 @@ GMP_DIR="gmp-${GMP_VERSION}" MPFR_DIR="mpfr-${MPFR_VERSION}" MPC_DIR="mpc-${MPC_VERSION}" -LIBELF_DIR="elfutils-${LIBELF_VERSION}" +LIBELF_DIR="libelf-${LIBELF_VERSION}" GCC_DIR="gcc-${GCC_VERSION}" BINUTILS_DIR="binutils-${BINUTILS_VERSION}" GDB_DIR="gdb-${GDB_VERSION}" diff --git a/util/crossgcc/patches/libelf-0.8.14_64bit_detection.patch b/util/crossgcc/patches/libelf-0.8.14_64bit_detection.patch new file mode 100644 index 0000000..d80d1c4 --- /dev/null +++ b/util/crossgcc/patches/libelf-0.8.14_64bit_detection.patch @@ -0,0 +1,28 @@ +libelf-0.8.13: Fix libelf 64bit detection + +Taken from crosstool-ng and and re-applied to 0.8.13 + +diff -urN libelf-0.8.13.orig/configure libelf-0.8.13/configure +--- libelf-0.8.13.orig/configure 2008-05-23 01:18:03.000000000 -0700 ++++ libelf-0.8.13/configure 2017-07-27 12:41:43.417835628 -0700 +@@ -1595,7 +1595,7 @@ + echo $ac_n "(cached) $ac_c" 1>&6 + else + if test "$cross_compiling" = yes; then +- ac_cv_sizeof_long_long=0 ++ ac_cv_sizeof_long_long=8 + else + cat > conftest.$ac_ext <<EOF + #line 1602 "configure" +diff -urN libelf-0.8.13.orig/configure.in libelf-0.8.13/configure.in +--- libelf-0.8.13.orig/configure.in 2008-05-23 01:17:56.000000000 -0700 ++++ libelf-0.8.13/configure.in 2017-07-27 12:41:43.421835676 -0700 +@@ -90,7 +90,7 @@ + AC_CHECK_SIZEOF(short,2) + AC_CHECK_SIZEOF(int,4) + AC_CHECK_SIZEOF(long,4) +-AC_CHECK_SIZEOF(long long,0) ++AC_CHECK_SIZEOF(long long,8) + # Windows port + AC_CHECK_SIZEOF(__int64, 0) + diff --git a/util/crossgcc/sum/elfutils-0.170.tar.bz2.cksum b/util/crossgcc/sum/elfutils-0.170.tar.bz2.cksum deleted file mode 100644 index a0647e0..0000000 --- a/util/crossgcc/sum/elfutils-0.170.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -aff6feac0ff69eb7b240babdf2918f640eadb032 tarballs/elfutils-0.170.tar.bz2 diff --git a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum new file mode 100644 index 0000000..daa27c6 --- /dev/null +++ b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum @@ -0,0 +1 @@ +c1d6ac5f182d19dd685c4dfd74eedbfe3992425d tarballs/libelf-0.8.13.tar.gz -- To view, visit https://review.coreboot.org/22739 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib2b3603de40fdb95ca8c5f7489acf034749499dd Gerrit-Change-Number: 22739 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit December 2017