coreboot-gerrit December 2017

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Change in coreboot[master]: mb/google/poppy: Add config option for camera ACPI support
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22702 ) Change subject: mb/google/poppy: Add config option for camera ACPI support ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64149/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18979/ : SUCCESS -- To view, visit https://review.coreboot.org/22702 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06 Gerrit-Change-Number: 22702 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 00:27:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Change POPPY_USE_* to VARIANT_HAS_*
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22701 ) Change subject: mb/google/poppy: Change POPPY_USE_* to VARIANT_HAS_* ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64148/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18978/ : SUCCESS -- To view, visit https://review.coreboot.org/22701 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6fd120a34a5b0c1f018164d5c2b60548da1d0f61 Gerrit-Change-Number: 22701 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 00:22:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/soraka: Disable SPI TPM
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22699 ) Change subject: mb/google/poppy/variants/soraka: Disable SPI TPM ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64145/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18975/ : SUCCESS -- To view, visit https://review.coreboot.org/22699 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia0554ce3a0d553631123cc2b23b6dc2f6f40a1a3 Gerrit-Change-Number: 22699 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 00:21:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Disable SPI TPM
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22698 ) Change subject: mb/google/poppy: Disable SPI TPM ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64144/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18974/ : SUCCESS -- To view, visit https://review.coreboot.org/22698 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I713e41c45e323bf13aa79412ec679c90121a52b2 Gerrit-Change-Number: 22698 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 00:17:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Introduce VARIANT_SPECIFIC_OPTIONS_*
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22700 ) Change subject: mb/google/poppy: Introduce VARIANT_SPECIFIC_OPTIONS_* ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64147/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18977/ : SUCCESS -- To view, visit https://review.coreboot.org/22700 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I15db2fdac5c9e55f9698c8a0c083d6467afae245 Gerrit-Change-Number: 22700 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 00:16:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Remove dynamic disabling of TPM
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22704 ) Change subject: mb/google/poppy: Remove dynamic disabling of TPM ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64146/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18976/ : SUCCESS -- To view, visit https://review.coreboot.org/22704 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie82825fcf7092e845583edaac9ba0d3fc9d1dd80 Gerrit-Change-Number: 22704 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 00:11:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: chromeec: Add command to override charger limit
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22624 ) Change subject: chromeec: Add command to override charger limit ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64142/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18972/ : SUCCESS -- To view, visit https://review.coreboot.org/22624 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8c6fc54e519ce13e3db82ee2cecaa96c6eb42d8a Gerrit-Change-Number: 22624 Gerrit-PatchSet: 2 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 00:05:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: Set BJ max current and voltage
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22623 ) Change subject: google/fizz: Set BJ max current and voltage ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64143/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18973/ : SUCCESS -- To view, visit https://review.coreboot.org/22623 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifebee09096e0935cc7d3e53920a251b0496d3c55 Gerrit-Change-Number: 22623 Gerrit-PatchSet: 4 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 00:05:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Add support for DDR4 memory
by Furquan Shaikh (Code Review) 06 Dec '17

06 Dec '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22745 Change subject: mb/google/poppy: Add support for DDR4 memory ...................................................................... mb/google/poppy: Add support for DDR4 memory This change updates memory SPD handling code in baseboard poppy to allow variants to define either LPDDR3 or DDR4 memory types. In addition to that, it also updates the function to print SPD info considering offsets that might be different across the two memory types. BUG=b:70188937 Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/romstage.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/poppy/variants/baseboard/memory.c M src/mainboard/google/poppy/variants/nautilus/memory.c 4 files changed, 82 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/22745/1 diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 2a6cd90..6bb4076 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -22,20 +22,52 @@ #include <fsp/soc_binding.h> -#define SPD_LEN 256 +/* Offset to identify DRAM type. */ +#define SPD_DRAM_TYPE_OFF 2 +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_DDR4 0x0c -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 +/* Length of SPD data. */ +#define SPD_LEN_LPDDR3 256 +#define SPD_LEN_DDR4 512 -static void mainboard_print_spd_info(uint8_t spd[]) +/* Fields that are common across different memory types. */ +#define SPD_DENSITY_BANKS_OFF 4 +#define SPD_ADDRESSING_OFF 5 +#define SPD_PART_LEN 18 + +/* Fields that are different depending upon memory type. */ +#define SPD_ORG_OFF_LPDDR3 7 +#define SPD_BUSW_OFF_LPDDR3 8 +#define SPD_PART_OFF_LPDDR3 128 + +#define SPD_ORG_OFF_DDR4 12 +#define SPD_BUSW_OFF_DDR4 13 +#define SPD_PART_OFF_DDR4 329 + +#define SPD_INFO(_type) \ + [MEMORY_##_type] = { \ + .str = #_type, \ + .type_code = SPD_DRAM_##_type, \ + .len = SPD_LEN_##_type, \ + .org_off = SPD_ORG_OFF_##_type, \ + .busw_off = SPD_BUSW_OFF_##_type, \ + .part_off = SPD_PART_OFF_##_type, \ + } + +static const struct dram_info { + const char *str; + uint16_t type_code; + uint16_t len; + uint16_t org_off; + uint16_t busw_off; + uint16_t part_off; +} spd_info[MEMORY_COUNT] = { + SPD_INFO(LPDDR3), + SPD_INFO(DDR4), +}; + +static void mainboard_print_spd_info(const uint8_t *spd, enum memory_type type) { const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; @@ -45,28 +77,23 @@ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; char spd_name[SPD_PART_LEN+1] = { 0 }; + const struct dram_info *info = &spd_info[type]; - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + assert (info->type_code == spd[SPD_DRAM_TYPE_OFF]); /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - return; - } + printk(BIOS_INFO, "SPD: module type is %s\n", info->str); + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS_OFF] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS_OFF] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING_OFF] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING_OFF] & 7]; + int ranks = spd_ranks[(spd[info->org_off] >> 3) & 7]; + int devw = spd_devw[spd[info->org_off] & 7]; + int busw = spd_busw[spd[info->busw_off] & 7]; /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + memcpy(spd_name, &spd[info->part_off], SPD_PART_LEN); spd_name[SPD_PART_LEN] = 0; printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); @@ -83,11 +110,12 @@ } } -static uintptr_t mainboard_get_spd_data(void) +static uintptr_t mainboard_get_spd_data(enum memory_type type) { char *spd_file; size_t spd_file_len; int spd_index; + const size_t spd_len = spd_info[type].len; spd_index = variant_memory_sku(); assert(spd_index >= 0); @@ -100,17 +128,15 @@ die("SPD data not found."); /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) + if (spd_file_len < spd_len) die("Missing SPD data."); /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); - spd_index = 1; - } + if (spd_file_len < ((spd_index + 1) * spd_len)) + die("Invalid SPD index."); - spd_index *= SPD_LEN; - mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); + spd_index *= spd_len; + mainboard_print_spd_info((uint8_t *)(spd_file + spd_index), type); return (uintptr_t)(spd_file + spd_index); } @@ -122,13 +148,19 @@ variant_memory_params(&p); - memcpy(&mem_cfg->DqByteMapCh0, p.dq_map, p.dq_map_size); - memcpy(&mem_cfg->DqsMapCpu2DramCh0, p.dqs_map, p.dqs_map_size); + assert(p.type < MEMORY_COUNT); + + if (p.dq_map && p.dq_map_size) + memcpy(&mem_cfg->DqByteMapCh0, p.dq_map, p.dq_map_size); + + if (p.dqs_map && p.dqs_map_size) + memcpy(&mem_cfg->DqsMapCpu2DramCh0, p.dqs_map, p.dqs_map_size); + memcpy(&mem_cfg->RcompResistor, p.rcomp_resistor, p.rcomp_resistor_size); memcpy(&mem_cfg->RcompTarget, p.rcomp_target, p.rcomp_target_size); - mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->MemorySpdDataLen = spd_info[p.type].len; } diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h index 62389af..c88b99a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h @@ -29,7 +29,14 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); +enum memory_type { + MEMORY_LPDDR3, + MEMORY_DDR4, + MEMORY_COUNT, +}; + struct memory_params { + enum memory_type type; const void *dq_map; size_t dq_map_size; const void *dqs_map; diff --git a/src/mainboard/google/poppy/variants/baseboard/memory.c b/src/mainboard/google/poppy/variants/baseboard/memory.c index d3f1286..8134f1a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/memory.c +++ b/src/mainboard/google/poppy/variants/baseboard/memory.c @@ -39,6 +39,7 @@ void __attribute__((weak)) variant_memory_params(struct memory_params *p) { + p->type = MEMORY_LPDDR3; p->dq_map = dq_map; p->dq_map_size = sizeof(dq_map); p->dqs_map = dqs_map; diff --git a/src/mainboard/google/poppy/variants/nautilus/memory.c b/src/mainboard/google/poppy/variants/nautilus/memory.c index 508c299..dc845bc 100644 --- a/src/mainboard/google/poppy/variants/nautilus/memory.c +++ b/src/mainboard/google/poppy/variants/nautilus/memory.c @@ -37,6 +37,7 @@ void variant_memory_params(struct memory_params *p) { + p->type = MEMORY_LPDDR3; p->dq_map = dq_map; p->dq_map_size = sizeof(dq_map); p->dqs_map = dqs_map; -- To view, visit https://review.coreboot.org/22745 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2 Gerrit-Change-Number: 22745 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: intel/dcp847ske: Add Intel NUC DCP847SKE
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22683 ) Change subject: intel/dcp847ske: Add Intel NUC DCP847SKE ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64141/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18971/ : SUCCESS -- To view, visit https://review.coreboot.org/22683 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Gerrit-Change-Number: 22683 Gerrit-PatchSet: 4 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Dec 2017 23:29:27 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017