coreboot-gerrit December 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22767 ) Change subject: soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64253/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19074/ : SUCCESS -- To view, visit https://review.coreboot.org/22767 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I420e94043145e8a5adcf8bb51239657891915d84 Gerrit-Change-Number: 22767 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 07 Dec 2017 06:52:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Remove pch_enable_dev() from SoC
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22755 ) Change subject: soc/intel/skylake: Remove pch_enable_dev() from SoC ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64252/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19073/ : SUCCESS -- To view, visit https://review.coreboot.org/22755 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1 Gerrit-Change-Number: 22755 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 07 Dec 2017 06:49:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c
by Subrata Banik (Code Review) 07 Dec '17

07 Dec '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22767 Change subject: soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c ...................................................................... soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c This patch ensures that all required information for pch/mch/igd deviceid and revision available in single stage and make use of local references. TEST=Build and boot soraka/eve Change-Id: I420e94043145e8a5adcf8bb51239657891915d84 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/include/soc/pch.h 2 files changed, 44 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/22767/1 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 7bc93e6..9bca7ac 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -46,6 +46,15 @@ }; static struct { + u16 lpcid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" }, + { PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" }, + { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, +}; + +static struct { u16 igdid; const char *name; } igd_table[] = { @@ -58,6 +67,16 @@ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, }; + +static uint8_t get_dev_revision(device_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static uint16_t get_dev_id(device_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} static void report_cpu_info(void) { @@ -120,8 +139,9 @@ static void report_mch_info(void) { int i; - u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); - u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); + device_t dev = SA_DEV_ROOT; + uint16_t mchid = get_dev_id(dev); + uint8_t mch_revision = get_dev_revision(dev); const char *mch_type = "Unknown"; for (i = 0; i < ARRAY_SIZE(mch_table); i++) { @@ -132,13 +152,31 @@ } printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", - mchid, mch_revision, mch_type); + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + int i; + device_t dev = PCH_DEV_LPC; + uint16_t lpcid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].lpcid == lpcid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + lpcid, get_dev_revision(dev), pch_type); } static void report_igd_info(void) { int i; - u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); + device_t dev = SA_DEV_IGD; + uint16_t igdid = get_dev_id(dev); const char *igd_type = "Unknown"; for (i = 0; i < ARRAY_SIZE(igd_table); i++) { @@ -148,12 +186,13 @@ } } printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", - igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); + igdid, get_dev_revision(dev), igd_type); } void report_platform_info(void) { report_cpu_info(); report_mch_info(); + report_pch_info(); report_igd_info(); } diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index 7c21dd4..53dd66a 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -28,8 +28,6 @@ #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 -u8 pch_revision(void); -u16 pch_type(void); void pch_log_state(void); void pch_uart_init(void); -- To view, visit https://review.coreboot.org/22767 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I420e94043145e8a5adcf8bb51239657891915d84 Gerrit-Change-Number: 22767 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: add SPK DMIC nhlt support
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22457 ) Change subject: mb/google/poppy/variants/nautilus: add SPK DMIC nhlt support ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64250/ : SUCCESS -- To view, visit https://review.coreboot.org/22457 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187 Gerrit-Change-Number: 22457 Gerrit-PatchSet: 9 Gerrit-Owner: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 05:46:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/nautilus: Add Maxim98357a support
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22458 ) Change subject: google/nautilus: Add Maxim98357a support ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64251/ : SUCCESS -- To view, visit https://review.coreboot.org/22458 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc Gerrit-Change-Number: 22458 Gerrit-PatchSet: 10 Gerrit-Owner: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 05:43:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/nautilus: Add Maxim98357a support
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22458 ) Change subject: google/nautilus: Add Maxim98357a support ...................................................................... Patch Set 9: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64249/ : ABORTED -- To view, visit https://review.coreboot.org/22458 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc Gerrit-Change-Number: 22458 Gerrit-PatchSet: 9 Gerrit-Owner: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 05:36:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: add SPK DMIC nhlt support
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22457 ) Change subject: mb/google/poppy/variants/nautilus: add SPK DMIC nhlt support ...................................................................... Patch Set 8: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64248/ : ABORTED -- To view, visit https://review.coreboot.org/22457 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187 Gerrit-Change-Number: 22457 Gerrit-PatchSet: 8 Gerrit-Owner: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 05:36:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [wip]mainboard/intel/cannonlake_rvp: Add support for SND_MAX98357_DA7219
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22144 ) Change subject: [wip]mainboard/intel/cannonlake_rvp: Add support for SND_MAX98357_DA7219 ...................................................................... Patch Set 12: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64246/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19071/ : SUCCESS -- To view, visit https://review.coreboot.org/22144 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If7960eb6bb441f35cbd9a8a6acc37f03e04e3b70 Gerrit-Change-Number: 22144 Gerrit-PatchSet: 12 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 03:35:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]soc/inte/cannonlake: Add audio NHLT support
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22134 ) Change subject: [WIP]soc/inte/cannonlake: Add audio NHLT support ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64247/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19072/ : SUCCESS -- To view, visit https://review.coreboot.org/22134 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie8561cc64412bef54329b317874a8fe12e0bf889 Gerrit-Change-Number: 22134 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 03:32:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]soc/inte/cannonlake: Add audio NHLT support
by Lijian Zhao (Code Review) 07 Dec '17

07 Dec '17

Hello Sathyanarayana Nujella, I'd like you to do a code review. Please visit https://review.coreboot.org/22134 to review the following change. Change subject: [WIP]soc/inte/cannonlake: Add audio NHLT support ...................................................................... [WIP]soc/inte/cannonlake: Add audio NHLT support BUG=None TEST=None Change-Id: Ie8561cc64412bef54329b317874a8fe12e0bf889 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/include/soc/nhlt.h A src/soc/intel/cannonlake/nhlt.c 4 files changed, 321 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/22134/7 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f4d524a..ec6284c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -8,6 +8,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_NHLT select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 @@ -68,6 +69,7 @@ select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select SOC_INTEL_COMMON_RESET select SSE2 @@ -113,6 +115,41 @@ hex default 0x400000 +config NHLT_DMIC_1CH_16B + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for 1 channel 16B DMIC array. + +config NHLT_DMIC_2CH_16B + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for 2 channel 16B DMIC array. + +config NHLT_DMIC_4CH_16B + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for 4 channel 16B DMIC array. + +config NHLT_MAX98357 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + +config NHLT_DA7219 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + config MAX_ROOT_PORTS int default 16 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 076e76b..31dba41 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -40,6 +40,7 @@ ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c +ramstage-y += nhlt.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c @@ -73,4 +74,32 @@ CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include +# DSP firmware settings files. +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cannonlake/nhlt-blobs +DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin +DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin +MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin +DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin + +cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B) +$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B) +$(DMIC_1CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER) +$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER) +$(MAX98357_RENDER)-type := raw + +cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-type := raw + endif diff --git a/src/soc/intel/cannonlake/include/soc/nhlt.h b/src/soc/intel/cannonlake/include/soc/nhlt.h new file mode 100644 index 0000000..10de336 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/nhlt.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CANNONLAKE_NHLT_H_ +#define _SOC_CANNONLAKE_NHLT_H_ + +#include <nhlt.h> + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +/* The following link values should be used for the hwlink parameters below. */ +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +/* Returns < 0 on error, 0 on success. */ +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink); + +#endif diff --git a/src/soc/intel/cannonlake/nhlt.c b/src/soc/intel/cannonlake/nhlt.c new file mode 100644 index 0000000..9ca54eb --- /dev/null +++ b/src/soc/intel/cannonlake/nhlt.c @@ -0,0 +1,212 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +static const struct nhlt_format_config dmic_1ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 1, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-1ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_dmic_array_config dmic_1ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED, +}; + +static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_1ch_mic_config, + .cfg_size = sizeof(dmic_1ch_mic_config), + .formats = dmic_1ch_formats, + .num_formats = ARRAY_SIZE(dmic_1ch_formats), + }, +}; + +static const struct nhlt_format_config dmic_2ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_dmic_array_config dmic_2ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_2CH_SMALL, +}; + +static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_2ch_mic_config, + .cfg_size = sizeof(dmic_2ch_mic_config), + .formats = dmic_2ch_formats, + .num_formats = ARRAY_SIZE(dmic_2ch_formats), + }, +}; + +static const struct nhlt_format_config dmic_4ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 4, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-4ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_dmic_array_config dmic_4ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED, +}; + +static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_4ch_mic_config, + .cfg_size = sizeof(dmic_4ch_mic_config), + .formats = dmic_4ch_formats, + .num_formats = ARRAY_SIZE(dmic_4ch_formats), + }, +}; + +static const struct nhlt_format_config da7219_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "dialog-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_endp_descriptor da7219_descriptors[] = { + /* Render Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = da7219_formats, + .num_formats = ARRAY_SIZE(da7219_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = da7219_formats, + .num_formats = ARRAY_SIZE(da7219_formats), + }, +}; + +static const struct nhlt_format_config max98357_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_endp_descriptor max98357_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98357_formats, + .num_formats = ARRAY_SIZE(max98357_formats), + }, +}; + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) +{ + switch (num_channels) { + case 1: + return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors, + ARRAY_SIZE(dmic_1ch_descriptors)); + case 2: + return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, + ARRAY_SIZE(dmic_2ch_descriptors)); + case 4: + return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, + ARRAY_SIZE(dmic_4ch_descriptors)); + default: + return -1; + } +} + +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, da7219_descriptors, + ARRAY_SIZE(da7219_descriptors)); +} + +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98357_descriptors, + ARRAY_SIZE(max98357_descriptors)); +} -- To view, visit https://review.coreboot.org/22134 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie8561cc64412bef54329b317874a8fe12e0bf889 Gerrit-Change-Number: 22134 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com>

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coreboot-gerrit December 2017