coreboot-gerrit December 2017

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Change in coreboot[master]: soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22767 ) Change subject: soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64260/ : SUCCESS -- To view, visit https://review.coreboot.org/22767 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I420e94043145e8a5adcf8bb51239657891915d84 Gerrit-Change-Number: 22767 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 07 Dec 2017 10:17:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Remove set_subsystem() from SoC
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22769 ) Change subject: soc/intel/skylake: Remove set_subsystem() from SoC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64259/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19079/ : SUCCESS -- To view, visit https://review.coreboot.org/22769 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iead57a286b26d532e578cfff99f412c23fd4c2fe Gerrit-Change-Number: 22769 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 10:17:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/reef: provide override GPIO table in coral
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22752 ) Change subject: mb/google/reef: provide override GPIO table in coral ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64258/ : SUCCESS -- To view, visit https://review.coreboot.org/22752 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9e0674f206426fddb3947273754774b310106334 Gerrit-Change-Number: 22752 Gerrit-PatchSet: 5 Gerrit-Owner: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Scott Collyer <scollyer(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 10:10:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Remove set_subsystem() from SoC
by Subrata Banik (Code Review) 07 Dec '17

07 Dec '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22770 Change subject: soc/intel/apollolake: Remove set_subsystem() from SoC ...................................................................... soc/intel/apollolake: Remove set_subsystem() from SoC Intel common PCI driver is handle PCI subsystem ID programming, hence no need to have an explicit soc function to do the same. TEST=PCI subsystem id is getting programming during pci enumeration. Change-Id: I3eb362ff1f3f6d5c81a0dbe854d8ecd59d5a0453 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/22770/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1e78cb1..53ffdb9 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -117,20 +117,6 @@ return NULL; } -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - else - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - (device << 16) | vendor); -} - -struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem -}; - static void pci_domain_set_resources(device_t dev) { assign_resources(dev->link_list); -- To view, visit https://review.coreboot.org/22770 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3eb362ff1f3f6d5c81a0dbe854d8ecd59d5a0453 Gerrit-Change-Number: 22770 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Remove set_subsystem() from SoC
by Subrata Banik (Code Review) 07 Dec '17

07 Dec '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22769 Change subject: soc/intel/skylake: Remove set_subsystem() from SoC ...................................................................... soc/intel/skylake: Remove set_subsystem() from SoC Intel common PCI driver is handle PCI subsystem ID programming, hence no need to have an explicit soc function to do the same. TEST=PCI subsystem id is getting programming during pci enumeration. Change-Id: Iead57a286b26d532e578cfff99f412c23fd4c2fe Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/22769/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 3e33053..fa51607 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -802,18 +802,3 @@ original->SendVrMbxCmd, params->SendVrMbxCmd); } - -static void pci_set_subsystem(device_t dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - else - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - (device << 16) | vendor); -} - -struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem -}; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 8e5cc2a..f4060b2 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -293,10 +293,6 @@ soc_irq_settings(params); } -struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_dev_set_subsystem -}; - /* Mainboard GPIO Configuration */ __attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params) { -- To view, visit https://review.coreboot.org/22769 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iead57a286b26d532e578cfff99f412c23fd4c2fe Gerrit-Change-Number: 22769 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add option to have subsystem_id in common pci...
by Subrata Banik (Code Review) 07 Dec '17

07 Dec '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22768 Change subject: soc/intel/common/block: Add option to have subsystem_id in common pci driver ...................................................................... soc/intel/common/block: Add option to have subsystem_id in common pci driver This patch ensures all Intel common PCI devices can have subsystem ID programmed alongwith PCI resource enabling (.enable_resources) as part of PCI enumeration process. TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI subsystem ID getting programmed. Example: Enabling resources... PCI: 00:00.0 subsystem <- 8086/590c PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/591e Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 17 files changed, 102 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/22768/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 77a9b63..99caef4 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -497,11 +497,16 @@ pci_dev_set_resources(dev); } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations cse_ops = { .set_resources = cse_set_resources, .read_resources = pci_dev_read_resources, .enable_resources = pci_dev_enable_resources, .init = pci_dev_init, + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 5b4f932..222be18 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -18,10 +18,15 @@ #include <device/pci.h> #include <device/pci_ids.h> +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations dsp_dev_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, + .ops_pci = &pci_ops, .scan_bus = &scan_static_bus, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 544ae96..2e0fef8 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -94,11 +94,16 @@ graphics_gtt_write(reg, val); } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static const struct device_operations graphics_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = graphics_soc_init, + .ops_pci = &pci_ops, .write_acpi_tables = graphics_soc_write_acpi_opregion, }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index c6f3be2..12a1efb 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -166,12 +166,17 @@ .transfer = lpss_i2c_dev_transfer, }; +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations i2c_dev_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .scan_bus = &scan_smbus, .ops_i2c_bus = &i2c_bus_ops, + .ops_pci = &pci_ops, .init = &lpss_i2c_dev_init, .acpi_fill_ssdt_generator = &lpss_i2c_acpi_fill_ssdt, }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index d425667..4519e33 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -88,14 +88,19 @@ set_child_resources(dev); } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations device_ops = { - .read_resources = soc_lpc_read_resources, - .set_resources = set_resources, - .enable_resources = pci_dev_enable_resources, - .write_acpi_tables = southbridge_write_acpi_tables, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, - .init = lpc_init, - .scan_bus = scan_lpc_bus, + .read_resources = soc_lpc_read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .init = lpc_init, + .scan_bus = scan_lpc_bus, + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 63b9c85..f9d3508 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -61,9 +61,14 @@ mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static const struct device_operations device_ops = { .read_resources = read_resources, .set_resources = DEVICE_NOOP, + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 19133f0..7d383fd 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -24,6 +24,8 @@ #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 +/* PCI-E Sub-System ID */ +#define PCIE_SUBSYSTEM_VENDOR_ID 0x94 static void pch_pcie_init(struct device *dev) { @@ -69,8 +71,16 @@ PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); } +static void pcie_dev_set_subsystem(struct device *dev, + unsigned vendor, unsigned device) +{ + pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + static struct pci_operations pcie_ops = { .set_L1_ss_latency = pcie_set_L1_ss_max_latency, + .set_subsystem = pcie_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 708e705..d86f2c8 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -94,11 +94,16 @@ } } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations device_ops = { .read_resources = &pch_pmc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &pmc_soc_init, + .ops_pci = &pci_ops, .scan_bus = &scan_lpc_bus, }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index f300656..58ba37c 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -58,11 +58,16 @@ pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations sata_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .final = sata_final, + .enable_resources = &pci_dev_enable_resources, + .final = sata_final, + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index d6f4843..9b0532d 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -54,13 +54,18 @@ } #endif +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations dev_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = &sd_fill_ssdt, #endif + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index e526baf..02268aa 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -77,12 +77,17 @@ res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations smbus_ops = { .read_resources = &smbus_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .scan_bus = &scan_smbus, .init = &pch_smbus_init, + .ops_pci = &pci_ops, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 9a34044..725c62b 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -43,12 +43,17 @@ .dev_to_bus = &spi_dev_to_bus, }; +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations spi_dev_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .scan_bus = &scan_generic_bus, .ops_spi_bus = &spi_bus_ops, + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 05fc5c7..7184c69 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -38,11 +38,16 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static const struct device_operations device_ops = { .read_resources = sram_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = soc_sram_init, + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 5be9fe1..89705e8 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -276,11 +276,16 @@ MCHBAR8(MCH_PAIR) = pair; } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations systemagent_ops = { .read_resources = &systemagent_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = soc_systemagent_init, + .ops_pci = &pci_ops, }; static const unsigned short systemagent_ids[] = { diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 7685415..103180b 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -140,10 +140,15 @@ } } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations device_ops = { .read_resources = &pch_uart_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &uart_common_enable_resources, + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 7b74b21..d92575c 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -22,11 +22,16 @@ __attribute__((weak)) void soc_xdci_init(struct device *dev) { /* no-op */ } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations usb_xdci_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = soc_xdci_init, + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index ac7bd58..6e85a50 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -22,11 +22,16 @@ __attribute__((weak)) void soc_xhci_init(struct device *dev) { /* no-op */ } +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + static struct device_operations usb_xhci_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = soc_xhci_init, + .ops_pci = &pci_ops, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/22768 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be Gerrit-Change-Number: 22768 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add support for nami board
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22703 ) Change subject: mb/google/poppy/variants/nami: Add support for nami board ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64257/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19078/ : SUCCESS -- To view, visit https://review.coreboot.org/22703 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412 Gerrit-Change-Number: 22703 Gerrit-PatchSet: 9 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 08:08:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Add support for DDR4 memory
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22745 ) Change subject: mb/google/poppy: Add support for DDR4 memory ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64256/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19077/ : SUCCESS -- To view, visit https://review.coreboot.org/22745 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2 Gerrit-Change-Number: 22745 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 08:05:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/reef: provide override GPIO table in coral
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22752 ) Change subject: mb/google/reef: provide override GPIO table in coral ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64255/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19076/ : SUCCESS -- To view, visit https://review.coreboot.org/22752 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9e0674f206426fddb3947273754774b310106334 Gerrit-Change-Number: 22752 Gerrit-PatchSet: 4 Gerrit-Owner: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Scott Collyer <scollyer(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 06:57:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Clean up bootblock/report_platform.c
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22756 ) Change subject: soc/intel/skylake: Clean up bootblock/report_platform.c ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64254/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19075/ : SUCCESS -- To view, visit https://review.coreboot.org/22756 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f7f219536831210750a486ee3b3308d6f285451 Gerrit-Change-Number: 22756 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 07 Dec 2017 06:56:56 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017