coreboot-gerrit December 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/apollolake: Add SMI and SCI support for ESPI
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22758 ) Change subject: soc/intel/apollolake: Add SMI and SCI support for ESPI ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64228/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19054/ : SUCCESS -- To view, visit https://review.coreboot.org/22758 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e Gerrit-Change-Number: 22758 Gerrit-PatchSet: 3 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 23:38:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/glkrvp: Change gpio configuration for eSPI
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22757 ) Change subject: mainboard/intel/glkrvp: Change gpio configuration for eSPI ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64226/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19052/ : SUCCESS -- To view, visit https://review.coreboot.org/22757 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I15c5f769f36a1801217b1e3650379c7b181d814f Gerrit-Change-Number: 22757 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 23:34:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: add ability to enable eSPI
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22320 ) Change subject: soc/intel/apollolake: add ability to enable eSPI ...................................................................... Patch Set 11: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64225/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19051/ : SUCCESS -- To view, visit https://review.coreboot.org/22320 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5 Gerrit-Change-Number: 22320 Gerrit-PatchSet: 11 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 23:33:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/intel/glkrvp: Add gpio.h in dsdt.asl file
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22760 ) Change subject: mb/intel/glkrvp: Add gpio.h in dsdt.asl file ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64227/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19053/ : SUCCESS -- To view, visit https://review.coreboot.org/22760 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ideb6dd4d0ac496a81721cd883865218cb19583d9 Gerrit-Change-Number: 22760 Gerrit-PatchSet: 3 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 23:28:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/scarlet: update Kingdisplay kd097d04 timing
by Julius Werner (Code Review) 06 Dec '17

06 Dec '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/22746 ) Change subject: google/scarlet: update Kingdisplay kd097d04 timing ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/22746 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib061f5e215611d20f59e3f24cfe3c7fbc507ebed Gerrit-Change-Number: 22746 Gerrit-PatchSet: 1 Gerrit-Owner: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey yang <nickey.yang(a)rock-chips.com> Gerrit-Comment-Date: Wed, 06 Dec 2017 23:26:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/common: Move files to common/block
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22765 ) Change subject: soc/amd/common: Move files to common/block ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64224/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19050/ : SUCCESS -- To view, visit https://review.coreboot.org/22765 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Gerrit-Change-Number: 22765 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 23:26:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/common: Move files to common/block
by Richard Spiegel (Code Review) 06 Dec '17

06 Dec '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22765 Change subject: soc/amd/common: Move files to common/block ...................................................................... soc/amd/common: Move files to common/block The following files need to be moved: amd_pci_util.c, amd_pci_util.h and spi.c. The remaining files are AGESA related and will be part of a separate issue/commit. After AGESA related files are moved, Kconfig and Makefile.inc will be removed too, thus rending a clean soc/amd/common folder. BUG=b:62240201 TEST=Build with no error. Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/mptable.c M src/soc/amd/common/Makefile.inc R src/soc/amd/common/block/include/amdblocks/amd_pci_util.h A src/soc/amd/common/block/pci/Kconfig A src/soc/amd/common/block/pci/Makefile.inc R src/soc/amd/common/block/pci/amd_pci_util.c A src/soc/amd/common/block/spi/Kconfig A src/soc/amd/common/block/spi/Makefile.inc R src/soc/amd/common/block/spi/spi.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/southbridge.c 14 files changed, 34 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/22765/1 diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index bd9f06c..25cf5b3 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <arch/acpi.h> #include <agesawrapper.h> -#include <amd_pci_util.h> +#include <amdblocks/amd_pci_util.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c index 5c07186..e29b3e3 100644 --- a/src/mainboard/amd/gardenia/mptable.c +++ b/src/mainboard/amd/gardenia/mptable.c @@ -23,7 +23,7 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <soc/southbridge.h> -#include <amd_pci_util.h> +#include <amdblocks/amd_pci_util.h> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 8e0358a..fc13567 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <arch/acpi.h> #include <agesawrapper.h> -#include <amd_pci_util.h> +#include <amdblocks/amd_pci_util.h> #include <cbmem.h> #include <baseboard/variants.h> #include <boardid.h> diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c index 5c07186..e29b3e3 100644 --- a/src/mainboard/google/kahlee/mptable.c +++ b/src/mainboard/google/kahlee/mptable.c @@ -23,7 +23,7 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <soc/southbridge.h> -#include <amd_pci_util.h> +#include <amdblocks/amd_pci_util.h> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index aa27512..b485bb3 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -12,10 +12,8 @@ ramstage-y += agesawrapper.c ramstage-y += amd_late_init.c -ramstage-y += amd_pci_util.c ramstage-y += def_callouts.c ramstage-y += heapmanager.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block diff --git a/src/soc/amd/common/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h similarity index 100% rename from src/soc/amd/common/amd_pci_util.h rename to src/soc/amd/common/block/include/amdblocks/amd_pci_util.h diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig new file mode 100644 index 0000000..aa5e8db --- /dev/null +++ b/src/soc/amd/common/block/pci/Kconfig @@ -0,0 +1,7 @@ +config SOC_AMD_COMMON_BLOCK_PCI + bool + default n + help + This option allows the SOC to use AMD common PCI utilities + to program IRQ. If this option is not used, the SOC must + implement these functions separately. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc new file mode 100644 index 0000000..fc40c9d --- /dev/null +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y) + +ramstage-y += amd_pci_util.c + +endif diff --git a/src/soc/amd/common/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c similarity index 98% rename from src/soc/amd/common/amd_pci_util.c rename to src/soc/amd/common/block/pci/amd_pci_util.c index 577b5cb..218f9d2 100644 --- a/src/soc/amd/common/amd_pci_util.c +++ b/src/soc/amd/common/block/pci/amd_pci_util.c @@ -17,7 +17,7 @@ #include <device/pci.h> #include <arch/io.h> #include <string.h> -#include <amd_pci_util.h> +#include <amdblocks/amd_pci_util.h> #include <pc80/i8259.h> #include <soc/amd_pci_int_defs.h> #include <amd_pci_int_types.h> @@ -174,7 +174,7 @@ continue; } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ - printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index" + printk (BIOS_ERR, "%s: got 0xC00/0xC01 table index" " 0x%x, max is 0x%x\n", __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); continue; diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig new file mode 100644 index 0000000..b594789 --- /dev/null +++ b/src/soc/amd/common/block/spi/Kconfig @@ -0,0 +1,7 @@ +config SOC_AMD_COMMON_BLOCK_SPI + bool + default n + help + This option allows the SOC to use AMD common PCI utilities + to program IRQ. If this option is not used, the SOC must + implement these functions separately. diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc new file mode 100644 index 0000000..fe2eabc --- /dev/null +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y) + +ramstage-$(CONFIG_SPI_FLASH) += spi.c + +endif diff --git a/src/soc/amd/common/spi.c b/src/soc/amd/common/block/spi/spi.c similarity index 96% rename from src/soc/amd/common/spi.c rename to src/soc/amd/common/block/spi/spi.c index 44c86e6..cf28985 100644 --- a/src/soc/amd/common/spi.c +++ b/src/soc/amd/common/block/spi/spi.c @@ -16,7 +16,7 @@ #include <console/console.h> #include <spi-generic.h> #include <spi_flash.h> -#include "s3_resume.h" +#include <amdblocks/s3_resume.h> void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) { diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 3ca0e39..fe4e4ef 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,8 +46,10 @@ select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR + select SOC_AMD_COMMON_BLOCK_SPI select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE select RELOCATABLE_MODULES diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index dbf27bc..267b16b 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <amd_pci_util.h> +#include <amdblocks/amd_pci_util.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <fchec.h> -- To view, visit https://review.coreboot.org/22765 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Gerrit-Change-Number: 22765 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/intel/glkrvp: Add gpio.h in dsdt.asl file
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22760 ) Change subject: mb/intel/glkrvp: Add gpio.h in dsdt.asl file ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64223/ : SUCCESS -- To view, visit https://review.coreboot.org/22760 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ideb6dd4d0ac496a81721cd883865218cb19583d9 Gerrit-Change-Number: 22760 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 22:47:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: add ability to enable eSPI
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22320 ) Change subject: soc/intel/apollolake: add ability to enable eSPI ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64222/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19049/ : SUCCESS -- To view, visit https://review.coreboot.org/22320 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5 Gerrit-Change-Number: 22320 Gerrit-PatchSet: 10 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 22:36:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/fizz: Enable mbox command for ISL VR c-state issue
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22763 ) Change subject: mb/google/fizz: Enable mbox command for ISL VR c-state issue ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64221/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19048/ : SUCCESS -- To view, visit https://review.coreboot.org/22763 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iebfda02df88ea0d2aaf79e8449b95c0eb2165c6b Gerrit-Change-Number: 22763 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 22:02:15 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017