coreboot-gerrit November 2017

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Change in coreboot[master]: amd/stoneyridge: Define MTRR S3 structures
by Marshall Dawson (Code Review) 30 Nov '17

30 Nov '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22643 Change subject: amd/stoneyridge: Define MTRR S3 structures ...................................................................... amd/stoneyridge: Define MTRR S3 structures In subsequent S3 patches, MTRR settings will be stored in DRAM. This is a departure from other examples of AMD support, including the binaryPI S3 support that was stripped out earlier. Create structures to simplify saving and restoring the MTRR settings. Change-Id: Ibd0dbf067e2a752636132de102028b1ebacf2343 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/s3_resume.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/22643/1 diff --git a/src/soc/amd/common/s3_resume.h b/src/soc/amd/common/s3_resume.h index 39a0712..3e80d72 100644 --- a/src/soc/amd/common/s3_resume.h +++ b/src/soc/amd/common/s3_resume.h @@ -16,6 +16,30 @@ #ifndef __S3_RESUME_H__ #define __S3_RESUME_H__ +#include <cpu/x86/msr.h> + +struct vmtrr_pair { + msr_t base; + msr_t mask; +}; + +#define MAX_VAR_MTRRS 0x20 +struct all_mtrrs { + msr_t sys_cfg; + msr_t _64k_00; + msr_t _16k_80; + msr_t _16k_a0; + msr_t _4k_c0; + msr_t _4k_c8; + msr_t _4k_d0; + msr_t _4k_d8; + msr_t _4k_e0; + msr_t _4k_e8; + msr_t _4k_f0; + msr_t _4k_f8; + struct vmtrr_pair vmtrr[MAX_VAR_MTRRS]; +}; + void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); #endif /* __S3_RESUME_H__ */ -- To view, visit https://review.coreboot.org/22643 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibd0dbf067e2a752636132de102028b1ebacf2343 Gerrit-Change-Number: 22643 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: ************ fix this up soc/amd/common: Define regions in AGESA ...
by Marshall Dawson (Code Review) 30 Nov '17

30 Nov '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22644 Change subject: ************ fix this up soc/amd/common: Define regions in AGESA cbmem ...................................................................... ************ fix this up soc/amd/common: Define regions in AGESA cbmem In 6c747068 "amd/stoneyridge: Put AGESA heap into cbmem" the AGESA heap was moved completely into cbmem. This was a departure from the "late cbmem init" method of adding late in post, then storing the S3 volatile data to the region. To prepare for S3 support, split the region into subregions for heap, AGESAs S3 volatile storage, and an MTRR save area. Change-Id: Id316db22ef57d19d61eba38c3a867ee44cbe7c2d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/BiosCallOuts.h M src/soc/amd/common/heapmanager.c 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/22644/1 diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/BiosCallOuts.h index 5237d52..0d287f9 100644 --- a/src/soc/amd/common/BiosCallOuts.h +++ b/src/soc/amd/common/BiosCallOuts.h @@ -17,12 +17,24 @@ #ifndef __CALLOUTS_AMD_AGESA_H__ #define __CALLOUTS_AMD_AGESA_H__ +#include "s3_resume.h" #include "agesawrapper.h" -#define BIOS_HEAP_START_ADDRESS 0x010000000 +//#define S3_NONVOLATILE_SIZE 0x1000 +//#define S3_MTRR_SIZE 0x1000 +//#define S3_TOTAL_SIZE (S3_NONVOLATILE_SIZE + S3_MTRR_SIZE) +#define S3_VOLATILE_SIZE 0x6000 #define BIOS_HEAP_SIZE 0x30000 #define BSP_STACK_BASE_ADDR 0x30000 +struct cbmem_usage { + uint8_t heap_base[BIOS_HEAP_SIZE]; +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + uint8_t s3_save_area[S3_VOLATILE_SIZE]; + struct all_mtrrs s3_mtrrs; +#endif +}; + typedef struct _BIOS_HEAP_MANAGER { UINT32 StartOfAllocatedNodes; UINT32 StartOfFreedNodes; diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/heapmanager.c index b991514..22d95f0 100644 --- a/src/soc/amd/common/heapmanager.c +++ b/src/soc/amd/common/heapmanager.c @@ -21,7 +21,10 @@ static void *GetHeapBase(void) { - return cbmem_add(CBMEM_ID_RESUME_SCRATCH, BIOS_HEAP_SIZE); + struct cbmem_usage *heap; + heap = (struct cbmem_usage *)cbmem_add(CBMEM_ID_RESUME_SCRATCH, + sizeof(struct cbmem_usage)); + return (void *)heap->heap_base; } static void EmptyHeap(int unused) -- To view, visit https://review.coreboot.org/22644 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id316db22ef57d19d61eba38c3a867ee44cbe7c2d Gerrit-Change-Number: 22644 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Add S3 region to Kconfig
by Marshall Dawson (Code Review) 30 Nov '17

30 Nov '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22642 Change subject: soc/amd/common: Add S3 region to Kconfig ...................................................................... soc/amd/common: Add S3 region to Kconfig Add the symbols back to Kconfig and make the S3 base and offset depend on HAVE_ACPI_RESUME. These will form the "backup" region for storing S3 data. The values are typical for AMD platforms and should allow adequate room for rotation (the Stoney Ridge NV size is 0x4c1 currently). Note that the primary choice for the S3 save location will be eventually be determined by the FMAP. Change-Id: I67846e47d364ecfc01934e879e3299813fcda1b3 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/Kconfig 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/22642/1 diff --git a/src/soc/amd/common/Kconfig b/src/soc/amd/common/Kconfig index debedac..33713f9 100644 --- a/src/soc/amd/common/Kconfig +++ b/src/soc/amd/common/Kconfig @@ -11,4 +11,24 @@ source "src/soc/amd/common/block/Kconfig" +config S3_DATA_POS + hex + depends on HAVE_ACPI_RESUME + default 0xffff0000 + help + For designs not using a flash map, this is the physical address where + S3 resume data is stored in the SPI flash. Place this on a 4KB + boundary for best results. The designer must ensure the region does + not interfere with anything else in the image. + +config S3_DATA_SIZE + int + depends on HAVE_ACPI_RESUME + default 32768 + help + For designs not using a flash map, this is the total size of the + region to be used for S3 resume data in the SPI flash. Make this + a multiple of 4KB for best results. The designer must ensure the + region does not interfere with anything else in the image. + endif # SOC_AMD_COMMON -- To view, visit https://review.coreboot.org/22642 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I67846e47d364ecfc01934e879e3299813fcda1b3 Gerrit-Change-Number: 22642 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Add s3_resume.h file
by Marshall Dawson (Code Review) 30 Nov '17

30 Nov '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22641 Change subject: soc/amd/common: Add s3_resume.h file ...................................................................... soc/amd/common: Add s3_resume.h file The common/spi.c file normally isn't built but may be by selecting the right Kconfig symbols. A build error occurs due to a missing header file. This may have been an oversight when stoneyridge was converted to soc or when S3 was removed from all binaryPI implementations. The spi.c file will be modified in a subsequent patch so it's here maintained and made to build. Add the missing file with to allow the file to build. TEST: select SPI_FLASH and build Kahlee BUG=b:69930455 Change-Id: I4ebb3098c6c1f42a94daa9b3d4eb7faa2fdf3f32 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/soc/amd/common/s3_resume.h 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/22641/1 diff --git a/src/soc/amd/common/s3_resume.h b/src/soc/amd/common/s3_resume.h new file mode 100644 index 0000000..39a0712 --- /dev/null +++ b/src/soc/amd/common/s3_resume.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __S3_RESUME_H__ +#define __S3_RESUME_H__ + +void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); + +#endif /* __S3_RESUME_H__ */ -- To view, visit https://review.coreboot.org/22641 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4ebb3098c6c1f42a94daa9b3d4eb7faa2fdf3f32 Gerrit-Change-Number: 22641 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/{hudson, stoneyridge}: fix out of bounds read
by build bot (Jenkins) (Code Review) 30 Nov '17

30 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22619 ) Change subject: amd/{hudson,stoneyridge}: fix out of bounds read ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63945/ : SUCCESS -- To view, visit https://review.coreboot.org/22619 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic16edc607358b9a688151735e6fcb3393d3bce80 Gerrit-Change-Number: 22619 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Nov 2017 14:55:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: crossgcc: fix edk2 tools_def template
by build bot (Jenkins) (Code Review) 30 Nov '17

30 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22640 ) Change subject: crossgcc: fix edk2 tools_def template ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18803/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63944/ : SUCCESS https://qa.coreboot.org/job/coreboot-toolchain/390/ : SUCCESS -- To view, visit https://review.coreboot.org/22640 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87d63ec18338e376787d02bb771471e746a17b62 Gerrit-Change-Number: 22640 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Nov 2017 14:17:21 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: crossgcc: fix edk2 tools_def template
by Patrick Georgi (Code Review) 30 Nov '17

30 Nov '17

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/22640 Change subject: crossgcc: fix edk2 tools_def template ...................................................................... crossgcc: fix edk2 tools_def template Forgot the /bin/ part of the executable paths Change-Id: I87d63ec18338e376787d02bb771471e746a17b62 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/crossgcc/edk2tools.txt 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/22640/1 diff --git a/util/crossgcc/edk2tools.txt b/util/crossgcc/edk2tools.txt index 8420c14..0344bf2 100644 --- a/util/crossgcc/edk2tools.txt +++ b/util/crossgcc/edk2tools.txt @@ -4,10 +4,10 @@ # #################################################################################### -DEFINE COREBOOT_IA32_PREFIX = @@PREFIX@@/i386-elf- -DEFINE COREBOOT_X64_PREFIX = @@PREFIX@@/x86_64-elf- -DEFINE COREBOOT_ARM_PREFIX = @@PREFIX@@/arm-eabi- -DEFINE COREBOOT_AARCH64_PREFIX = @@PREFIX@@/arch64-elf- +DEFINE COREBOOT_IA32_PREFIX = @@PREFIX@@/bin/i386-elf- +DEFINE COREBOOT_X64_PREFIX = @@PREFIX@@/bin/x86_64-elf- +DEFINE COREBOOT_ARM_PREFIX = @@PREFIX@@/bin/arm-eabi- +DEFINE COREBOOT_AARCH64_PREFIX = @@PREFIX@@/bin/arch64-elf- DEFINE COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) DEFINE COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -- To view, visit https://review.coreboot.org/22640 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I87d63ec18338e376787d02bb771471e746a17b62 Gerrit-Change-Number: 22640 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: soc/intel/cannonlake: Make use of Intel common Graphics block
by build bot (Jenkins) (Code Review) 30 Nov '17

30 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22617 ) Change subject: soc/intel/cannonlake: Make use of Intel common Graphics block ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18801/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63942/ : SUCCESS -- To view, visit https://review.coreboot.org/22617 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d Gerrit-Change-Number: 22617 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Nov 2017 10:27:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/nautilus: add synaptics touch screen support
by build bot (Jenkins) (Code Review) 30 Nov '17

30 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22613 ) Change subject: mb/google/nautilus: add synaptics touch screen support ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18802/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63943/ : SUCCESS -- To view, visit https://review.coreboot.org/22613 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6 Gerrit-Change-Number: 22613 Gerrit-PatchSet: 4 Gerrit-Owner: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: shkim <sh_.kim(a)samsung.com> Gerrit-Comment-Date: Thu, 30 Nov 2017 10:26:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Add PNP config
by build bot (Jenkins) (Code Review) 30 Nov '17

30 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22488 ) Change subject: soc/intel/apollolake: Add PNP config ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18797/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63938/ : SUCCESS -- To view, visit https://review.coreboot.org/22488 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Gerrit-Change-Number: 22488 Gerrit-PatchSet: 6 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Nov 2017 10:23:52 +0000 Gerrit-HasComments: No

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coreboot-gerrit November 2017