coreboot-gerrit November 2017

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Change in coreboot[master]: google/reks: override RX ODT limit, RAM geometry if needed
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22268 ) Change subject: google/reks: override RX ODT limit, RAM geometry if needed ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17766/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62767/ : SUCCESS -- To view, visit https://review.coreboot.org/22268 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423 Gerrit-Change-Number: 22268 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 05:45:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/reks: override USB2 Phy settings on BSW D-Stepping SOC
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22269 ) Change subject: google/reks: override USB2 Phy settings on BSW D-Stepping SOC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17765/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62766/ : SUCCESS -- To view, visit https://review.coreboot.org/22269 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414 Gerrit-Change-Number: 22269 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 05:40:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/reks: override RX ODT limit, RAM geometry if needed
by Matt DeVillier (Code Review) 01 Nov '17

01 Nov '17

Matt DeVillier has uploaded a new patch set (#2). ( https://review.coreboot.org/22268 ) Change subject: google/reks: override RX ODT limit, RAM geometry if needed ...................................................................... google/reks: override RX ODT limit, RAM geometry if needed Adapted from Chromium commit 6ee6f3d: Reks: To set the RX ODT limit... Override RX ODT and DRAM geometry for Micron part MT52L256M32D1PF-107. Use get_ramid() to determine if override is necessary. Original-Change-Id: I41f3aba030a00152e1217533ef953338ac396605 Original-Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Original-Reviewed-by: Kane Chen <kane.chen(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng(a)quantatw.com> Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/reks/Makefile.inc A src/mainboard/google/cyan/variants/reks/romstage.c 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/22268/2 -- To view, visit https://review.coreboot.org/22268 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423 Gerrit-Change-Number: 22268 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/reks: override RX ODT limit, RAM geometry if needed
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22268 ) Change subject: google/reks: override RX ODT limit, RAM geometry if needed ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/62765/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/17764/ : SUCCESS -- To view, visit https://review.coreboot.org/22268 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423 Gerrit-Change-Number: 22268 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 05:34:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/reks: override USB2 Phy settings on BSW D-Stepping SOC
by Matt DeVillier (Code Review) 01 Nov '17

01 Nov '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/22269 Change subject: google/reks: override USB2 Phy settings on BSW D-Stepping SOC ...................................................................... google/reks: override USB2 Phy settings on BSW D-Stepping SOC Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings... Base on Intel recommendation, override following settings for USB2 port 1/2/3 on BSW D-stepping SOC. 1. Set USB[1] register for right side to 7321 2. Set USB[2] register for left side to 7021 3. Set USB[3] register for CCD to 7021 Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng(a)quantatw.com> Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/reks/Makefile.inc A src/mainboard/google/cyan/variants/reks/ramstage.c 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/22269/1 diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc index 6577124..86499b4 100644 --- a/src/mainboard/google/cyan/variants/reks/Makefile.inc +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -17,6 +17,7 @@ romstage-y += spd_util.c ramstage-y += gpio.c +ramstage-y += ramstage.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/cyan/variants/reks/ramstage.c b/src/mainboard/google/cyan/variants/reks/ramstage.c new file mode 100644 index 0000000..27f9dfa --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/ramstage.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> + +void board_silicon_USB2_override(SILICON_INIT_UPD *params) +{ + if (SocStepping() >= SocD0) { + //D-Stepping + //USB2[1] right external port + params->Usb2Port1PerPortPeTxiSet = 7; + params->Usb2Port1PerPortTxiSet = 3; + params->Usb2Port1IUsbTxEmphasisEn = 2; + params->Usb2Port1PerPortTxPeHalf = 1; + + //USB2[2] left external port + params->Usb2Port2PerPortPeTxiSet = 7; + params->Usb2Port2PerPortTxiSet = 0; + params->Usb2Port2IUsbTxEmphasisEn = 2; + params->Usb2Port2PerPortTxPeHalf = 1; + + //USB2[3] CCD + params->Usb2Port3PerPortPeTxiSet = 7; + params->Usb2Port3PerPortTxiSet = 0; + params->Usb2Port3IUsbTxEmphasisEn = 2; + params->Usb2Port3PerPortTxPeHalf = 1; + } +} -- To view, visit https://review.coreboot.org/22269 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414 Gerrit-Change-Number: 22269 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/fizz: enable SPD read by word
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22267 ) Change subject: google/fizz: enable SPD read by word ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/62764/ : SUCCESS -- To view, visit https://review.coreboot.org/22267 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57 Gerrit-Change-Number: 22267 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 05:29:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/reks: override RX ODT limit, RAM geometry if needed
by Matt DeVillier (Code Review) 01 Nov '17

01 Nov '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/22268 Change subject: google/reks: override RX ODT limit, RAM geometry if needed ...................................................................... google/reks: override RX ODT limit, RAM geometry if needed Adapted from Chromium commit 6ee6f3d: Reks: To set the RX ODT limit... Override RX ODT and DRAM geometry for Micron part MT52L256M32D1PF-107. Use get_ramid() to determine if override is necessary. Original-Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Original-Reviewed-by: Kane Chen <kane.chen(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng(a)quantatw.com> Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- A src/mainboard/google/cyan/variants/reks/romstage.c 1 file changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/22268/1 diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c new file mode 100644 index 0000000..5414cbd --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <baseboard/variants.h> +#include <mainboard/google/cyan/spd/spd_util.h> + +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) +{ + int ram_id = get_ramid(); + + /* + * RAMID = A - 4GiB Micron MT52L256M32D1PF-107 + * RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107 + */ + if (ram_id == 2 || ram_id == 0xA) { + + /* + * For new micron part, it requires read/receive + * enable training before sending cmds to get MR8. + * To override dram geometry settings as below: + * + * PcdDramWidth = x32 + * PcdDramDensity = 8Gb + * PcdDualRankDram = disable + */ + memory_params->PcdRxOdtLimitChannel0 = 1; + memory_params->PcdRxOdtLimitChannel1 = 1; + memory_params->PcdDisableAutoDetectDram = 1; + memory_params->PcdDramWidth = 2; + memory_params->PcdDramDensity = 3; + memory_params->PcdDualRankDram = 0; + } +} -- To view, visit https://review.coreboot.org/22268 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423 Gerrit-Change-Number: 22268 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/fizz: enable SPD read by word
by Kane Chen (Code Review) 01 Nov '17

01 Nov '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22267 to look at the new patch set (#2). Change subject: google/fizz: enable SPD read by word ...................................................................... google/fizz: enable SPD read by word This is to enable SPD word access to reduce boot time. It can save 80 ~ 100 ms per DIMM BUG=b:67021853 BRANCH=None TEST=system boot, and boot time is reduced Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/fizz/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/22267/2 -- To view, visit https://review.coreboot.org/22267 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57 Gerrit-Change-Number: 22267 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/fizz: enable SPD word access
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22267 ) Change subject: google/fizz: enable SPD word access ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17763/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62763/ : SUCCESS -- To view, visit https://review.coreboot.org/22267 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57 Gerrit-Change-Number: 22267 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 05:11:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: enable SPD word access
by Kane Chen (Code Review) 01 Nov '17

01 Nov '17

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/22267 Change subject: google/fizz: enable SPD word access ...................................................................... google/fizz: enable SPD word access This is to enable SPD word access to reduce boot time. It can save 80 ~ 100 ms per DIMM BUG=b:67021853 BRANCH=None TEST=system boot, and boot time is reduced Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/fizz/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/22267/1 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 34e3881..8036b8b 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -18,6 +18,7 @@ select FIZZ_USE_SPI_TPM select GENERIC_SPD_BIN select RT8168_GET_MAC_FROM_VPD + select SPD_READ_BY_WORD config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES -- To view, visit https://review.coreboot.org/22267 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57 Gerrit-Change-Number: 22267 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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coreboot-gerrit November 2017