coreboot-gerrit November 2017

coreboot-gerrit@coreboot.org

1 participants
1623 discussions

Change in coreboot[master]: nb/intel/x4x: Add a convenient macro to loop over bytelanes
by build bot (Jenkins) (Code Review) 05 Nov '17

05 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22347 ) Change subject: nb/intel/x4x: Add a convenient macro to loop over bytelanes ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17975/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63015/ : SUCCESS -- To view, visit https://review.coreboot.org/22347 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857 Gerrit-Change-Number: 22347 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Nov 2017 07:51:26 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/intel/x4x: Add a convenient macro to loop over bytelanes
by Arthur Heymans (Code Review) 05 Nov '17

05 Nov '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22347 Change subject: nb/intel/x4x: Add a convenient macro to loop over bytelanes ...................................................................... nb/intel/x4x: Add a convenient macro to loop over bytelanes During raminit a lot of procedures need to be done for each bytelane. Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr2.c M src/northbridge/intel/x4x/rcven.c M src/northbridge/intel/x4x/x4x.h 3 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/22347/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index e3d5bb9..9ed4295 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -809,7 +809,7 @@ int ch, lane, rank; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { - for (lane = 0; lane < 8; lane++) { + FOR_EACH_BYTELANE(lane) { FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank) { switch (s->selected_timings.mem_clk) { case MEM_CLOCK_667MHz: @@ -871,7 +871,7 @@ int ch, lane, rank; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { - for (lane = 0; lane < 8; lane++) { + FOR_EACH_BYTELANE(lane) { FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank) { rt_set_dqs(ch, lane, rank, &s->rt_dqs[ch][rank][lane]); @@ -1148,7 +1148,7 @@ reg32 |= s->rcven_t[channel].min_common_coarse << 16; MCHBAR32(0x400 * channel + 0x248) = reg32; - for (lane = 0; lane < 8; lane++) { + FOR_EACH_BYTELANE(lane) { medium |= s->rcven_t[channel].medium[lane] << (lane * 2); coarse_offset |= diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 1f27208..b1ef034 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -325,7 +325,7 @@ addr = test_address(channel, rank); break; } - for (lane = 0; lane < 8; lane++) { + FOR_EACH_BYTELANE(lane) { printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n", channel, lane, addr); timing[lane].coarse = (s->selected_timings.CAS + 1); @@ -361,7 +361,7 @@ s->rcven_t[channel].min_common_coarse = mincoarse; printk(BIOS_DEBUG, "Receive enable, final timings:\n"); /* Normalise coarse */ - for (lane = 0; lane < 8; lane++) { + FOR_EACH_BYTELANE(lane) { if (timing[lane].coarse == 0) reg8 = 0; else diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 434c5f3..5f2c440 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -161,6 +161,7 @@ #define TOTAL_CHANNELS 2 #define TOTAL_DIMMS 4 +#define TOTAL_BYTELANES 8 #define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) #define RAW_CARD_UNPOPULATED 0xff #define RAW_CARD_POPULATED 0 @@ -215,6 +216,8 @@ FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) #define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) +#define FOR_EACH_BYTELANE(l) \ + for (l = 0; l < TOTAL_BYTELANES; l++) #define DDR3_MAX_CAS 18 -- To view, visit https://review.coreboot.org/22347 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857 Gerrit-Change-Number: 22347 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: drvs/lenovo/hybrid_graphics/romstage: Fix for PMH7 boards
by build bot (Jenkins) (Code Review) 05 Nov '17

05 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22341 ) Change subject: drvs/lenovo/hybrid_graphics/romstage: Fix for PMH7 boards ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17971/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63011/ : SUCCESS -- To view, visit https://review.coreboot.org/22341 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30ec19e13269cb254e51ad1fab3b10ad1a49e86e Gerrit-Change-Number: 22341 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vasya Boytsov <vasiliy.boytsov(a)phystech.edu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Nov 2017 07:09:41 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: util/inteltool: Add Skylake DMIBAR register dumping
by build bot (Jenkins) (Code Review) 05 Nov '17

05 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22345 ) Change subject: util/inteltool: Add Skylake DMIBAR register dumping ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63010/ : SUCCESS -- To view, visit https://review.coreboot.org/22345 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Gerrit-Change-Number: 22345 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Nov 2017 06:09:11 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: util/inteltool: Add Skylake DMIBAR register dumping
by Maximilian Schander (Code Review) 05 Nov '17

05 Nov '17

Hello Jonathan Neuschäfer, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/22345 to look at the new patch set (#3). Change subject: util/inteltool: Add Skylake DMIBAR register dumping ...................................................................... util/inteltool: Add Skylake DMIBAR register dumping Register definitions were taken from * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2 * Page 117 * 332688-003EN Tested on a 6th gen skylake mobile cpu and capability registers do match up with the default values. Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Signed-off-by: Maximilian Schander <coreboot(a)mimoja.de> --- M util/inteltool/pcie.c 1 file changed, 70 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/22345/3 -- To view, visit https://review.coreboot.org/22345 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Gerrit-Change-Number: 22345 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: util/inteltool Add Skylake DMIBAR register dumping
by Jonathan Neuschäfer (Code Review) 05 Nov '17

05 Nov '17

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/22345 ) Change subject: util/inteltool Add Skylake DMIBAR register dumping ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/22345/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/22345/2//COMMIT_MSG@7 PS2, Line 7: ol : -- To view, visit https://review.coreboot.org/22345 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Gerrit-Change-Number: 22345 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Nov 2017 05:27:46 +0000 Gerrit-HasComments: Yes

1 0

Change in coreboot[master]: util/inteltool Add Skylake DMIBAR register dumping
by build bot (Jenkins) (Code Review) 05 Nov '17

05 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22345 ) Change subject: util/inteltool Add Skylake DMIBAR register dumping ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17970/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63009/ : SUCCESS -- To view, visit https://review.coreboot.org/22345 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Gerrit-Change-Number: 22345 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Nov 2017 05:17:17 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: util/inteltool Add Skylake DMIBAR register dumping
by Maximilian Schander (Code Review) 05 Nov '17

05 Nov '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22345 to look at the new patch set (#2). Change subject: util/inteltool Add Skylake DMIBAR register dumping ...................................................................... util/inteltool Add Skylake DMIBAR register dumping Register definitions were taken from * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2 * Page 117 * 332688-003EN Tested on a 6th gen skylake mobile cpu and capability registers do match up with the default values. Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Signed-off-by: Maximilian Schander <coreboot(a)mimoja.de> --- M util/inteltool/pcie.c 1 file changed, 70 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/22345/2 -- To view, visit https://review.coreboot.org/22345 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Gerrit-Change-Number: 22345 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: util/inteltool Add Skylake DMIBAR register dumping
by build bot (Jenkins) (Code Review) 05 Nov '17

05 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22345 ) Change subject: util/inteltool Add Skylake DMIBAR register dumping ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17969/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63008/ : SUCCESS -- To view, visit https://review.coreboot.org/22345 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Gerrit-Change-Number: 22345 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Nov 2017 05:02:58 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: util/inteltool Add Skylake DMIBAR register dumping
by Maximilian Schander (Code Review) 05 Nov '17

05 Nov '17

Maximilian Schander has uploaded this change for review. ( https://review.coreboot.org/22345 Change subject: util/inteltool Add Skylake DMIBAR register dumping ...................................................................... util/inteltool Add Skylake DMIBAR register dumping Register definitions were taken from * 6th Generation Intel Processor Families for S-Platform Col 2 * Page 117 * 332688-003EN Tested on a 6th gen skylake mobile cpu and capability registers do match up with the default values. Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Signed-off-by: Maximilian Schander <coreboot(a)mimoja.de> --- M util/inteltool/pcie.c 1 file changed, 70 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/22345/1 diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 67b0e19..7e28cc3 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -171,6 +171,68 @@ /* ... - Reserved */ }; + +/* + * All Skylake DMI Registers per + * + * 6th Generation Intel Processor Families for S-Platform Col 2 + * Page 117 + * 332688-003EN + */ +static const io_register_t skylake_dmi_registers[] = { + { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control +/* { 0x0E, 2, "RSVD" }, // Reserved */ + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control +/* { 0x18, 2, "RSVD" }, // Reserved */ + { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control +/* { 0x24, 2, "RSVD" }, // Reserved */ + { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status +/* { 0x28, 4 "RSVD" }, // Reserved */ +/* { 0x2C, 4, "RSVD" }, // Reserved */ +/* { 0x30, 2, "RSVD" }, // Reserved */ +/* { 0x32, 4, "RSVD" }, // Reserved */ + { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability + { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control +/* { 0x3C, 2, "RSVD" }, // Reserved */ + { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status + { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ + { 0x44, 4, "DMIESD" }, // DMI Element Self Description +/* { 0x48, 4, "RSVD" }, // Reserved */ +/* { 0x4C, 4, "RSVD" }, // Reserved */ + { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description +/* { 0x54, 4, "RSVD" }, // Reserved */ + { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address + { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address + { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description +/* { 0x64, 4, "RSVD" }, // Reserved */ + { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address +/* { 0x6C, 4, "RSVD" }, // Reserved */ +/* { 0x70, 4, "RSVD" }, // Reserved */ +/* { 0x74, 4, "RSVD" }, // Reserved */ +/* { 0x78, 4, "RSVD" }, // Reserved */ +/* { 0x7C, 4, "RSVD" }, // Reserved */ +/* { 0x80, 4, "RSVD" }, // Reserved */ + { 0x84, 4, "LCAP" }, // Link Capabilities + { 0x88, 2, "LCTL" }, // Link Control + { 0x8A, 2, "LSTS" }, // DMI Link Status + { 0x98, 2, "LCTL2" }, // Link Control 2 + { 0x9A, 2, "LSTS2" }, // DMI Link Status 2 +/* ... - Reserved */ + { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status + { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask + { 0x1CC, 4, "DMIUESEV" }, // DMI Uncorrectable Error Mask + { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status + { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask +/* ... - Reserved */ +}; + + /* * Egress Port Root Complex MMIO configuration space */ @@ -335,7 +397,14 @@ dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; - + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: + dmi_registers = skylake_dmi_registers; + size = ARRAY_SIZE(skylake_dmi_registers); + dmibar_phys = pci_read_long(nb, 0x68); + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ + break; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); return 1; -- To view, visit https://review.coreboot.org/22345 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e Gerrit-Change-Number: 22345 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Schander <coreboot(a)mimoja.de>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2017