coreboot-gerrit November 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Make use of Intel SPI common block
by build bot (Jenkins) (Code Review) 07 Nov '17

07 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22362 ) Change subject: soc/intel/cannonlake: Make use of Intel SPI common block ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/63075/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/18027/ : SUCCESS -- To view, visit https://review.coreboot.org/22362 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174 Gerrit-Change-Number: 22362 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Nov 2017 12:45:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel SPI common block
by build bot (Jenkins) (Code Review) 07 Nov '17

07 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22361 ) Change subject: soc/intel/skylake: Make use of Intel SPI common block ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/63074/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/18026/ : SUCCESS -- To view, visit https://review.coreboot.org/22361 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3 Gerrit-Change-Number: 22361 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Nov 2017 12:45:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Make use of Intel SPI common block
by Subrata Banik (Code Review) 07 Nov '17

07 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22364 Change subject: soc/intel/apollolake: Make use of Intel SPI common block ...................................................................... soc/intel/apollolake: Make use of Intel SPI common block TEST=Build and boot reef Change-Id: I1bb22ef1737b9e35892294ec0d66df39c546d72e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc D src/soc/intel/apollolake/spi.c 3 files changed, 1 insertion(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/22364/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index cf2492c..f568799 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -86,6 +86,7 @@ select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index c295e36..5e9e5cb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += lpc.c bootblock-y += mmap_boot.c bootblock-y += pmutil.c -bootblock-y += spi.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S @@ -34,12 +33,10 @@ romstage-y += mmap_boot.c romstage-y += pmutil.c romstage-y += reset.c -romstage-y += spi.c smm-y += mmap_boot.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += spi.c smm-y += uart_early.c smm-y += uart.c @@ -58,18 +55,15 @@ ramstage-y += uart.c ramstage-y += nhlt.c ramstage-y += systemagent.c -ramstage-y += spi.c ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += sram.c -ramstage-y += spi.c ramstage-y += xdci.c ramstage-y += sd.c postcar-y += memmap.c postcar-y += mmap_boot.c -postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S @@ -82,7 +76,6 @@ verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c verstage-y += pmutil.c verstage-y += reset.c -verstage-y += spi.c ifeq ($(CONFIG_SOC_INTEL_GLK),y) bootblock-y += gpio_glk.c diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c deleted file mode 100644 index 9a651ee..0000000 --- a/src/soc/intel/apollolake/spi.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <intelblocks/fast_spi.h> -#include <spi-generic.h> - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/22364 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1bb22ef1737b9e35892294ec0d66df39c546d72e Gerrit-Change-Number: 22364 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Add support for SPI device
by Subrata Banik (Code Review) 07 Nov '17

07 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22363 Change subject: soc/intel/apollolake: Add support for SPI device ...................................................................... soc/intel/apollolake: Add support for SPI device Provide a translation table to convert SPI device structure into SPI bus number and vice versa. Change-Id: I4c8b23c7d6f289927cd7545f3875ee4352603afa Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/include/soc/pci_devs.h 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/22363/1 diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 6aa2520..3b36292 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -158,4 +158,24 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SMBUS _PCH_DEV(LPC, 1) +static inline int spi_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_SPI0: return 0; + case PCH_DEVFN_SPI1: return 1; + case PCH_DEVFN_SPI2: return 2; + } + return -1; +} + +static inline int spi_bus_to_devfn(unsigned int bus) +{ + switch (bus) { + case 0: return PCH_DEVFN_SPI0; + case 1: return PCH_DEVFN_SPI1; + case 2: return PCH_DEVFN_SPI2; + } + return -1; +} + #endif -- To view, visit https://review.coreboot.org/22363 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4c8b23c7d6f289927cd7545f3875ee4352603afa Gerrit-Change-Number: 22363 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Make use of Intel SPI common block
by Subrata Banik (Code Review) 07 Nov '17

07 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22362 Change subject: soc/intel/cannonlake: Make use of Intel SPI common block ...................................................................... soc/intel/cannonlake: Make use of Intel SPI common block TEST=Build and boot RVP Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc D src/soc/intel/cannonlake/spi.c 3 files changed, 1 insertion(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/22362/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 92aad28..36ea922 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -65,6 +65,7 @@ select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_SPI_FLASH_PROTECT diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index de137f6..93cc457 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -17,7 +17,6 @@ bootblock-y += gspi.c bootblock-y += i2c.c bootblock-y += memmap.c -bootblock-y += spi.c bootblock-$(CONFIG_UART_DEBUG) += uart.c romstage-y += gpio.c @@ -26,7 +25,6 @@ romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c -romstage-y += spi.c romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-y += acpi.c @@ -44,7 +42,6 @@ ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += smmrelocate.c -ramstage-y += spi.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c @@ -54,19 +51,16 @@ smm-y += gpio.c smm-y += pmutil.c smm-y += smihandler.c -smm-$(CONFIG_SPI_FLASH_SMM) += spi.c smm-$(CONFIG_UART_DEBUG) += uart.c smm-$(CONFIG_UART_DEBUG) += uart_pch.c postcar-y += memmap.c postcar-y += pmutil.c -postcar-y += spi.c postcar-$(CONFIG_UART_DEBUG) += uart.c verstage-y += gspi.c verstage-y += i2c.c verstage-y += pmutil.c -verstage-y += spi.c verstage-$(CONFIG_UART_DEBUG) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20 diff --git a/src/soc/intel/cannonlake/spi.c b/src/soc/intel/cannonlake/spi.c deleted file mode 100644 index 1d65dee..0000000 --- a/src/soc/intel/cannonlake/spi.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/spi.h> -#include <intelblocks/fast_spi.h> -#include <intelblocks/gspi.h> -#include <soc/ramstage.h> -#include <soc/pci_devs.h> -#include <spi-generic.h> - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, -#if !ENV_SMM - { .ctrlr = &gspi_ctrlr, .bus_start = 1, - .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)}, -#endif -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); - -#if ENV_RAMSTAGE - -static int spi_dev_to_bus(struct device *dev) -{ - return spi_devfn_to_bus(dev->path.pci.devfn); -} - -static struct spi_bus_operations spi_bus_ops = { - .dev_to_bus = &spi_dev_to_bus, -}; - -static struct device_operations spi_dev_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_generic_bus, - .ops_spi_bus = &spi_bus_ops, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI, - PCI_DEVICE_ID_INTEL_CNL_SPI0, - PCI_DEVICE_ID_INTEL_CNL_SPI1, - PCI_DEVICE_ID_INTEL_CNL_SPI2, - 0 -}; - -static const struct pci_driver pch_spi __pci_driver = { - .ops = &spi_dev_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -#endif -- To view, visit https://review.coreboot.org/22362 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174 Gerrit-Change-Number: 22362 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel SPI common block
by Subrata Banik (Code Review) 07 Nov '17

07 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22361 Change subject: soc/intel/skylake: Make use of Intel SPI common block ...................................................................... soc/intel/skylake: Make use of Intel SPI common block TEST=Build and boot soraka/eve Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3 --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/spi.c 3 files changed, 1 insertion(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/22361/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f830f54..9f8dfe5 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -73,6 +73,7 @@ select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index bc53922..e3a4eda 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -20,7 +20,6 @@ bootblock-y += gspi.c bootblock-y += pch.c bootblock-y += pmutil.c -bootblock-y += spi.c bootblock-y += lpc.c verstage-y += gspi.c @@ -28,7 +27,6 @@ verstage-$(CONFIG_UART_DEBUG) += uart_debug.c verstage-y += pmutil.c verstage-y += i2c.c -verstage-y += spi.c romstage-y += gpio.c romstage-y += gspi.c @@ -39,7 +37,6 @@ romstage-y += pei_data.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c -romstage-y += spi.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c @@ -66,7 +63,6 @@ ramstage-y += sd.c ramstage-y += smi.c ramstage-y += smmrelocate.c -ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c @@ -77,14 +73,12 @@ smm-y += pch.c smm-y += pmutil.c smm-y += smihandler.c -smm-$(CONFIG_SPI_FLASH_SMM) += spi.c smm-$(CONFIG_UART_DEBUG) += uart_debug.c smm-y += uart.c postcar-y += memmap.c postcar-$(CONFIG_UART_DEBUG) += uart_debug.c postcar-y += gspi.c -postcar-y += spi.c # cpu_microcode_bins += ??? diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c deleted file mode 100644 index e575e6e..0000000 --- a/src/soc/intel/skylake/spi.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/spi.h> -#include <intelblocks/fast_spi.h> -#include <intelblocks/gspi.h> -#include <soc/ramstage.h> -#include <spi-generic.h> - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, -#if !ENV_SMM - { .ctrlr = &gspi_ctrlr, .bus_start = 1, - .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)}, -#endif -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); - -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) - -static int spi_dev_to_bus(struct device *dev) -{ - return spi_devfn_to_bus(dev->path.pci.devfn); -} - -static struct spi_bus_operations spi_bus_ops = { - .dev_to_bus = &spi_dev_to_bus, -}; - -static struct device_operations spi_dev_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_generic_bus, - .ops_pci = &soc_pci_ops, - .ops_spi_bus = &spi_bus_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d24, 0x9d29, 0x9d2a, 0 -}; - -static const struct pci_driver pch_spi __pci_driver = { - .ops = &spi_dev_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -#endif -- To view, visit https://review.coreboot.org/22361 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3 Gerrit-Change-Number: 22361 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common SPI support
by Subrata Banik (Code Review) 07 Nov '17

07 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22360 Change subject: soc/intel/common/block: Add Intel common SPI support ...................................................................... soc/intel/common/block: Add Intel common SPI support SOC need to select specific macros need to compile common SPI code. Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/spi/Kconfig A src/soc/intel/common/block/spi/Makefile.inc A src/soc/intel/common/block/spi/spi.c 3 files changed, 98 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/22360/1 diff --git a/src/soc/intel/common/block/spi/Kconfig b/src/soc/intel/common/block/spi/Kconfig new file mode 100644 index 0000000..bebb87a --- /dev/null +++ b/src/soc/intel/common/block/spi/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_SPI + bool + help + Intel Processor common SPI support + diff --git a/src/soc/intel/common/block/spi/Makefile.inc b/src/soc/intel/common/block/spi/Makefile.inc new file mode 100644 index 0000000..9c71d64 --- /dev/null +++ b/src/soc/intel/common/block/spi/Makefile.inc @@ -0,0 +1,14 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c + +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c + +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c + +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c + +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c +endif + diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c new file mode 100644 index 0000000..7671ab9 --- /dev/null +++ b/src/soc/intel/common/block/spi/spi.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/spi.h> +#include <intelblocks/fast_spi.h> +#include <intelblocks/gspi.h> +#include <soc/pci_devs.h> +#include <spi-generic.h> + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, +#if !ENV_SMM && IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) + { .ctrlr = &gspi_ctrlr, .bus_start = 1, + .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)}, +#endif +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); + +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) + +static int spi_dev_to_bus(struct device *dev) +{ + return spi_devfn_to_bus(dev->path.pci.devfn); +} + +static struct spi_bus_operations spi_bus_ops = { + .dev_to_bus = &spi_dev_to_bus, +}; + +static struct device_operations spi_dev_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_generic_bus, + .ops_spi_bus = &spi_bus_ops, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_SPI1, + PCI_DEVICE_ID_INTEL_SPT_SPI2, + PCI_DEVICE_ID_INTEL_SPT_SPI3, + PCI_DEVICE_ID_INTEL_APL_SPI0, + PCI_DEVICE_ID_INTEL_APL_SPI1, + PCI_DEVICE_ID_INTEL_APL_SPI2, + PCI_DEVICE_ID_INTEL_APL_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_GLK_SPI0, + PCI_DEVICE_ID_INTEL_GLK_SPI1, + PCI_DEVICE_ID_INTEL_GLK_SPI2, + PCI_DEVICE_ID_INTEL_CNL_SPI0, + PCI_DEVICE_ID_INTEL_CNL_SPI1, + PCI_DEVICE_ID_INTEL_CNL_SPI2, + PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI, + 0 +}; + +static const struct pci_driver pch_spi __pci_driver = { + .ops = &spi_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; +#endif -- To view, visit https://review.coreboot.org/22360 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c Gerrit-Change-Number: 22360 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY
by Patrick Georgi (Code Review) 07 Nov '17

07 Nov '17

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/22356 ) Change subject: siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY ...................................................................... siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY For internal measurements this mainboard needs a marking inside the NC FPGA when coreboot is ready and payload has been loaded. Change-Id: I37908b21e2a077dec7fa99b0db6d1fd9b6878341 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/22356 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/siemens/mc_apl1/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index bcdbb4f..ae86894 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -11,6 +11,7 @@ select DRIVERS_I2C_RX6110SA select DRIVERS_UART_8250IO select APL_SKIP_SET_POWER_LIMITS + select NC_FPGA_NOTIFY_CB_READY config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/22356 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I37908b21e2a077dec7fa99b0db6d1fd9b6878341 Gerrit-Change-Number: 22356 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY
by Patrick Georgi (Code Review) 07 Nov '17

07 Nov '17

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/22356 ) Change subject: siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/22356 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I37908b21e2a077dec7fa99b0db6d1fd9b6878341 Gerrit-Change-Number: 22356 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Nov 2017 12:34:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: add nhlt support
by build bot (Jenkins) (Code Review) 07 Nov '17

07 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22325 ) Change subject: mb/google/poppy/variants/nautilus: add nhlt support ...................................................................... Patch Set 2: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/63072/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/18024/ : SUCCESS -- To view, visit https://review.coreboot.org/22325 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09 Gerrit-Change-Number: 22325 Gerrit-PatchSet: 2 Gerrit-Owner: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Nov 2017 11:14:23 +0000 Gerrit-HasComments: No

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