coreboot-gerrit October 2017

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Change in coreboot[master]: soc/amd/stoneyridge: Replace magic registers
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21767 ) Change subject: soc/amd/stoneyridge: Replace magic registers ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61412/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16548/ : SUCCESS -- To view, visit https://review.coreboot.org/21767 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9187ba1c41ebb1201ddc177e8184672c60cd5f5d Gerrit-Change-Number: 21767 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 15:33:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/ite/common: Add temperature offset
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21843 ) Change subject: superio/ite/common: Add temperature offset ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61410/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16546/ : SUCCESS -- To view, visit https://review.coreboot.org/21843 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4 Gerrit-Change-Number: 21843 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 15:25:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/ite/common: Add temperature limits
by Vagiz Tarkhanov (Code Review) 02 Oct '17

02 Oct '17

Vagiz Tarkhanov has uploaded this change for review. ( https://review.coreboot.org/21844 Change subject: superio/ite/common: Add temperature limits ...................................................................... superio/ite/common: Add temperature limits Add devicetree options to set temperature limits that are used to alarm user when temperature exceeds defined values. Audio alerts by superio are not implemented yet, but since limits are visible to userland, some software might use them as is. For instance, lm-sensors displays "ALERT" when temperature exceeds limits. Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9 Signed-off-by: Vagiz Tarkhanov <rakkin(a)autistici.org> --- M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/21844/1 diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 5f216c1..696285f 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -127,6 +127,12 @@ ite_ec_write(base, ITE_EC_BEEP_ENABLE, reg); ite_ec_write(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); + /* Set temperature limits */ + u8 max = conf->max; + ite_ec_write(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), + max ? max : 127); + ite_ec_write(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min); + /* Enable the startup of monitoring operation */ reg = ite_ec_read(base, ITE_EC_CONFIGURATION); reg |= ITE_EC_CONFIGURATION_START; diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 1be6436..64603c6 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -86,6 +86,9 @@ #define ITE_EC_FAN_CTL_TEMPIN_MASK (3 << 0) #define ITE_EC_FAN_CTL_TEMPIN(x) (((x)-1) & 3) +#define ITE_EC_HIGH_TEMP_LIMIT(x) (0x40 + ((x-1) * 2)) +#define ITE_EC_LOW_TEMP_LIMIT(x) (0x41 + ((x-1) * 2)) + #define ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE 0x50 #define ITE_EC_ADC_TEMP_CHANNEL_ENABLE 0x51 #define ITE_EC_ADC_TEMP_EXT_REPORTS_TO(x) (((x) & 3) << 6) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index a1bb89d..e4c4eaa 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -32,6 +32,9 @@ enum ite_ec_thermal_mode mode; /* Offset is used for diode sensors and PECI */ u8 offset; + /* Limits */ + u8 min; + u8 max; }; /* Bit mask for voltage pins VINx */ -- To view, visit https://review.coreboot.org/21844 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9 Gerrit-Change-Number: 21844 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org>

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Change in coreboot[master]: superio/ite/common: Add temperature offset
by Vagiz Tarkhanov (Code Review) 02 Oct '17

02 Oct '17

Vagiz Tarkhanov has uploaded this change for review. ( https://review.coreboot.org/21843 Change subject: superio/ite/common: Add temperature offset ...................................................................... superio/ite/common: Add temperature offset Add devicetree options to set temperature adjustment registers required for thermal diode sensors and PECI. Without these adjustmets thermal diode sensors and PECI display raw values. For PECI it means negative temperatures. I'd gladly update TMPINx shorthands to FANx format, but many boards already assume that TMPINx set mode. Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4 Signed-off-by: Vagiz Tarkhanov <rakkin(a)autistici.org> --- M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h 3 files changed, 47 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/21843/1 diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1e313ce..5f216c1 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -99,13 +99,13 @@ * into TMPINx register */ static void enable_tmpin(const u16 base, const u8 tmpin, - const enum ite_ec_thermal_mode mode) + const struct ite_ec_thermal_config *const conf) { u8 reg; reg = ite_ec_read(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE); - switch (mode) { + switch (conf->mode) { case THERMAL_DIODE: reg |= ITE_EC_ADC_TEMP_DIODE_MODE(tmpin); break; @@ -115,11 +115,17 @@ default: printk(BIOS_WARNING, "Unsupported thermal mode 0x%x on TMPIN%d\n", - mode, tmpin); + conf->mode, tmpin); return; } ite_ec_write(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg); + + /* Set temperature offsets */ + reg = ite_ec_read(base, ITE_EC_BEEP_ENABLE); + reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; + ite_ec_write(base, ITE_EC_BEEP_ENABLE, reg); + ite_ec_write(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); /* Enable the startup of monitoring operation */ reg = ite_ec_read(base, ITE_EC_CONFIGURATION); @@ -233,7 +239,7 @@ /* Enable HWM if configured */ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) - enable_tmpin(base, i + 1, conf->tmpin_mode[i]); + enable_tmpin(base, i + 1, &conf->tmpin[i]); /* Enable reading of voltage pins */ ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index fa13116..1be6436 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -93,6 +93,26 @@ #define ITE_EC_ADC_TEMP_DIODE_MODE(x) (1 << ((x)-1)) #define ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE 0x55 +/* Matches length of ITE_EC_TMPIN_CNT */ +static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; + +#define ITE_EC_BEEP_ENABLE 0x5C +#define ITE_EC_TEMP_ADJUST_WRITE_ENABLE (1 << 7) +#define ITE_EC_ADC_CLOCK_1MHZ (6 << 4) +#define ITE_EC_ADC_CLOCK_2MHZ (7 << 4) +#define ITE_EC_ADC_CLOCK_24MHZ (5 << 4) +#define ITE_EC_ADC_CLOCK_31KHZ (4 << 4) +#define ITE_EC_ADC_CLOCK_62KHZ (3 << 4) +#define ITE_EC_ADC_CLOCK_125KHZ (2 << 4) +#define ITE_EC_ADC_CLOCK_250KHZ (1 << 4) +#define ITE_EC_ADC_CLOCK_500KHZ (0 << 4) +#define ITE_EC_BEEP_ON_TMP_LIMIT (1 << 2) +#define ITE_EC_BEEP_ON_VIN_LIMIT (1 << 1) +#define ITE_EC_BEEP_ON_FAN_LIMIT (1 << 0) +#define ITE_EC_BEEP_FREQ_DIV_OF_FAN 0x5D +#define ITE_EC_BEEP_FREQ_DIV_OF_VOLT 0x5E +#define ITE_EC_BEEP_FREQ_DIV_OF_TEMP 0x5F + #define ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(x) (0x60 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TEMP_LIMIT_START(x) (0x61 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(x) (0x62 + ((x)-1) * 8) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index f01c574..a1bb89d 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -28,6 +28,12 @@ THERMAL_RESISTOR, }; +struct ite_ec_thermal_config { + enum ite_ec_thermal_mode mode; + /* Offset is used for diode sensors and PECI */ + u8 offset; +}; + /* Bit mask for voltage pins VINx */ enum ite_ec_voltage_pin { VIN0 = 0x01, @@ -74,25 +80,28 @@ u8 peci_tmpin; /* - * Enable thermal mode on TMPINx. - */ - enum ite_ec_thermal_mode tmpin_mode[ITE_EC_TMPIN_CNT]; - - /* * Enable reading of voltage pins VINx. */ enum ite_ec_voltage_pin vin_mask; /* + * Enable temperature sensors in given mode. + */ + struct ite_ec_thermal_config tmpin[ITE_EC_TMPIN_CNT]; + + /* * Enable a FAN in given mode. */ struct ite_ec_fan_config fan[ITE_EC_FAN_CNT]; + + /* FIXME: enable beep when exceeding TMPIN, VIN, FAN limits */ }; /* Some shorthands for device trees */ -#define TMPIN1 ec.tmpin_mode[0] -#define TMPIN2 ec.tmpin_mode[1] -#define TMPIN3 ec.tmpin_mode[2] +#define TMPIN1 ec.tmpin[0].mode +#define TMPIN2 ec.tmpin[1].mode +#define TMPIN3 ec.tmpin[2].mode + #define FAN1 ec.fan[0] #define FAN2 ec.fan[1] #define FAN3 ec.fan[2] -- To view, visit https://review.coreboot.org/21843 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4 Gerrit-Change-Number: 21843 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org>

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Change in coreboot[master]: nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21841 ) Change subject: nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61409/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16545/ : SUCCESS -- To view, visit https://review.coreboot.org/21841 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3 Gerrit-Change-Number: 21841 Gerrit-PatchSet: 2 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 14:50:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs
by Arthur Heymans (Code Review) 02 Oct '17

02 Oct '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21841 ) Change subject: nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/21841/1/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit.c: https://review.coreboot.org/#/c/21841/1/src/northbridge/intel/sandybridge/r… PS1, Line 238: spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); maybe only apply Kconfig condition on this line? It's still useful to know from the debug message if your setup is in principle not supported. -- To view, visit https://review.coreboot.org/21841 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3 Gerrit-Change-Number: 21841 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 13:57:55 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21841 ) Change subject: nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61408/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16544/ : SUCCESS -- To view, visit https://review.coreboot.org/21841 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3 Gerrit-Change-Number: 21841 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 13:56:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs
by Vagiz Tarkhanov (Code Review) 02 Oct '17

02 Oct '17

Vagiz Tarkhanov has uploaded this change for review. ( https://review.coreboot.org/21841 Change subject: nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs ...................................................................... nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs XMP profiles can have a restriction on max supported DIMMs per channel, but many configurations work with more DIMMs. This is relevant on mainboards with 2 DIMM slots per channel (usually 4 in total). Populating both slots with DIMMs that support XMP profiles only with 1 DIMM per channel turns off said XMP profiles. Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3 Signed-off-by: Vagiz Trakhanov <rakkin(a)autistici.org> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/21841/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 1a47f0d..5ffb796 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -54,6 +54,15 @@ Disabled by default as it might causes system instability. Handle with care! +config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS + bool "Ignore XMP profile max DIMMs per channel" + default n + depends on USE_NATIVE_RAMINIT + help + Ignore the max DIMMs per channel restriciton defined in XMP profiles. + Disabled by default as it might causes system instability. + Handle with care! + config CBFS_SIZE hex default 0x100000 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index bdba748..6e4d63f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -230,7 +230,8 @@ if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { printram("No valid XMP profile found.\n"); spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); - } else if (dimms_on_channel > dimm->dimm[channel][slot].dimms_per_channel) { + } else if ((dimms_on_channel > dimm->dimm[channel][slot].dimms_per_channel) + && !IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) { printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", dimm->dimm[channel][slot].dimms_per_channel, dimms_on_channel); -- To view, visit https://review.coreboot.org/21841 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3 Gerrit-Change-Number: 21841 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org>

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Change in coreboot[master]: buildgcc: Update IASL to 20170831
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21156 ) Change subject: buildgcc: Update IASL to 20170831 ...................................................................... Patch Set 5: Build Unstable https://qa.coreboot.org/job/coreboot-toolchain/373/ : UNSTABLE https://qa.coreboot.org/job/coreboot-gerrit/61406/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16542/ : SUCCESS -- To view, visit https://review.coreboot.org/21156 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c14f3aad59749896816bb8789788fc513e7176f Gerrit-Change-Number: 21156 Gerrit-PatchSet: 5 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 11:18:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: buildgcc: Update GCC to 7.2.0
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20809 ) Change subject: buildgcc: Update GCC to 7.2.0 ...................................................................... Patch Set 7: Build Unstable https://qa.coreboot.org/job/coreboot-toolchain/371/ : UNSTABLE https://qa.coreboot.org/job/coreboot-gerrit/61405/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16540/ : SUCCESS -- To view, visit https://review.coreboot.org/20809 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I85ee0efc6497ba8a38f6295e30524c90c689d909 Gerrit-Change-Number: 20809 Gerrit-PatchSet: 7 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Anonymous Coward #1001719 Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: guqr Gerrit-Comment-Date: Mon, 02 Oct 2017 10:02:24 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017