coreboot-gerrit October 2017

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Change in coreboot[master]: autoport/bd82x6x.go: Improve gpio.c generation
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19508 ) Change subject: autoport/bd82x6x.go: Improve gpio.c generation ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61419/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16552/ : SUCCESS -- To view, visit https://review.coreboot.org/19508 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 Gerrit-Change-Number: 19508 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 17:34:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: autoport: Add GPL boilerplate header to not empty .c files
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19510 ) Change subject: autoport: Add GPL boilerplate header to not empty .c files ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61420/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16553/ : SUCCESS -- To view, visit https://review.coreboot.org/19510 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d6b48762b1249bb0becb178a30e1396bf6978fc Gerrit-Change-Number: 19510 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 17:33:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Wait for UART to be ready
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21731 ) Change subject: soc/amd/stoneyridge: Wait for UART to be ready ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61418/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16551/ : SUCCESS -- To view, visit https://review.coreboot.org/21731 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676 Gerrit-Change-Number: 21731 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 17:32:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Add new USB currents
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21845 ) Change subject: sb/intel/bd82x6x: Add new USB currents ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61416/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16549/ : SUCCESS -- To view, visit https://review.coreboot.org/21845 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I547c4ab3a2ce507d013ed527ab81291a916ce9b5 Gerrit-Change-Number: 21845 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 17:17:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard: Add Gigabyte GA-Z77-DS3H support
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21846 ) Change subject: mainboard: Add Gigabyte GA-Z77-DS3H support ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/61417/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/16550/ : SUCCESS -- To view, visit https://review.coreboot.org/21846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90fef8b7a1181c2f6481e834d1aa342905b85f1e Gerrit-Change-Number: 21846 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 17:12:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard: Add Gigabyte GA-Z77-DS3H support
by Vagiz Tarkhanov (Code Review) 02 Oct '17

02 Oct '17

Vagiz Tarkhanov has uploaded this change for review. ( https://review.coreboot.org/21846 Change subject: mainboard: Add Gigabyte GA-Z77-DS3H support ...................................................................... mainboard: Add Gigabyte GA-Z77-DS3H support What was tested: native ram and vga init, booting, suspend/resume, pcie and pci slots, video, audio, COM port, PS/2 keyboard, virtualization, pci pass-through, one out of two EHCI controllers, xHCI, fan and thermal sensors in superio. There is one remanining issue: EHCI is buggy. With my Wacom tablet attached GRUB registers phantom key presses, but in Linux the tablet works fine. Also, in Linux if a keyboard and a mouse attached simultaneously, the mouse is unresponsive. Workaround: attach mice and/or keyboards to xHCI because xHCI is stable. This commit depends on the ability to set temperature offsets and limits in ite superio. Change-Id: I90fef8b7a1181c2f6481e834d1aa342905b85f1e Signed-off-by: Vagiz Trakhanov <rakkin(a)autistici.org> --- A src/mainboard/gigabyte/ga-z77-ds3h/Kconfig A src/mainboard/gigabyte/ga-z77-ds3h/Kconfig.name A src/mainboard/gigabyte/ga-z77-ds3h/Makefile.inc A src/mainboard/gigabyte/ga-z77-ds3h/acpi/ec.asl A src/mainboard/gigabyte/ga-z77-ds3h/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z77-ds3h/acpi/platform.asl A src/mainboard/gigabyte/ga-z77-ds3h/acpi/superio.asl A src/mainboard/gigabyte/ga-z77-ds3h/acpi/thermal.asl A src/mainboard/gigabyte/ga-z77-ds3h/acpi/video.asl A src/mainboard/gigabyte/ga-z77-ds3h/acpi_tables.c A src/mainboard/gigabyte/ga-z77-ds3h/board_info.txt A src/mainboard/gigabyte/ga-z77-ds3h/cmos.default A src/mainboard/gigabyte/ga-z77-ds3h/cmos.layout A src/mainboard/gigabyte/ga-z77-ds3h/devicetree.cb A src/mainboard/gigabyte/ga-z77-ds3h/dsdt.asl A src/mainboard/gigabyte/ga-z77-ds3h/gma-mainboard.ads A src/mainboard/gigabyte/ga-z77-ds3h/gpio.c A src/mainboard/gigabyte/ga-z77-ds3h/hda_verb.c A src/mainboard/gigabyte/ga-z77-ds3h/mainboard.c A src/mainboard/gigabyte/ga-z77-ds3h/romstage.c A src/mainboard/gigabyte/ga-z77-ds3h/thermal.h 21 files changed, 1,251 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/21846/1 diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig b/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig new file mode 100644 index 0000000..3cd99ac --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig @@ -0,0 +1,67 @@ +if BOARD_GIGABYTE_GA_Z77_DS3H + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA1155 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select INTEL_INT15 + select SERIRQ_CONTINUOUS_MODE + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select TPM + +config DRAM_RESET_GATE_GPIO + int + default 25 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + string + default gigabyte/ga-z77-ds3h + +config MAINBOARD_PART_NUMBER + string + default "GA-Z77-DS3H" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x5001 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config MAX_CPUS + int + default 8 + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config IFD_BIOS_SECTION + string + default "0x00300000:0x007fffff" + +config IFD_ME_SECTION + string + default "0x00001000:0x002fffff" + +endif # BOARD_GIGABYTE_GA_Z77_DS3H diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig.name b/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig.name new file mode 100644 index 0000000..65b3f3f --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_Z77_DS3H + bool "GA-Z77-DS3H" diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/Makefile.inc b/src/mainboard/gigabyte/ga-z77-ds3h/Makefile.inc new file mode 100644 index 0000000..a8846b6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/mainboard.asl new file mode 100644 index 0000000..34de86f --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/mainboard.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/platform.asl new file mode 100644 index 0000000..0603164 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/platform.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/superio.asl new file mode 100644 index 0000000..78bf687 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/superio.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/thermal.asl new file mode 100644 index 0000000..61ea07c --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/thermal.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 2 seconds + Name (_TZP, 20) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi/video.asl b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/video.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi/video.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/acpi_tables.c b/src/mainboard/gigabyte/ga-z77-ds3h/acpi_tables.c new file mode 100644 index 0000000..532242f --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/acpi_tables.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/board_info.txt b/src/mainboard/gigabyte/ga-z77-ds3h/board_info.txt new file mode 100644 index 0000000..fc1c7e1 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4147#sp +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/cmos.default b/src/mainboard/gigabyte/ga-z77-ds3h/cmos.default new file mode 100644 index 0000000..767372c --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/cmos.default @@ -0,0 +1,8 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +sata_mode=AHCI +hyper_threading=Enable diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/cmos.layout b/src/mainboard/gigabyte/ga-z77-ds3h/cmos.layout new file mode 100644 index 0000000..ebc7c42 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/devicetree.cb b/src/mainboard/gigabyte/ga-z77-ds3h/devicetree.cb new file mode 100644 index 0000000..b9e9a02 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/devicetree.cb @@ -0,0 +1,176 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Vagiz Tarkhanov <rakkin(a)autistici.org> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA1155 + device lapic 0 on end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on # Host Bridge + subsystemid 0x1458 0x5000 + end + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on # Integrated graphics + subsystemid 0x1458 0xd000 + end + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + register "alt_gp_smi_en" = "0x0000" + register "gen1_dec" = "0x003c0a01" + + # Set max SATA speed to 6.0 Gb/s + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + + register "pcie_port_coalesce" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "p_cnt_throttling_supported" = "0" + register "docking_supported" = "0" + register "c2_latency" = "0x0065" + + register "xhci_overcurrent_mapping" = "0x00000c03" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_switchable_ports" = "0x0000000f" + + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1458 0x5007 + end + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on # PCIe Port #3, Atheros AR8161 Gbe + subsystemid 0x1458 0xe000 + end + device pci 1c.3 on end # PCI Bridge + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device pci 1e.0 off end # PCI Bridge + device pci 1f.0 on # ISA/LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8728f + register "ec.vin_mask" = "VIN_ALL" + register "TMPIN1" = "THERMAL_RESISTOR" + register "TMPIN2" = "THERMAL_RESISTOR" + register "TMPIN3" = "THERMAL_DIODE" + register "ec.peci_tmpin" = "3" + # PECI is calculated by substracting from this offset + register "ec.tmpin[2].offset" = "97" + # Temperature at which superio raises the alarm + register "ec.tmpin[2].max" = "85" + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "0" + register "FAN1.smart.tmp_start" = "20" + register "FAN1.smart.tmp_full" = "60" + register "FAN1.smart.tmp_delta" = "2" + register "FAN1.smart.pwm_start" = "50" + register "FAN1.smart.slope" = "1" + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = "3" + register "FAN2.smart.tmp_off" = "0" + register "FAN2.smart.tmp_start" = "20" + register "FAN2.smart.tmp_full" = "60" + register "FAN2.smart.tmp_delta" = "2" + register "FAN2.smart.pwm_start" = "50" + register "FAN2.smart.slope" = "1" + register "FAN3.mode" = "FAN_SMART_AUTOMATIC" + register "FAN3.smart.tmpin" = "3" + register "FAN3.smart.tmp_off" = "0" + register "FAN3.smart.tmp_start" = "20" + register "FAN3.smart.tmp_full" = "60" + register "FAN3.smart.tmp_delta" = "2" + register "FAN3.smart.pwm_start" = "50" + register "FAN3.smart.slope" = "1" + + #FIXME: add FAN4 + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # Serial Port 2 + device pnp 2e.3 off end # Parallel Port + device pnp 2e.4 on # EC + io 0x60 = 0xa30 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0xf0 = 8 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # IR + end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMBus + subsystemid 0x1458 0x5001 + end + device pci 1f.4 off end + device pci 1f.5 off end # SATA Controller 2 + end + end +end diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/dsdt.asl b/src/mainboard/gigabyte/ga-z77-ds3h/dsdt.asl new file mode 100644 index 0000000..75f2efe --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/dsdt.asl @@ -0,0 +1,29 @@ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } +} diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/gma-mainboard.ads b/src/mainboard/gigabyte/ga-z77-ds3h/gma-mainboard.ads new file mode 100644 index 0000000..2b88265 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/gma-mainboard.ads @@ -0,0 +1,15 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/gpio.c b/src/mainboard/gigabyte/ga-z77-ds3h/gpio.c new file mode 100644 index 0000000..3d4342e --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/gpio.c @@ -0,0 +1,434 @@ +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_NO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/hda_verb.c b/src/mainboard/gigabyte/ga-z77-ds3h/hda_verb.c new file mode 100644 index 0000000..253ec08 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/hda_verb.c @@ -0,0 +1,8 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/mainboard.c b/src/mainboard/gigabyte/ga-z77-ds3h/mainboard.c new file mode 100644 index 0000000..97cc46f --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/mainboard.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_init(device_t dev) +{ +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/romstage.c b/src/mainboard/gigabyte/ga-z77-ds3h/romstage.c new file mode 100644 index 0000000..81c5ded --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/romstage.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2017 Vagiz Tarkhanov <rakkin(a)autistici.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_BASE 0x2e + +#define GPIO_DEV PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, IT8728F_SP1) + +#include <superio/ite/it8728f/it8728f.h> +#include <superio/ite/common/ite.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <drivers/uart/uart8250reg.h> + + +static void it8728f_z77ds3h_disable_reboot(pnp_devfn_t dev) +{ + /* protect dual bios */ + ite_reg_write(dev, 0xEF, 0x7E); + + /* booting with coreboot gives 0x40 while vendor sets 0x00 */ + ite_reg_write(dev, 0x25, 0x00); + /* simple iobase 0xa00 */ + ite_reg_write(dev, 0x62, 0x0a); + /* clear watchdog timeout */ + ite_reg_write(dev, 0x73, 0x00); + /* enable generation of SMI# due to EC's IRQ */ + ite_reg_write(dev, 0xf0, 0x10); + /* hardware monitor alert beep -> gp36(pin12)*/ + ite_reg_write(dev, 0xf6, 0x1c); +} + +void rcba_config(void) +{ + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17e01fe3; + + /* Enable HECI */ + RCBA32(FD2) &= ~0x2; +} + +void pch_enable_lpc(void) +{ + /* + * Enable: + * EC Decode Range PortA30/A20 + * SuperIO Port2E/2F + * PS/2 Keyboard/Mouse Port60/64 + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN + | CNF1_LPC_EN | COMA_LPC_EN); + + /* GPIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8728f_z77ds3h_disable_reboot(GPIO_DEV); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 6, 0 }, // f53 - current + { 1, 6, 0 }, // f53 + { 1, 1, 1 }, // f57 + { 1, 7, 1 }, // 357 + { 1, 1, 2 }, // f57 + { 1, 1, 2 }, // f57 + { 1, 8, 3 }, // 353 + { 1, 8, 3 }, // 353 + { 1, 6, 4 }, // f53 + { 1, 6, 4 }, // f53 + { 1, 6, 6 }, // f53 + { 1, 1, 5 }, // f57 + { 1, 1, 5 }, // f57 + { 1, 6, 6 }, // f53 +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + /* Aparantly the COMA port is booted in an undefined state in which + * the divisor is very high. In console_init() some functions are + * called which print to the console resulting in very long + * (up to 30s) boot delays. + * Setting the Baudrate Divisor Latch Access Bit (BDLAB) here fixes it. + */ + if (CONFIG_TTYS0_BASE == 0x3f8) + outb(UART8250_LCR_DLAB, CONFIG_TTYS0_BASE + UART8250_LCR); +} diff --git a/src/mainboard/gigabyte/ga-z77-ds3h/thermal.h b/src/mainboard/gigabyte/ga-z77-ds3h/thermal.h new file mode 100644 index 0000000..3791f32 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z77-ds3h/thermal.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GAZ77DS3H_THERMAL_H +#define GAZ77DS3H_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 97 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 85 + +#endif -- To view, visit https://review.coreboot.org/21846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I90fef8b7a1181c2f6481e834d1aa342905b85f1e Gerrit-Change-Number: 21846 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org>

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Change in coreboot[master]: sb/intel/bd82x6x: Add new USB currents
by Vagiz Tarkhanov (Code Review) 02 Oct '17

02 Oct '17

Vagiz Tarkhanov has uploaded this change for review. ( https://review.coreboot.org/21845 Change subject: sb/intel/bd82x6x: Add new USB currents ...................................................................... sb/intel/bd82x6x: Add new USB currents These currents were found on Gigabyte GA-Z77-DS3H with vendor bios. Change-Id: I547c4ab3a2ce507d013ed527ab81291a916ce9b5 Signed-off-by: Vagiz Tarkhanov <rakkin(a)autistici.org> --- M src/southbridge/intel/bd82x6x/early_usb.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/21845/1 diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 339a835..473fa01 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -29,7 +29,9 @@ /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, 0x2000094a, 0x2000035f }; + const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, + 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, + 0x20000353}; int i; /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); -- To view, visit https://review.coreboot.org/21845 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I547c4ab3a2ce507d013ed527ab81291a916ce9b5 Gerrit-Change-Number: 21845 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org>

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Change in coreboot[master]: cpu/x86: Align stack in SIPI handler
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21768 ) Change subject: cpu/x86: Align stack in SIPI handler ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61415/ : SUCCESS -- To view, visit https://review.coreboot.org/21768 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibdd8242494c6a2bc0c6ead7ac98be55149219d7c Gerrit-Change-Number: 21768 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 16:21:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Remove preprocessor #if
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21770 ) Change subject: soc/amd/stoneyridge/southbridge.c: Remove preprocessor #if ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61414/ : SUCCESS -- To view, visit https://review.coreboot.org/21770 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4 Gerrit-Change-Number: 21770 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 16:11:00 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: superio/ite/common: Add temperature limits
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21844 ) Change subject: superio/ite/common: Add temperature limits ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61411/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16547/ : SUCCESS -- To view, visit https://review.coreboot.org/21844 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9 Gerrit-Change-Number: 21844 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 15:37:43 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017