coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: src/soc: Remove unnecessary whitespace before "\n" and "\t"
by gerrit＠coreboot.org 28 Aug '16

28 Aug '16

the following patch was just integrated into master: commit 03b040b95f1a16d07b98e15c1aeef77ec7a4eca9 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Aug 25 21:11:45 2016 +0200 src/soc: Remove unnecessary whitespace before "\n" and "\t" Change-Id: I89bc8b26f2dba4770aea14b8bbc7e657355e8c59 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16325 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16325 for details. -gerrit

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New patch to review for coreboot: nyan-blaze: Correct indentation for sdram configs
by Paul Kocialkowski 28 Aug '16

28 Aug '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16342 -gerrit commit 86dbab59157375af827b115dffea49892533feef Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Sun Aug 28 17:39:11 2016 +0200 nyan-blaze: Correct indentation for sdram configs This corrects indentation for sdram configs in nyan_blaze. Change-Id: Ia9ad2a37c6e3b79e1260f490db893244c32685b6 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/mainboard/google/nyan_blaze/sdram_configs.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.c b/src/mainboard/google/nyan_blaze/sdram_configs.c index ffc9b8c..b4f2a8e 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.c +++ b/src/mainboard/google/nyan_blaze/sdram_configs.c @@ -19,18 +19,18 @@ #include "sdram_configs.h" static struct sdram_params sdram_configs[] = { -#include "bct/sdram-hynix-2GB-792.inc" /* ram_code = 0000 */ +#include "bct/sdram-hynix-2GB-792.inc" /* ram_code = 0000 */ #include "bct/sdram-micron-2GB-792.inc" /* ram_code = 0001 */ -#include "bct/sdram-samsung-2GB-792.inc" /* ram_code = 0010 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0011 */ -#include "bct/sdram-micron-2GB-792.inc" /* ram_code = 0100 */ -#include "bct/sdram-hynix-C-2GB-792.inc" /* ram_code = 0101 */ +#include "bct/sdram-samsung-2GB-792.inc" /* ram_code = 0010 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0011 */ +#include "bct/sdram-micron-2GB-792.inc" /* ram_code = 0100 */ +#include "bct/sdram-hynix-C-2GB-792.inc" /* ram_code = 0101 */ #include "bct/sdram-unused.inc" /* ram_code = 0110 */ #include "bct/sdram-unused.inc" /* ram_code = 0111 */ -#include "bct/sdram-hynix-4GB-792.inc" /* ram_code = 1000 */ -#include "bct/sdram-micron-4GB-792.inc" /* ram_code = 1001 */ -#include "bct/sdram-samsung-4GB-792.inc" /* ram_code = 1010 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1011 */ +#include "bct/sdram-hynix-4GB-792.inc" /* ram_code = 1000 */ +#include "bct/sdram-micron-4GB-792.inc" /* ram_code = 1001 */ +#include "bct/sdram-samsung-4GB-792.inc" /* ram_code = 1010 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1011 */ #include "bct/sdram-unused.inc" /* ram_code = 1100 */ #include "bct/sdram-unused.inc" /* ram_code = 1101 */ #include "bct/sdram-unused.inc" /* ram_code = 1110 */

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Patch set updated for coreboot: util/intelmetool: Add bootguard information dump support
by Philipp Deppenwiese 28 Aug '16

28 Aug '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16328 -gerrit commit 15f717c41e215fe17fcd1f3359911cd2c230aa68 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Aug 26 02:10:51 2016 +0200 util/intelmetool: Add bootguard information dump support With this implementation it's possible to detect the state of bootguard in intel based systems. Currently it's WIP and in a testphase. Handle it with care! Change-Id: Ifeec8e20fa8efc35d7db4c6a84be1f118dccfc4a Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- util/intelmetool/Makefile | 2 +- util/intelmetool/intelmetool.c | 224 ++++++++++++++++++++++++++++------------- util/intelmetool/intelmetool.h | 9 +- util/intelmetool/me.c | 14 +-- util/intelmetool/me.h | 2 + util/intelmetool/mmap.c | 4 - util/intelmetool/msr.c | 78 ++++++++++++++ util/intelmetool/msr.h | 43 ++++++++ 8 files changed, 288 insertions(+), 88 deletions(-) diff --git a/util/intelmetool/Makefile b/util/intelmetool/Makefile index 4461f86..4ea5c0f 100644 --- a/util/intelmetool/Makefile +++ b/util/intelmetool/Makefile @@ -20,7 +20,7 @@ PREFIX ?= /usr/local CFLAGS ?= -O0 -g -Wall -W -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-sign-compare -Wno-unused-function LDFLAGS += -lpci -lz -OBJS = intelmetool.o me.o me_status.o mmap.o +OBJS = intelmetool.o me.o me_status.o mmap.o msr.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index aec0715..724ce5a 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -16,6 +16,8 @@ #include <stdlib.h> #include <getopt.h> #include <unistd.h> +#include <string.h> +#include <cpuid.h> #ifdef __NetBSD__ #include <machine/sysarch.h> @@ -23,17 +25,22 @@ #include "me.h" #include "mmap.h" +#include "msr.h" #include "intelmetool.h" -#define FD2 0x3428 -#define ME_COMMAND_DELAY 10000 - extern int fd_mem; int debug = 0; static uint32_t fd2 = 0; static const int size = 0x4000; static volatile uint8_t *rcba; +static char cpu_id[CPU_ID_SIZE] = { 0 }; + +void print_cap(const char *name, int state) +{ + printf("ME Capability: %-30s : %s\n", + name, state ? CRED "ON" RESET : CGRN "OFF" RESET); +} static void dumpmem(uint8_t *phys, uint32_t size) { @@ -72,6 +79,16 @@ static void rehide_me() { } } +static void get_cpu_id(char *id) { + cpu_t cpu; + unsigned int level = 0; + unsigned int eax = 0; + + __get_cpuid(level, &eax, &cpu.ebx, &cpu.ecx, &cpu.edx); + + memcpy(id, (char*)&cpu, CPU_ID_SIZE); +} + /* You need >4GB total ram, in kernel cmdline, use 'mem=1000m' * then this code will clone to absolute memory address 0xe0000000 * which can be read using a mmap tool at that offset. @@ -80,10 +97,14 @@ static void rehide_me() { */ static void dump_me_memory() { uint32_t me_clone = 0x60000000; - uint8_t *dump; + void *dump; dump = map_physical_exact(me_clone, me_clone, 0x2000000); - zeroit(dump, 0x2000000); + if(!dump) { + printf("ME physical memory can't be mapped!! Take a look at DMESG log.\n"); + return; + } + zeroit((uint8_t*)dump, 0x2000000); printf("Send magic command for memory clone\n"); mei_reset(); @@ -95,7 +116,7 @@ static void dump_me_memory() { printf("Wait a second..."); usleep(ME_COMMAND_DELAY); printf("done\n\nHere are the first bytes:\n"); - dumpmemfile(dump, 0x2000000); + dumpmemfile((uint8_t*)dump, 0x2000000); //printf("Try reading 0x%zx with other mmap tool...\n" // "Press enter to quit, you only get one chance to run this tool before reboot required for some reason\n", me_clone); while (getc(stdin) != '\n') {}; @@ -103,10 +124,9 @@ static void dump_me_memory() { } } -static int pci_platform_scan() { +static int pci_platform_scan(char* msg) { struct pci_access *pacc; struct pci_dev *dev; - char namebuf[1024], *name; pacc = pci_alloc(); pacc->method = PCI_ACCESS_I386_TYPE1; @@ -116,38 +136,28 @@ static int pci_platform_scan() { for (dev=pacc->devices; dev; dev=dev->next) { pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_SIZES | PCI_FILL_CLASS); - name = pci_lookup_name(pacc, namebuf, sizeof(namebuf), - PCI_LOOKUP_DEVICE, dev->vendor_id, dev->device_id); - if (dev->vendor_id == 0x8086) { + if (dev->vendor_id == INTEL_PLATFORM_VENDOR_ID) { if (PCI_DEV_HAS_ME_DISABLE(dev->device_id)) { - printf(CGRN "Good news, you have a `%s` so ME is present but can be disabled, continuing...\n\n" RESET, name); + snprintf(msg, ME_MESSAGE_LEN, CGRN "Good news, your ME is present but can be disabled, continuing...\n\n" RESET); break; } else if (PCI_DEV_HAS_ME_DIFFICULT(dev->device_id)) { - printf(CRED "Bad news, you have a `%s` so you have ME hardware on board and you can't control or disable it, continuing...\n\n" RESET, name); + snprintf(msg, ME_MESSAGE_LEN, CRED "Bad news, you have ME hardware on board but you can't control or disable it, continuing...\n\n" RESET); break; } else if (PCI_DEV_CAN_DISABLE_ME_IF_PRESENT(dev->device_id)) { - printf(CYEL "Not sure if ME hardware is present because you have a `%s`, but it is possible to disable it if you do, continuing...\n\n" RESET, name); + snprintf(msg, ME_MESSAGE_LEN, CYEL "Not sure if ME hardware is present, but it is possible to disable it if you do, continuing...\n\n" RESET); break; } else if (PCI_DEV_ME_NOT_SURE(dev->device_id)) { - printf(CYEL "Found `%s`. Not sure whether you have ME hardware, exiting\n\n" RESET, name); - pci_cleanup(pacc); - return 1; + snprintf(msg, ME_MESSAGE_LEN, CYEL "Not sure whether you have ME hardware, exiting\n\n" RESET); break; } } } - if (!PCI_DEV_HAS_ME_DISABLE(dev->device_id) && - !PCI_DEV_HAS_ME_DIFFICULT(dev->device_id) && - !PCI_DEV_CAN_DISABLE_ME_IF_PRESENT(dev->device_id) && - !PCI_DEV_ME_NOT_SURE(dev->device_id)) { - printf(CCYN "ME is not present on your board or unkown\n\n" RESET); - pci_cleanup(pacc); - return 1; + if(!dev) { + snprintf(msg, ME_MESSAGE_LEN, CCYN "ME is not present on your board or unkown\n\n" RESET); } pci_cleanup(pacc); - return 0; } @@ -166,7 +176,7 @@ static struct pci_dev *pci_me_interface_scan(char **name) { for (dev=pacc->devices; dev; dev=dev->next) { pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_SIZES | PCI_FILL_CLASS); *name = pci_lookup_name(pacc, namebuf, sizeof(namebuf), - PCI_LOOKUP_DEVICE, dev->vendor_id, dev->device_id); + PCI_LOOKUP_DEVICE, dev->vendor_id, dev->device_id); if (dev->vendor_id == 0x8086) { if (PCI_DEV_HAS_SUPPORTED_ME(dev->device_id)) { me = 1; @@ -206,17 +216,23 @@ static int activate_me() { pci_fill_info(sb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_SIZES | PCI_FILL_CLASS); rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; - rcba = map_physical(rcba_phys, size); + void* map = map_physical(rcba_phys, size); + if(!map) { + return 1; + } else { + rcba = (uint8_t*)map; + } //printf("RCBA at 0x%08" PRIx32 "\n", (uint32_t)rcba_phys); fd2 = *(uint32_t *)(rcba + FD2); *(uint32_t *)(rcba + FD2) = fd2 & ~0x2; - if (fd2 & 0x2) { - printf("MEI was hidden on PCI, now unlocked\n"); - } else { - printf("MEI not hidden on PCI, checking if visible\n"); + if (debug) { + if (fd2 & 0x2) { + printf("MEI was hidden on PCI, now unlocked\n"); + } else { + printf("MEI not hidden on PCI, checking if visible\n"); + } } - pci_cleanup(pacc); return 0; @@ -225,9 +241,9 @@ static int activate_me() { static void dump_me_info() { struct pci_dev *dev; uint32_t stat, stat2; - char *name; + char *name, msg[ME_MESSAGE_LEN] = { 0 }; - if (pci_platform_scan()) { + if (pci_platform_scan(msg)) { exit(1); } @@ -236,10 +252,9 @@ static void dump_me_info() { exit(1); } - if (activate_me()) { - exit(1); - } + activate_me(); + printf("%s", msg); printf("MEI found: [%x:%x] %s\n\n", dev->vendor_id, dev->device_id, name); stat = pci_read_long(dev, 0x40); printf("ME Status : 0x%x\n", stat); @@ -271,10 +286,62 @@ static void dump_me_info() { munmap((void*)rcba, size); } +static void dump_bootguard_info() { + struct pci_dev *dev; + uint32_t stat = 0; + char *name, msg[ME_MESSAGE_LEN] = { 0 }; + uint64_t bootguard = 0; + + if(msr_bootguard(&bootguard, debug) < 0) { + return; + } + + pci_platform_scan(msg); + dev = pci_me_interface_scan(&name); + activate_me(); + + if(dev) { + stat = pci_read_long(dev, 0x40); + } + + if(debug) { + printf("BootGuard MSR Output: 0x%" PRIx64 "\n", bootguard); + bootguard &= ~0xff; + } + + if(BOOTGUARD_CAPABILITY(bootguard)) { + print_cap("BootGuard ", 1); + if (dev && (stat & 0x10)) { + printf(CYEL "Your southbridge configuration is insecure!! BootGuard keys can be overwritten or wiped or you are in developer mode.\n" RESET); + } + switch(bootguard) { + case BOOTGUARD_DISABLED: + printf("ME Capability: BootGuard Mode : " CGRN "Disabled\n" RESET); + printf(CGRN "\nYour system is bootguard ready but your vendor disabled it. You can flash other firmware!\n" RESET); + break; + case BOOTGUARD_ENABLED_COMBI_MODE: + printf("ME Capability: BootGuard Mode : " CRED "Verified & Measured Boot\n" RESET); + printf(CRED "\nYou can't flash other firmware. Verified boot is enabled!\n" RESET); + break; + case BOOTGUARD_ENABLED_MEASUREMENT_MODE: + printf("ME Capability: BootGuard Mode : " CGRN "Measured Boot\n" RESET); + printf(CGRN "\nYour system is bootguard ready but only running the measured boot mode. You can flash other firmware!\n" RESET); + break; + case BOOTGUARD_ENABLED_VERIFIED_MODE: + printf("ME Capability: BootGuard Mode : " CRED "Verified Boot\n" RESET); + printf(CRED "\nYou can't flash other firmware. Verified boot is enabled!\n" RESET); + break; + } + } else { + print_cap("BootGuard ", 0); + printf(CGRN "\nYour system isn't bootguard ready. You can flash other firmware!\n" RESET); + } +} + static void print_version(void) { printf("intelmetool v%s -- ", INTELMETOOL_VERSION); - printf("Copyright (C) 2015 Damien Zammit\n\n"); + printf("Copyright (C) 2016 Damien Zammit, Philipp Deppenwiese\n\n"); printf( "This program is free software: you can redistribute it and/or modify\n" "it under the terms of the GNU General Public License as published by\n" @@ -287,13 +354,14 @@ static void print_version(void) static void print_usage(const char *name) { - printf("usage: %s [-vh?sd]\n", name); + printf("usage: %s [-vh?mdb]\n", name); printf("\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" - " -s | --show: dump all me information on console\n" - " -d | --debug: enable debug output\n" - "\n"); + " -v | --version print the version\n" + " -h | --help print this help\n\n" + " -m | --me dump all me related information on console\n" + " -b | --bootguard dump bootguard state of the platform\n" + " -d | --debug enable debug output\n" + "\n"); exit(1); } @@ -305,21 +373,25 @@ int main(int argc, char *argv[]) static struct option long_options[] = { {"version", 0, 0, 'v'}, {"help", 0, 0, 'h'}, - {"show", 0, 0, 's'}, + {"me", 0, 0, 'm'}, + {"bootguard", 0, 0, 'b'}, {"debug", 0, 0, 'd'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?sd", - long_options, &option_index)) != EOF) { - switch (opt) { + while ((opt = getopt_long(argc, argv, "vh?mdb", + long_options, &option_index)) != EOF) { + switch (opt) { case 'v': print_version(); exit(0); break; - case 's': + case 'm': cmd_exec = 1; break; + case 'b': + cmd_exec = 2; + break; case 'd': debug = 1; break; @@ -329,42 +401,52 @@ int main(int argc, char *argv[]) print_usage(argv[0]); exit(0); break; - } } + } #if defined(__FreeBSD__) - if (open("/dev/io", O_RDWR) < 0) { - perror("/dev/io"); + if (open("/dev/io", O_RDWR) < 0) { + perror("/dev/io"); #elif defined(__NetBSD__) # ifdef __i386__ - if (i386_iopl(3)) { - perror("iopl"); + if (i386_iopl(3)) { + perror("iopl"); # else - if (x86_64_iopl(3)) { - perror("iopl"); + if (x86_64_iopl(3)) { + perror("iopl"); # endif #else - if (iopl(3)) { - perror("iopl"); + if (iopl(3)) { + perror("iopl"); #endif - printf("You need to be root.\n"); - exit(1); - } + printf("You need to be root.\n"); + exit(1); + } #ifndef __DARWIN__ - if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { - perror("Can not open /dev/mem"); - exit(1); - } + if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { + perror("Can not open /dev/mem"); + exit(1); + } + + get_cpu_id(cpu_id); + if(strncmp(cpu_id, "GenuineIntel", CPU_ID_SIZE-1)) { + perror("Error CPU is not from Intel."); + exit(1); + } #endif switch(cmd_exec) { - case 1: - dump_me_info(); - break; - default: - print_usage(argv[0]); - break; + case 1: + dump_me_info(); + break; + case 2: + dump_bootguard_info(); + break; + default: + dump_me_info(); + dump_bootguard_info(); + break; } return 0; diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index 4b9803b..bd6dcf4 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -22,7 +22,7 @@ #define ME_PRESENT_CAN_DISABLE 4 #define ME_PRESENT_CANNOT_DISABLE 5 -#define INTELMETOOL_VERSION "1.0" +#define INTELMETOOL_VERSION "1.1" #if defined(__GLIBC__) #include <sys/io.h> @@ -48,7 +48,14 @@ #define CWHT "\x1B[37m" #define RESET "\033[0m" +#define CPU_ID_SIZE 13 +#define FD2 0x3428 +#define ME_COMMAND_DELAY 10000 +#define ME_MESSAGE_LEN 256 +#define INTEL_PLATFORM_VENDOR_ID 0x8086 + extern int debug; +extern void print_cap(const char *name, int state); // Definitely has ME and can be disabled #define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811 diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index da5fb71..0313132 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -420,12 +420,6 @@ int mkhi_get_fw_version(void) return 0; } -static inline void print_cap(const char *name, int state) -{ - printf("ME Capability: %-30s : %s\n", - name, state ? "ON" : "OFF"); -} - /* Get ME Firmware Capabilities */ int mkhi_get_fwcaps(void) { @@ -463,12 +457,10 @@ int mkhi_get_fwcaps(void) print_cap("Small business technology ", fwcaps.cap.caps_sku.small_business); print_cap("Level III manageability ", fwcaps.cap.caps_sku.l3manageability); print_cap("IntelR Anti-Theft (AT) ", fwcaps.cap.caps_sku.intel_at); - print_cap("IntelR Capability Licensing Service (CLS) ", - fwcaps.cap.caps_sku.intel_cls); - print_cap("IntelR Power Sharing Technology (MPC) ", - fwcaps.cap.caps_sku.intel_mpc); + print_cap("IntelR Capability Licensing Service (CLS) ", fwcaps.cap.caps_sku.intel_cls); + print_cap("IntelR Power Sharing Technology (MPC) ", fwcaps.cap.caps_sku.intel_mpc); print_cap("ICC Over Clocking ", fwcaps.cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP) ", fwcaps.cap.caps_sku.pavp); + print_cap("Protected Audio Video Path (PAVP) ", fwcaps.cap.caps_sku.pavp); print_cap("IPV6 ", fwcaps.cap.caps_sku.ipv6); print_cap("KVM Remote Control (KVM) ", fwcaps.cap.caps_sku.kvm); print_cap("Outbreak Containment Heuristic (OCH) ", fwcaps.cap.caps_sku.och); diff --git a/util/intelmetool/me.h b/util/intelmetool/me.h index 76ee245..d0f4252 100644 --- a/util/intelmetool/me.h +++ b/util/intelmetool/me.h @@ -20,6 +20,8 @@ #include <inttypes.h> #include <pci/pci.h> +#include "intelmetool.h" + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ diff --git a/util/intelmetool/mmap.c b/util/intelmetool/mmap.c index da36eaa..bf3c378 100644 --- a/util/intelmetool/mmap.c +++ b/util/intelmetool/mmap.c @@ -28,8 +28,6 @@ void *map_physical_exact(uint64_t phys_addr, uint64_t mapto, size_t len) { if (virt_addr == MAP_FAILED) { err = errno; - printf("Error mapping physical memory 0x%016" PRIx64 "[0x%zx] ERRNO=%d\n", - phys_addr, len, err); return NULL; } @@ -44,8 +42,6 @@ void *map_physical(uint64_t phys_addr, size_t len) { if (virt_addr == MAP_FAILED) { err = errno; - printf("Error mapping physical memory 0x%016" PRIx64 "[0x%zx] ERRNO=%d\n", - phys_addr, len, err); return NULL; } diff --git a/util/intelmetool/msr.c b/util/intelmetool/msr.c new file mode 100644 index 0000000..0274b6a --- /dev/null +++ b/util/intelmetool/msr.c @@ -0,0 +1,78 @@ +/* intelmetool + * + * Copyright (C) 2013-2016 Philipp Deppenwiese <zaolin(a)das-labor.org>, Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fcntl.h> +#include <unistd.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> + +#include "msr.h" + +#ifndef __DARWIN__ +static int fd_msr = 0; + +static uint64_t rdmsr(int addr) +{ + uint32_t buf[2]; + uint64_t msr = 0; + + if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { + perror("Could not lseek() to MSR"); + close(fd_msr); + return -1; + } + + if (read(fd_msr, buf, 8) == 8) { + msr = buf[1]; + msr <<= 32; + msr |= buf[0]; + close(fd_msr); + return msr; + } + + if (errno == EIO) { + close(fd_msr); + return -2; + } else { + perror("Could not read() MSR"); + close(fd_msr); + return -1; + } + + return msr; +} +#endif + +int msr_bootguard(uint64_t *msr, int debug) { + +#ifndef __DARWIN__ + fd_msr = open("/dev/cpu/0/msr", O_RDONLY); + if (fd_msr < 0) { + perror("Error while opening /dev/cpu/0/msr"); + printf("Did you run 'modprobe msr'?\n"); + return -1; + } + + *msr = rdmsr(MSR_BOOTGUARD); +#endif + + if(!debug) { + *msr &= ~0xff; + } + + return 0; +} diff --git a/util/intelmetool/msr.h b/util/intelmetool/msr.h new file mode 100644 index 0000000..b46a8da --- /dev/null +++ b/util/intelmetool/msr.h @@ -0,0 +1,43 @@ +/* intelmetool + * + * Copyright (C) 2013-2016 Philipp Deppenwiese <zaolin(a)das-labor.org>, Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <inttypes.h> +#include <stdlib.h> +#include <fcntl.h> +#include <sys/mman.h> +#include <stdio.h> + +#define MSR_BOOTGUARD 0x13A + +#define BOOTGUARD_DISABLED 0x400000000 +#define BOOTGUARD_ENABLED_VERIFIED_MODE 0x100000000 +#define BOOTGUARD_ENABLED_MEASUREMENT_MODE 0x200000000 +#define BOOTGUARD_ENABLED_COMBI_MODE 0x300000000 +#define BOOTGUARD_CAPABILITY(x) ( \ + ( (x) == BOOTGUARD_DISABLED ) || \ + ( (x) == BOOTGUARD_ENABLED_VERIFIED_MODE ) || \ + ( (x) == BOOTGUARD_ENABLED_MEASUREMENT_MODE ) || \ + ( (x) == BOOTGUARD_ENABLED_COMBI_MODE )) + +#ifndef __DARWIN__ + +typedef struct { + unsigned int ebx; + unsigned int edx; + unsigned int ecx; +} cpu_t; + +extern int msr_bootguard(uint64_t *msr, int debug); +#endif

1 0

Patch set updated for coreboot: soc/intel/skylake: Include Kabylake specific IGD Device IDs
by Barnali Sarkar 27 Aug '16

27 Aug '16

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16329 -gerrit commit 98e2d7b52c7f73fa400d8b88aad58e69794e2e1d Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Fri Aug 26 14:48:46 2016 +0530 soc/intel/skylake: Include Kabylake specific IGD Device IDs Add Kabylake specific Graphics IDs in report_platform.c and igd.c. BUG=none BRANCH=none TEST=Built and boot kunimitsu Change-Id: I3b810d0ff51eb51d396b783e282779aefb2dcb8c Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/skylake/bootblock/report_platform.c | 3 +++ src/soc/intel/skylake/igd.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 2610940..f10159f 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -66,6 +66,9 @@ static struct { { IGD_SKYLAKE_GT1_SULTM, "Skylake ULT GT1"}, { IGD_SKYLAKE_GT2_SULXM, "Skylake ULX GT2" }, { IGD_SKYLAKE_GT2_SULTM, "Skylake ULT GT2" }, + { IGD_KABYLAKE_GT1_SULTM, "Kabylake ULT GT1"}, + { IGD_KABYLAKE_GT2_SULXM, "Kabylake ULX GT2" }, + { IGD_KABYLAKE_GT2_SULTM, "Kabylake ULT GT2" }, }; static void report_cpu_info(void) diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index 3e29ab0..a8ac645 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -209,6 +209,9 @@ static const unsigned short pci_device_ids[] = { IGD_SKYLAKE_GT1_SULTM, IGD_SKYLAKE_GT2_SULXM, IGD_SKYLAKE_GT2_SULTM, + IGD_KABYLAKE_GT1_SULTM, + IGD_KABYLAKE_GT2_SULXM, + IGD_KABYLAKE_GT2_SULTM, 0, };

1 0

New patch to review for coreboot: nb/gm45/gma.c: enable VESA framebuffer mode on VGA output
by Arthur Heymans 27 Aug '16

27 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16338 -gerrit commit 2ef2553600c16b94124d87f09150af1bbbe3f86c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Aug 27 01:09:19 2016 +0200 nb/gm45/gma.c: enable VESA framebuffer mode on VGA output This implements "Keep VESA framebuffer" behavior on VGA output of gm45. Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 250 ++++++++++++++++++++++++++++++++------- 1 file changed, 206 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index ad887b9..e4e38cf 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -345,14 +345,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, } static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - u8 *mmio) + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { int i; - u32 hactive, vactive; + u8 edid_data[128]; + struct edid edid; + struct edid_mode *mode; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 target_frequency; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + vga_gr_write(0x18, 0); + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + write32(mmio + VGA0, 0x31108); write32(mmio + VGA1, 0x31406); @@ -363,8 +387,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + 0x7041c, 0x0); write32(mmio + DPLL_MD(0), 0x3); @@ -382,25 +405,136 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); + udelay(1); + + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); + decode_edid(edid_data, + sizeof(edid_data), &edid); + mode = &edid.mode; + + /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); - hactive = 640; - vactive = 400; + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + target_frequency = 2 * mode->pixel_clock; + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } + + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } + + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) + / (link_frequency * 8 * 4); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); mdelay(1); - write32(mmio + FP0(0), 0x31108); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + FP0(0), ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | (pixel_m2 - 2)); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); + mdelay(1); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT @@ -409,49 +543,68 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); - + | ADPA_DPMS_ON); write32(mmio + HTOTAL(0), - ((hactive - 1) << 16) + ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); write32(mmio + HBLANK(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); write32(mmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); - write32(mmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive - 1) << 16) + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); write32(mmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1)); write32(mmio + PIPECONF(0), PIPECONF_DISABLE); write32(mmio + PF_WIN_POS(0), 0); - - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) + | (vactive - 1)); + write32(mmio + PF_CTL(0), 0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0x80000000); + } mdelay(1); + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + write32(mmio + 0x000f000c, 0x00002040); mdelay(1); write32(mmio + 0x000f000c, 0x00002050); write32(mmio + 0x00060100, 0x00044000); mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6); + write32(mmio + 0x000f0008, 0x00000040); + write32(mmio + 0x000f000c, 0x00022050); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + VGACNTRL, 0x0); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + VGACNTRL, VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + mdelay(1); + } else { + write32(mmio + VGACNTRL, 0xc4008e); + } write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT @@ -462,24 +615,32 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON ); + write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - vga_textmode_init(); - - /* Enable screen memory. */ + /* Enable screen memory. */ vga_sr_write(1, vga_sr_read(1) & ~0x20); /* Clear interrupts. */ write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset((void *) lfb, 0, + edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } + + } -/* compare the header of the vga edid header - if vga is not connected it should not have a correct header */ +/* compare the header of the vga edid header */ +/* if vga is not connected it should not have a correct header */ static u8 vga_connected(u8 *mmio) { u8 vga_edid[128]; u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); + intel_gmbus_stop(mmio + GMBUS0); for (int i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_SPEW, "VGA not connected. Using LVDS display\n"); @@ -566,7 +727,8 @@ static void gma_func0_init(struct device *dev) "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); if (vga_connected(res2mmio(gtt_res, 0, 0))) - gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); + gma_init_vga(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); else gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), physbase, pio_res->base, lfb_res->base);

1 0

Patch set updated for coreboot: gm45/gma.c: clean up some registers
by Arthur Heymans 27 Aug '16

27 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16217 -gerrit commit c827d458ab09e2d8ca2e8f72d67fd84759787d69 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Aug 15 00:04:34 2016 +0200 gm45/gma.c: clean up some registers According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" some registries are set incorrectly in gm45/gma.c. Some values are changed after comparing them with the values the i915 linux kernel (3.13 was used) module sets while modesetting. The values were obtained using 'intel_reg' from intel-gpu-tools, during a normal boot and with 'nomodeset' as a kernel argument. Some registers that don't exist on gm45 are set in gma.c, which is probably the result of copying code from a more recent intel northbridge. The result is that that gm45 laptops with wxga displays still work as before. gm45 laptops with wxga+ or higher resolution now just work, where previously a black screen was shown. TEST: build with native graphic init and flash on a gm45 target, like lenovo x200. Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 110 +++++++-------------------------------- 1 file changed, 18 insertions(+), 92 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index a89f9bb..b02c89b 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -47,60 +47,6 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -static void power_port(u8 *mmio) -{ - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - write32(mmio + 0x00061100, 0x00010000); - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - read32(mmio + 0x00061100); // = 0x00000000 - read32(mmio + 0x00064200); // = 0x0000001c - write32(mmio + 0x00064210, 0x8004003e); - write32(mmio + 0x00064214, 0x80060002); - write32(mmio + 0x00064218, 0x01000000); - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - write32(mmio + 0x00064f00, 0x0100030c); - write32(mmio + 0x00064f04, 0x00b8230c); - write32(mmio + 0x00064f08, 0x06f8930c); - write32(mmio + 0x00064f0c, 0x09f8e38e); - write32(mmio + 0x00064f10, 0x00b8030c); - write32(mmio + 0x00064f14, 0x0b78830c); - write32(mmio + 0x00064f18, 0x0ff8d3cf); - write32(mmio + 0x00064f1c, 0x01e8030c); - write32(mmio + 0x00064f20, 0x0ff863cf); - write32(mmio + 0x00064f24, 0x0ff803cf); - write32(mmio + 0x000c4030, 0x00001000); - read32(mmio + 0x00044000); // = 0x00000000 - write32(mmio + 0x00044030, 0x00001000); - read32(mmio + 0x00061150); // = 0x0000001c - write32(mmio + 0x00061150, 0x0000089c); - write32(mmio + 0x000fcc00, 0x01986f00); - write32(mmio + 0x000fcc0c, 0x01986f00); - write32(mmio + 0x000fcc18, 0x01986f00); - write32(mmio + 0x000fcc24, 0x01986f00); - read32(mmio + 0x00044000); // = 0x00000000 - read32(mmio + LVDS); // = 0x40000002 -} - static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { @@ -150,8 +96,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); - power_port(mmio); - intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128); decode_edid(edid_data, sizeof(edid_data), &edid); @@ -277,28 +221,32 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + | LVDS_ENABLE_DITHER + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_PIPE(0)); mdelay(1); write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(mmio + FP0(0), ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); + | ((pixel_m1 - 2) << 8) | (pixel_m2 - 2)); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | DPLL_VGA_MODE_DIS | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); + | (6 << 9)); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | DPLL_VGA_MODE_DIS | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); + | (6 << 9)); /* Re-lock the registers. */ write32(mmio + PP_CONTROL, (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); @@ -307,7 +255,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_ENABLE_DITHER + | LVDS_PIPE(0)); write32(mmio + HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) @@ -324,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1)); write32(mmio + VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) | (vactive + bottom_border + vfront_porch - 1)); write32(mmio + PIPECONF(0), PIPECONF_DISABLE); @@ -335,7 +285,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | (vactive - 1)); write32(mmio + PF_CTL(0), 0); write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PFIT_CONTROL, 0x20000000); + write32(mmio + PFIT_CONTROL, 0); } else { write32(mmio + PIPESRC(0), (639 << 16) | 399); write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); @@ -362,7 +312,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { - write32(mmio + VGACNTRL, 0xc4008e | VGA_DISP_DISABLE); + write32(mmio + VGACNTRL, VGA_DISP_DISABLE); write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); mdelay(1); @@ -370,37 +320,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + VGACNTRL, 0xc4008e); } - write32(mmio + TRANS_HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + TRANS_HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + TRANS_HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + TRANS_VTOTAL(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + TRANS_VBLANK(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + TRANS_VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + 0x00060100, 0xb01c4000); - write32(mmio + 0x000f000c, 0xb01a2050); - mdelay(1); - write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC - ); - write32(mmio + LVDS, - LVDS_PORT_ENABLE + write32(mmio + LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_ENABLE_DITHER + | LVDS_PIPE(0)); write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);

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Patch set updated for coreboot: gm45/gma.c: use screen on vga connector if connected
by Arthur Heymans 27 Aug '16

27 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16295 -gerrit commit dbfc82ef2b1aad50f039b8cb3b029d9f4253d131 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Aug 22 17:58:46 2016 +0200 gm45/gma.c: use screen on vga connector if connected The intel x4x native graphic init works on gm45 to use the vga screen instead of the integrated lvds screen. This patch integrates it in gm45 in a way that the behavior is similar to vbios: If no vga display is connected the internal lvds screen is used. If an external screen is detected on the vga port it will be used instead. Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 155 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 152 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index b02c89b..ad887b9 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -static void intel_gma_init(const struct northbridge_intel_gm45_config *info, +static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { @@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, } } +static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + u8 *mmio) +{ + + int i; + u32 hactive, vactive; + + vga_gr_write(0x18, 0); + + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); + write32(mmio + DPLL_MD(1), 0x3); + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = 640; + vactive = 400; + + mdelay(1); + write32(mmio + FP0(0), 0x31108); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + HTOTAL(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HSYNC(0), + ((hactive - 1) << 16) + | (hactive - 1)); + + write32(mmio + VTOTAL(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VSYNC(0), + ((vactive - 1) << 16) + | (vactive - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); + + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + + mdelay(1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + write32(mmio + VGACNTRL, 0x0); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + vga_textmode_init(); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); +} + +/* compare the header of the vga edid header + if vga is not connected it should not have a correct header */ +static u8 vga_connected(u8 *mmio) +{ + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_SPEW, "VGA not connected. Using LVDS display\n"); + return 0; + } + } + printk(BIOS_SPEW, "VGA display connected\n"); + return 1; +} + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) + gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); } /* Linux relies on VBT for panel info. */

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Patch merged into coreboot/master: rockchip/rk3399: Enable ramstage compression, shuffle around memlayout
by gerrit＠coreboot.org 27 Aug '16

27 Aug '16

the following patch was just integrated into master: commit eb131f30a3c1bf56d24b1bea2bc2a77d458843ff Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Jul 29 12:30:50 2016 -0700 rockchip/rk3399: Enable ramstage compression, shuffle around memlayout Since we now have so much more room for activities in our romstage SRAM section, we can easily fit the LZMA decompressor to enable ramstage compression. Also shuffle around memlayout sections a little more to make use of unused space, and balance out leftover memory so that all sections that might need future expansion have a reasonable amount. Change-Id: I47f2d03e520fc3103ef04257b4ba7e93874b8956 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16334 for details. -gerrit

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Patch merged into coreboot/master: gru: Make SDRAM parameters individual struct files in CBFS
by gerrit＠coreboot.org 27 Aug '16

27 Aug '16

the following patch was just integrated into master: commit 329031fdedb332f75b2d3ce6c165bb62d9631600 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Aug 19 16:35:22 2016 -0700 gru: Make SDRAM parameters individual struct files in CBFS This patch changes Gru SDRAM parameters from structures that just get compiled into the romstage to individual CBFS files. This allows us to only load the parameter set we need for the board we're booting from flash, which reduces our boot time and the SRAM memory footprint required to hold the romstage. TEST=Booted Kevin. Change-Id: Ie88a515cbdb19a794ca0a230a56bcc82bed1e550 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16274 for details. -gerrit

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Patch merged into coreboot/master: cbmem: Always maintain backing store struct in a global on non-x86
by gerrit＠coreboot.org 27 Aug '16

27 Aug '16

the following patch was just integrated into master: commit 3c814b2e2b8e053da352f4746a4914fb43af09d7 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Aug 19 16:20:40 2016 -0700 cbmem: Always maintain backing store struct in a global on non-x86 The current CBMEM code contains an optimization that maintains the structure with information about the CBMEM backing store in a global variable, so that we don't have to recover it from cbmem_top() again every single time we access CBMEM. However, due to the problems with using globals in x86 romstage, this optimization has only been enabled in ramstage. However, all non-x86 platforms are SRAM-based (at least for now) and can use globals perfectly fine in earlier stages. Therefore, this patch extends the optimization on those platforms to all stages. This also allows us to remove the requirement that cbmem_top() needs to return NULL before its backing store has been initialized from those boards, since the CBMEM code can now keep track of whether it has been initialized by itself. Change-Id: Ia6c1db00ae01dee485d5e96e4315cb399dc63696 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16273 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16273 for details. -gerrit

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coreboot-gerrit August 2016