the following patch was just integrated into master:
commit 6e5421d2a887737fc7c8a916d54151f9b1706f6d
Author: Timothy Pearson <tpearson(a)raptorengineering.com>
Date: Tue Aug 23 15:41:05 2016 -0500
sb/amd/sb700: Add option to increase SPI speed to 33MHz
Some SB700-based systems and ROMs support high speed (33MHz) SPI
access instead of the power-on default 16.5MHz. Add an option
to enable high speed SPI access in the bootblock, and set the
default value to Disabled. This greatly decreases boot time on
SB700-based systems, especiall when a large payload is in use.
On a KGPE-D16 with a Petitboot (Linux + initramfs) payload, the
command prompt was accessible within 20 seconds of power on, which
incidentally is faster than the proprietary BIOS on the same machine
could even reach the GRUB bootloader.
Change-Id: Iadbd9bb611754262ef75a5e5a6ee4390a46e45cf
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com>
Test: Booted KGPE-D16 with Linux payload
Reviewed-on: https://review.coreboot.org/16306
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16306 for details.
-gerrit
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16332
-gerrit
commit e234f4d2e3356df413abc676b8908b11b1563044
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Aug 26 21:16:01 2016 +0530
soc/intel/skylake: Use postcar functions for setting up new stack
Setup stack and MTRRs using the postcar funtions provided
in postcar_loader.c.
Change-Id: Ia5771e70386dbae9fa181e3635021dd187345123
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/soc/intel/skylake/romstage/romstage_fsp20.c | 50 +++++++++++++++++++++++--
1 file changed, 47 insertions(+), 3 deletions(-)
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 57b2a52..95ae060 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -24,16 +24,25 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <fsp/util.h>
+#include <fsp/memmap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <timestamp.h>
#include <vboot/vboot_common.h>
+/*
+ * Romstage needs some stack for decompressing ramstage images, since the lzma
+ * lib keeps its state on the stack during romstage.
+ */
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
asmlinkage void *car_stage_c_entry(void)
{
bool s3wake;
- void *top_of_stack;
+ struct postcar_frame pcf;
+
+ uintptr_t top_of_ram;
struct chipset_power_state *ps;
console_init();
@@ -46,8 +55,43 @@ asmlinkage void *car_stage_c_entry(void)
s3wake = ps->prev_sleep_state == ACPI_S3;
fsp_memory_init(s3wake);
- top_of_stack = setup_stack_and_mtrrs();
- return top_of_stack;
+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ die("Unable to initialize postcar frame.\n");
+
+ /*
+ * We need to make sure ramstage will be run cached. At this point exact
+ * location of ramstage in cbmem is not known. Instruct postcar to cache
+ * 16 megs under cbmem top which is a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+ /* cbmem_top() needs to be at least 16 MiB aligned */
+ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
+
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
+
+ if(IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ void *smm_base;
+ size_t smm_size;
+ uintptr_t tseg_base;
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is not
+ * restricted to SMM mode until SMM has been relocated. By setting
+ * the region to cacheable it provides faster access when relocating
+ * the SMM handler as well as using the TSEG region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ tseg_base = (uintptr_t)smm_base;
+ postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+ }
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, 16*MiB, MTRR_TYPE_WRPROT);
+ postcar_commit_mtrrs(&pcf);
+
+ printk(BIOS_DEBUG, "top_of_stack = 0x%lx\n", pcf.stack);
+ return (void *)pcf.stack;
}
static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16331
-gerrit
commit 9394065972f3cce869159210ad76ca3231845b1a
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Aug 26 21:08:50 2016 +0530
arch/x86: Make postcar library available irrespective of CONFIG_POSTCAR_STAGE
postcar_loader.c has a useful library of funtions for
setting up stack and MTRRs. Make it available in romstage
irrespective of CONFIG_POSTCAR_STAGE for use in stack setup
after Dram init.
Change-Id: I322b12577d74268d03fe42a9744648763693cddd
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/arch/x86/Makefile.inc | 2 +-
src/arch/x86/include/arch/cpu.h | 3 +++
src/arch/x86/postcar_loader.c | 17 +++++++++++------
3 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9b16add..38a2a8c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -213,7 +213,7 @@ romstage-y += memcpy.c
romstage-y += memmove.c
romstage-y += memset.c
romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-romstage-$(CONFIG_POSTCAR_STAGE) += postcar_loader.c
+romstage-y += postcar_loader.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ifneq ($(CONFIG_ROMCC),y)
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 5c26bcf..400e1ba 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -273,6 +273,9 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size);
void postcar_frame_add_mtrr(struct postcar_frame *pcf,
uintptr_t addr, size_t size, int type);
+/* Push used MTRR and Max MTRRs on to the stack */
+void postcar_commit_mtrrs(struct postcar_frame *pcf);
+
/*
* Load and run a program that takes control of execution that
* tears down CAR and loads ramstage. The postcar_frame object
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index cc1d460..7f27a7e 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -84,6 +84,16 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,
pcf->num_var_mttrs++;
}
+void postcar_commit_mtrrs(struct postcar_frame *pcf)
+{
+ /*
+ * Place the number of used variable MTRRs on stack then max number
+ * of variable MTRRs supported in the system.
+ */
+ stack_push(pcf, pcf->num_var_mttrs);
+ stack_push(pcf, pcf->max_var_mttrs);
+}
+
void run_postcar_phase(struct postcar_frame *pcf)
{
struct prog prog =
@@ -93,12 +103,7 @@ void run_postcar_phase(struct postcar_frame *pcf)
.prog = &prog,
};
- /*
- * Place the number of used variable MTRRs on stack then max number
- * of variable MTRRs supported in the system.
- */
- stack_push(pcf, pcf->num_var_mttrs);
- stack_push(pcf, pcf->max_var_mttrs);
+ postcar_commit_mtrrs(pcf);
if (prog_locate(&prog))
die("Failed to locate after CAR program.\n");
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16312
-gerrit
commit d64af5f17c587da1424148d510cd1ae0e43421d2
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Wed Aug 24 16:05:32 2016 +0530
driver/intel/fsp2.0: Add External stage cache region helper
If ramstage caching outside CBMEM is enabled
i.e CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM, then a
helper function to determine the caching region in SMM
should be implemented. Add the same to FSP2.0 driver.
FSP1.1 driver had the same implementation hence copied stage_cache.c.
The SoC code should implement the smm_subregion to provide
the base and size of the caching region within SMM. The fsp/memmap.h
provides the prototype and we will reuse the same from FPS 1.1.
Change-Id: I4412a710391dc0cee044b96403c50260c3534e6f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/drivers/intel/fsp2_0/Makefile.inc | 2 ++
src/drivers/intel/fsp2_0/include/fsp/memmap.h | 47 +++++++++++++++++++++++++++
src/drivers/intel/fsp2_0/stage_cache.c | 28 ++++++++++++++++
3 files changed, 77 insertions(+)
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 0a6ae43..79b57f6 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -23,6 +23,7 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
romstage-y += util.c
romstage-y += memory_init.c
+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-y += debug.c
ramstage-y += graphics.c
@@ -32,6 +33,7 @@ ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
ramstage-y += notify.c
ramstage-y += silicon_init.c
+ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-y += util.c
diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h
new file mode 100644
index 0000000..965bce6
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/include/fsp/memmap.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COMMON_MEMMAP_H_
+#define _COMMON_MEMMAP_H_
+
+#include <types.h>
+
+/*
+ * mmap_region_granularity must to return a size which is a positive non-zero
+ * integer multiple of the SMM size when SMM is in use. When not using SMM,
+ * this value should be set to 8 MiB.
+ */
+size_t mmap_region_granularity(void);
+
+/* Fills in the arguments for the entire SMM region covered by chipset
+ * protections. e.g. TSEG. */
+void smm_region(void **start, size_t *size);
+
+enum {
+ /* SMM handler area. */
+ SMM_SUBREGION_HANDLER,
+ /* SMM cache region. */
+ SMM_SUBREGION_CACHE,
+ /* Chipset specific area. */
+ SMM_SUBREGION_CHIPSET,
+ /* Total sub regions supported. */
+ SMM_SUBREGION_NUM,
+};
+
+/* Fills in the start and size for the requested SMM subregion. Returns
+ * 0 on susccess, < 0 on failure. */
+int smm_subregion(int sub, void **start, size_t *size);
+
+#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c
new file mode 100644
index 0000000..2d594e6
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/stage_cache.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/memmap.h>
+#include <stage_cache.h>
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+ printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
+ *base = NULL;
+ *size = 0;
+ }
+}
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16267
-gerrit
commit 93673ff0e0ee4765c721eba5c5646c5c74d2932f
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Tue Aug 23 14:31:23 2016 +0530
skylake: Add initial FSP2.0 support
Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.
The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.
Add the below files,
car_stage.S:
Add romstage entry point (car_stage_entry).
This calls into romstage_fsp20.c and aslo handles
the car teardown.
romstage_fsp20.c:
Call fsp_memory_init() and also has the callback
for filling memory init parameters.
Also add monotonic_timer.c to verstage.
With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.
TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0
Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/soc/intel/skylake/Kconfig | 1 +
src/soc/intel/skylake/Makefile.inc | 13 +-
src/soc/intel/skylake/chip_fsp20.c | 30 +++++
src/soc/intel/skylake/igd.c | 29 +----
src/soc/intel/skylake/include/fsp11/soc/ramstage.h | 36 ++++++
src/soc/intel/skylake/include/fsp11/soc/romstage.h | 30 +++++
src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 39 ++++++
src/soc/intel/skylake/include/fsp20/soc/romstage.h | 30 +++++
src/soc/intel/skylake/include/soc/ramstage.h | 31 -----
src/soc/intel/skylake/include/soc/romstage.h | 30 -----
src/soc/intel/skylake/include/soc/smm.h | 1 -
src/soc/intel/skylake/include/soc/vr_config.h | 9 +-
src/soc/intel/skylake/memmap.c | 1 -
src/soc/intel/skylake/opregion.c | 49 ++++++++
src/soc/intel/skylake/reset.c | 32 +++++
src/soc/intel/skylake/romstage/Makefile.inc | 5 +-
src/soc/intel/skylake/romstage/car_stage.S | 131 +++++++++++++++++++++
src/soc/intel/skylake/romstage/romstage_fsp20.c | 44 +++++++
src/soc/intel/skylake/vr_config.c | 27 +++--
19 files changed, 460 insertions(+), 108 deletions(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 6171c41..edf5db3 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
select RTC
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 716c3d5..aa3da61 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -40,12 +40,14 @@ romstage-y += pch.c
romstage-y += pcr.c
romstage-y += pei_data.c
romstage-y += pmutil.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += smbus_common.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-y += chip.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c
ramstage-y += cpu.c
ramstage-y += cpu_info.c
ramstage-y += dsp.c
@@ -59,12 +61,14 @@ ramstage-y += lpc.c
ramstage-y += me_status.c
ramstage-y += memmap.c
ramstage-y += monotonic_timer.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c
ramstage-y += pch.c
ramstage-y += pcie.c
ramstage-y += pcr.c
ramstage-y += pei_data.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-y += ramstage.c
ramstage-y += sd.c
ramstage-y += smbus.c
@@ -93,7 +97,14 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
+CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
+else
+CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake
+endif
# Currently used for microcode path.
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
new file mode 100644
index 0000000..215530c
--- /dev/null
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <chip.h>
+#include <bootstate.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd)
+{
+}
+
+struct pci_operations soc_pci_ops = {
+ /* TODO: Add set subsystem id function */
+};
+
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 3e29ab0..969f386 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -24,7 +24,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <drivers/intel/gma/i915_reg.h>
-#include <fsp/gop.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
#include <soc/pm.h>
@@ -117,35 +116,10 @@ static void igd_init(struct device *dev)
}
/* Initialize IGD OpRegion, called from ACPI code */
-static int init_igd_opregion(igd_opregion_t *opregion)
+static int update_igd_opregion(igd_opregion_t *opregion)
{
- const optionrom_vbt_t *vbt;
- uint32_t vbt_len;
u16 reg16;
- memset(opregion, 0, sizeof(igd_opregion_t));
-
- /* Read VBT table from flash */
- vbt = fsp_get_vbt(&vbt_len);
- if (!vbt)
- die("vbt data not found");
-
- memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
- sizeof(IGD_OPREGION_SIGNATURE) - 1);
- memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
- memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
- sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
- sizeof(opregion->vbt.gvd1));
-
- /* Size, in KB, of the entire OpRegion structure (including header)*/
- opregion->header.size = sizeof(igd_opregion_t) / KiB;
- opregion->header.version = IGD_OPREGION_VERSION;
-
- /* We just assume we're mobile for now */
- opregion->header.mailboxes = MAILBOXES_MOBILE;
-
- /* TODO Initialize Mailbox 1 */
-
/* Initialize Mailbox 3 */
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
@@ -189,6 +163,7 @@ static unsigned long write_acpi_igd_opregion(device_t device,
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
init_igd_opregion(opregion);
+ update_igd_opregion(opregion);
current += sizeof(igd_opregion_t);
current = acpi_align_current(current);
diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
new file mode 100644
index 0000000..e469554
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+#include <fsp/gop.h>
+#include <fsp/ramstage.h>
+#include <fsp/soc_binding.h>
+
+#define FSP_SIL_UPD SILICON_INIT_UPD
+#define FSP_MEM_UPD MEMORY_INIT_UPD
+
+void pch_enable_dev(device_t dev);
+void soc_init_pre_device(void *chip_info);
+void soc_init_cpus(device_t dev);
+const char *soc_acpi_name(struct device *dev);
+int init_igd_opregion(igd_opregion_t *igd_opregion);
+extern struct pci_operations soc_pci_ops;
+
+#endif
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
new file mode 100644
index 0000000..6c40bd6
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <fsp/romstage.h>
+
+void systemagent_early_init(void);
+void intel_early_me_status(void);
+void enable_smbus(void);
+int smbus_read_byte(unsigned device, unsigned address);
+
+int early_spi_read_wpsr(u8 *sr);
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
new file mode 100644
index 0000000..3a9d96b
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/intel/common/opregion.h>
+
+#define FSP_SIL_UPD struct FSP_S_CONFIG
+#define FSP_MEM_UPD struct FSP_M_CONFIG
+
+void intel_silicon_init(void);
+void mainboard_silicon_init_params(struct FSP_S_CONFIG *params);
+void pch_enable_dev(device_t dev);
+void soc_init_pre_device(void *chip_info);
+void soc_init_cpus(device_t dev);
+const char *soc_acpi_name(struct device *dev);
+
+extern struct pci_operations soc_pci_ops;
+
+#endif
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
new file mode 100644
index 0000000..d48ac67
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <arch/cpu.h>
+#include <fsp/api.h>
+
+asmlinkage void *car_stage_c_entry(void);
+void mainboard_memory_init_params(struct FSPM_UPD *mupd);
+
+void systemagent_early_init(void);
+int smbus_read_byte(unsigned device, unsigned address);
+int early_spi_read_wpsr(u8 *sr);
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h
deleted file mode 100644
index 55f9972..0000000
--- a/src/soc/intel/skylake/include/soc/ramstage.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_RAMSTAGE_H_
-#define _SOC_RAMSTAGE_H_
-
-#include <chip.h>
-#include <device/device.h>
-#include <fsp/ramstage.h>
-
-void pch_enable_dev(device_t dev);
-void soc_init_pre_device(void *chip_info);
-void soc_init_cpus(device_t dev);
-const char *soc_acpi_name(struct device *dev);
-
-extern struct pci_operations soc_pci_ops;
-
-#endif
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
deleted file mode 100644
index 6c40bd6..0000000
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_ROMSTAGE_H_
-#define _SOC_ROMSTAGE_H_
-
-#include <fsp/romstage.h>
-
-void systemagent_early_init(void);
-void intel_early_me_status(void);
-void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
-
-int early_spi_read_wpsr(u8 *sr);
-void mainboard_fill_spd_data(struct pei_data *pei_data);
-
-#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index fa8da46..1beaaa4 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <fsp/memmap.h>
-#include <fsp/romstage.h>
#include <soc/gpio.h>
struct ied_header {
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h
index d70fd21..1c19b88 100644
--- a/src/soc/intel/skylake/include/soc/vr_config.h
+++ b/src/soc/intel/skylake/include/soc/vr_config.h
@@ -19,7 +19,11 @@
#ifndef _SOC_VR_CONFIG_H_
#define _SOC_VR_CONFIG_H_
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/soc_binding.h>
+#else
+#include <fsp/api.h>
+#endif
struct vr_config {
@@ -74,7 +78,6 @@ enum vr_domain{
NUM_VR_DOMAINS
};
-void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
- const struct vr_config *cfg);
-
+void fill_vr_domain_config(void *params,
+ int domain, const struct vr_config *cfg);
#endif
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 6af1371..96debfd 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -21,7 +21,6 @@
#include <device/pci.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/systemagent.h>
#include <stdlib.h>
diff --git a/src/soc/intel/skylake/opregion.c b/src/soc/intel/skylake/opregion.c
new file mode 100644
index 0000000..31987cb
--- /dev/null
+++ b/src/soc/intel/skylake/opregion.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <soc/ramstage.h>
+#include <fsp/gop.h>
+#include <stdlib.h>
+#include <string.h>
+
+int init_igd_opregion(igd_opregion_t *opregion)
+{
+ const optionrom_vbt_t *vbt;
+ uint32_t vbt_len;
+
+ memset(opregion, 0, sizeof(igd_opregion_t));
+
+ /* Read VBT table from flash */
+ vbt = fsp_get_vbt(&vbt_len);
+ if (!vbt)
+ die("vbt data not found");
+
+ memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
+ sizeof(IGD_OPREGION_SIGNATURE) - 1);
+ memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
+ memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
+ sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
+ sizeof(opregion->vbt.gvd1));
+
+ /* Size, in KB, of the entire OpRegion structure (including header)*/
+ opregion->header.size = sizeof(igd_opregion_t) / KiB;
+ opregion->header.version = IGD_OPREGION_VERSION;
+
+ /* We just assume we're mobile for now */
+ opregion->header.mailboxes = MAILBOXES_MOBILE;
+
+ return 0;
+}
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
new file mode 100644
index 0000000..ab251ce
--- /dev/null
+++ b/src/soc/intel/skylake/reset.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <reset.h>
+
+void chipset_handle_reset(enum fsp_status status)
+{
+ switch(status) {
+ case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
+ printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
+ hard_reset();
+ break;
+ default:
+ printk(BIOS_ERR, "unhandled reset type %x\n", status);
+ die("unknown reset type");
+ break;
+ }
+}
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 31a452f..e552c39 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,7 +1,8 @@
-
verstage-y += power_state.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage.S
romstage-y += power_state.c
-romstage-y += romstage.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
romstage-y += spi.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S
new file mode 100644
index 0000000..c6401fa
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/car_stage.S
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <rules.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+.section ".text"
+.global car_stage_entry
+
+car_stage_entry:
+
+ /* Enter the C code */
+ call car_stage_c_entry
+
+/*
+ * Car teardown
+ */
+ /*
+ * eax: New stack address
+ */
+
+ /* Switch to the stack in RAM */
+ movl %eax, %esp
+
+ #include <soc/car_teardown.S>
+
+ /* Display the MTRRs */
+ call soc_display_mtrrs
+
+ /*
+ * The stack contents are initialized in src/soc/intel/common/stack.c
+ * to be the following:
+ *
+ * *
+ * *
+ * *
+ * +36: MTRR mask 1 63:32
+ * +32: MTRR mask 1 31:0
+ * +28: MTRR base 1 63:32
+ * +24: MTRR base 1 31:0
+ * +20: MTRR mask 0 63:32
+ * +16: MTRR mask 0 31:0
+ * +12: MTRR base 0 63:32
+ * +8: MTRR base 0 31:0
+ * +4: Number of MTRRs to setup (described above)
+ * +0: Number of variable MTRRs to clear
+ */
+
+ /* Clear all of the variable MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+ clr %eax
+ clr %edx
+
+1:
+ testl %ebx, %ebx
+ jz 1f
+ wrmsr /* Write MTRR base. */
+ inc %ecx
+ wrmsr /* Write MTRR mask. */
+ inc %ecx
+ dec %ebx
+ jmp 1b
+
+1:
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+2:
+ testl %ebx, %ebx
+ jz 2f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
+ wrmsr
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
+ wrmsr
+ inc %ecx
+
+ dec %ebx
+ jmp 2b
+2:
+
+ post_code(0x39)
+
+ /* And enable cache again after setting MTRRs. */
+ movl %cr0, %eax
+ andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+ movl %eax, %cr0
+
+ post_code(0x3a)
+
+ /* Enable MTRR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ orl $MTRR_DEF_TYPE_EN, %eax
+ wrmsr
+
+ post_code(0x3b)
+
+ /* Invalidate the cache again. */
+ invd
+
+__main:
+ post_code(POST_PREPARE_RAMSTAGE)
+ cld /* Clear direction flag. */
+
+ call copy_and_run
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
new file mode 100644
index 0000000..8a15a69
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/romstage.h>
+
+asmlinkage void *car_stage_c_entry(void)
+{
+ bool s3wake = false;
+ console_init();
+ /* TODO: Add fill_powerstate and determine sleep state. */
+ fsp_memory_init(s3wake);
+ return NULL;
+}
+static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)
+{
+ /* TODO: Fill SoC specific Memory init Params */
+}
+
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){
+
+ struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+ soc_memory_init_params(m_cfg);
+ mainboard_memory_init_params(mupd);
+}
+
+__attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+ /* Do nothing */
+}
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 40223e3..17ccd7d 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -14,6 +14,8 @@
*
*/
+#include <fsp/api.h>
+#include <soc/ramstage.h>
#include <soc/vr_config.h>
/* Default values for domain configuration. PSI3 and PSI4 are disabled. */
@@ -80,9 +82,10 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
},
};
-void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
- const struct vr_config *chip_cfg)
+void fill_vr_domain_config(void *params,
+ int domain, const struct vr_config *chip_cfg)
{
+ FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params;
const struct vr_config *cfg;
if (domain < 0 || domain >= NUM_VR_DOMAINS)
@@ -94,14 +97,14 @@ void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
else
cfg = &default_configs[domain];
- params->VrConfigEnable[domain] = cfg->vr_config_enable;
- params->Psi1Threshold[domain] = cfg->psi1threshold;
- params->Psi2Threshold[domain] = cfg->psi2threshold;
- params->Psi3Threshold[domain] = cfg->psi3threshold;
- params->Psi3Enable[domain] = cfg->psi3enable;
- params->Psi4Enable[domain] = cfg->psi4enable;
- params->ImonSlope[domain] = cfg->imon_slope;
- params->ImonOffset[domain] = cfg->imon_offset;
- params->IccMax[domain] = cfg->icc_max;
- params->VrVoltageLimit[domain] = cfg->voltage_limit;
+ vr_params->VrConfigEnable[domain] = cfg->vr_config_enable;
+ vr_params->Psi1Threshold[domain] = cfg->psi1threshold;
+ vr_params->Psi2Threshold[domain] = cfg->psi2threshold;
+ vr_params->Psi3Threshold[domain] = cfg->psi3threshold;
+ vr_params->Psi3Enable[domain] = cfg->psi3enable;
+ vr_params->Psi4Enable[domain] = cfg->psi4enable;
+ vr_params->ImonSlope[domain] = cfg->imon_slope;
+ vr_params->ImonOffset[domain] = cfg->imon_offset;
+ vr_params->IccMax[domain] = cfg->icc_max;
+ vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
}