coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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1551 discussions

Patch set updated for coreboot: nvramcui: remove undeclared variable
by Antonello Dettori 29 Aug '16

29 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16333 -gerrit commit 468c4a44d708e596f3dd38d4b5fb194454eefb35 Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Aug 18 10:32:27 2016 +0200 nvramcui: remove undeclared variable Remove an undeclared variable that was accidentally left over, nvramcui is currently unable to compile and operate because of this. Regression introduced in: https://review.coreboot.org/#/c/16248/ Change-Id: Ieaba615838d7593546ab5696baf1b8f9828da345 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/nvramcui/nvramcui.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index 991303e..84e5536 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -179,8 +179,8 @@ int main(void) struct cb_cmos_option_table *opttbl = get_system_option_table(); - if (opttbl == NULL && cmos_default == NULL) { - printf("Could not find coreboot option table/cmos.default.\n"); + if (opttbl == NULL) { + printf("Could not find coreboot option table.\n"); halt(); }

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Patch set updated for coreboot: nb/gm45/gma.c: enable VESA framebuffer mode on VGA output
by Arthur Heymans 29 Aug '16

29 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16338 -gerrit commit d1e4b2a49fe8ed39e7da700f7f37e2682e181f47 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Aug 27 01:09:19 2016 +0200 nb/gm45/gma.c: enable VESA framebuffer mode on VGA output This implements "Keep VESA framebuffer" behavior on VGA output of gm45. Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 246 ++++++++++++++++++++++++++++++++------- 1 file changed, 204 insertions(+), 42 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 74c9bc3..4d5a30a 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -345,14 +345,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, } static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - u8 *mmio) + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { int i; - u32 hactive, vactive; + u8 edid_data[128]; + struct edid edid; + struct edid_mode *mode; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 target_frequency; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + vga_gr_write(0x18, 0); + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + write32(mmio + VGA0, 0x31108); write32(mmio + VGA1, 0x31406); @@ -363,8 +387,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + 0x7041c, 0x0); write32(mmio + DPLL_MD(0), 0x3); @@ -382,25 +405,136 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); + udelay(1); + + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); + decode_edid(edid_data, + sizeof(edid_data), &edid); + mode = &edid.mode; + + /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); - hactive = 640; - vactive = 400; + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + target_frequency = 2 * mode->pixel_clock; + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } + + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } + + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) + / (link_frequency * 8 * 4); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); mdelay(1); - write32(mmio + FP0(0), 0x31108); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + FP0(0), ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | (pixel_m2 - 2)); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); + mdelay(1); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT @@ -409,49 +543,68 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); - + | ADPA_DPMS_ON); write32(mmio + HTOTAL(0), - ((hactive - 1) << 16) + ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); write32(mmio + HBLANK(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); write32(mmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); - write32(mmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive - 1) << 16) + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); write32(mmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1)); write32(mmio + PIPECONF(0), PIPECONF_DISABLE); write32(mmio + PF_WIN_POS(0), 0); - - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) + | (vactive - 1)); + write32(mmio + PF_CTL(0), 0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0x80000000); + } mdelay(1); + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + write32(mmio + 0x000f000c, 0x00002040); mdelay(1); write32(mmio + 0x000f000c, 0x00002050); write32(mmio + 0x00060100, 0x00044000); mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6); + write32(mmio + 0x000f0008, 0x00000040); + write32(mmio + 0x000f000c, 0x00022050); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + VGACNTRL, 0x0); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + VGACNTRL, VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + mdelay(1); + } else { + write32(mmio + VGACNTRL, 0xc4008e); + } write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT @@ -462,15 +615,22 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON ); + write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - vga_textmode_init(); - - /* Enable screen memory. */ + /* Enable screen memory. */ vga_sr_write(1, vga_sr_read(1) & ~0x20); /* Clear interrupts. */ write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset((void *) lfb, 0, + edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } + + } /* compare the header of the vga edid header */ @@ -480,6 +640,7 @@ static u8 vga_connected(u8 *mmio) u8 vga_edid[128]; u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); + intel_gmbus_stop(mmio + GMBUS0); for (int i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); @@ -566,7 +727,8 @@ static void gma_func0_init(struct device *dev) "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); if (vga_connected(res2mmio(gtt_res, 0, 0))) - gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); + gma_init_vga(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); else gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), physbase, pio_res->base, lfb_res->base);

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Patch set updated for coreboot: gm45/gma.c: use screen on vga connector if connected
by Arthur Heymans 29 Aug '16

29 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16295 -gerrit commit 96f12966c6cc5e3f697180570e66e9de165eceab Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Aug 22 17:58:46 2016 +0200 gm45/gma.c: use screen on vga connector if connected The intel x4x and gm45 have very similar integrated graphic devices. Currently the x4x native graphic init enables VGA, while gm45 can output on LVDS. This patch reuses the x4x graphic initialisation code to enable output on VGA in gm45 in a way that the behavior is similar to vbios: If no VGA display is connected the internal LVDS screen is used. If an external screen is detected on the VGA port it will be used instead. Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 153 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index d5f6471..74c9bc3 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -static void intel_gma_init(const struct northbridge_intel_gm45_config *info, +static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { @@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, sizeof(edid_data), &edid); mode = &edid.mode; - /* Disable screen memory to prevent garbage from appearing. */ + /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); hactive = edid.x_resolution; @@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, } } +static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + u8 *mmio) +{ + + int i; + u32 hactive, vactive; + + vga_gr_write(0x18, 0); + + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); + write32(mmio + DPLL_MD(1), 0x3); + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = 640; + vactive = 400; + + mdelay(1); + write32(mmio + FP0(0), 0x31108); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + HTOTAL(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HSYNC(0), + ((hactive - 1) << 16) + | (hactive - 1)); + + write32(mmio + VTOTAL(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VSYNC(0), + ((vactive - 1) << 16) + | (vactive - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); + + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + + mdelay(1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + write32(mmio + VGACNTRL, 0x0); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + vga_textmode_init(); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); +} + +/* compare the header of the vga edid header */ +/* if vga is not connected it should not have a correct header */ +static u8 vga_connected(u8 *mmio) +{ + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); + return 0; + } + } + printk(BIOS_SPEW, "VGA display connected\n"); + return 1; +} + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) + gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); } /* Linux relies on VBT for panel info. */

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Patch set updated for coreboot: nb/gm45/gma.c: enable VESA framebuffer mode on VGA output
by Arthur Heymans 29 Aug '16

29 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16338 -gerrit commit 01197ceeddb700d64f60559c7866e96f4fd03cdf Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Aug 27 01:09:19 2016 +0200 nb/gm45/gma.c: enable VESA framebuffer mode on VGA output This implements "Keep VESA framebuffer" behavior on VGA output of gm45. Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 250 ++++++++++++++++++++++++++++++++------- 1 file changed, 206 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index b520963..b4858d7 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -345,14 +345,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, } static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - u8 *mmio) + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { int i; - u32 hactive, vactive; + u8 edid_data[128]; + struct edid edid; + struct edid_mode *mode; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 target_frequency; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + vga_gr_write(0x18, 0); + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + write32(mmio + VGA0, 0x31108); write32(mmio + VGA1, 0x31406); @@ -363,8 +387,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + 0x7041c, 0x0); write32(mmio + DPLL_MD(0), 0x3); @@ -382,25 +405,136 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); + udelay(1); + + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); + decode_edid(edid_data, + sizeof(edid_data), &edid); + mode = &edid.mode; + + /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); - hactive = 640; - vactive = 400; + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + target_frequency = 2 * mode->pixel_clock; + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } + + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } + + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) + / (link_frequency * 8 * 4); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); mdelay(1); - write32(mmio + FP0(0), 0x31108); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + FP0(0), ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | (pixel_m2 - 2)); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); + mdelay(1); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT @@ -409,49 +543,68 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); - + | ADPA_DPMS_ON); write32(mmio + HTOTAL(0), - ((hactive - 1) << 16) + ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); write32(mmio + HBLANK(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); write32(mmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); - write32(mmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive - 1) << 16) + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); write32(mmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1)); write32(mmio + PIPECONF(0), PIPECONF_DISABLE); write32(mmio + PF_WIN_POS(0), 0); - - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) + | (vactive - 1)); + write32(mmio + PF_CTL(0), 0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0x80000000); + } mdelay(1); + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + write32(mmio + 0x000f000c, 0x00002040); mdelay(1); write32(mmio + 0x000f000c, 0x00002050); write32(mmio + 0x00060100, 0x00044000); mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6); + write32(mmio + 0x000f0008, 0x00000040); + write32(mmio + 0x000f000c, 0x00022050); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + VGACNTRL, 0x0); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + VGACNTRL, VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + mdelay(1); + } else { + write32(mmio + VGACNTRL, 0xc4008e); + } write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT @@ -462,24 +615,32 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON ); + write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - vga_textmode_init(); - - /* Enable screen memory. */ + /* Enable screen memory. */ vga_sr_write(1, vga_sr_read(1) & ~0x20); /* Clear interrupts. */ write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset((void *) lfb, 0, + edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } + + } -/* compare the header of the vga edid header - if vga is not connected it should not have a correct header */ +/* compare the header of the vga edid header */ +/* if vga is not connected it should not have a correct header */ static u8 vga_connected(u8 *mmio) { u8 vga_edid[128]; u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); + intel_gmbus_stop(mmio + GMBUS0); for (int i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_SPEW, "VGA not connected. Using LVDS display\n"); @@ -566,7 +727,8 @@ static void gma_func0_init(struct device *dev) "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); if (vga_connected(res2mmio(gtt_res, 0, 0))) - gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); + gma_init_vga(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); else gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), physbase, pio_res->base, lfb_res->base);

1 0

Patch set updated for coreboot: gm45/gma.c: clean up some registers
by Arthur Heymans 29 Aug '16

29 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16217 -gerrit commit c72bbbf768e3aaf563714123ea7a04aff24dc7da Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Aug 15 00:04:34 2016 +0200 gm45/gma.c: clean up some registers According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" some registries are set incorrectly in gm45/gma.c. Some values are changed after comparing them with the values the i915 linux kernel (3.13 was used) module sets while modesetting. The values were obtained using 'intel_reg' from intel-gpu-tools, during a normal boot and with 'nomodeset' as a kernel argument. Some registers that don't exist on gm45 are set in gma.c, which is probably the result of copying code from a more recent intel northbridge. The result is that that gm45 laptops with wxga displays still work as before. gm45 laptops with wxga+ or higher resolution now just work, where previously a black screen was shown. TEST: build with native graphic init and flash on a gm45 target, like lenovo x200. Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 110 +++++++-------------------------------- 1 file changed, 18 insertions(+), 92 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index a89f9bb..d5f6471 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -47,60 +47,6 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -static void power_port(u8 *mmio) -{ - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - write32(mmio + 0x00061100, 0x00010000); - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - read32(mmio + 0x00061100); // = 0x00000000 - read32(mmio + 0x00064200); // = 0x0000001c - write32(mmio + 0x00064210, 0x8004003e); - write32(mmio + 0x00064214, 0x80060002); - write32(mmio + 0x00064218, 0x01000000); - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - write32(mmio + 0x00064f00, 0x0100030c); - write32(mmio + 0x00064f04, 0x00b8230c); - write32(mmio + 0x00064f08, 0x06f8930c); - write32(mmio + 0x00064f0c, 0x09f8e38e); - write32(mmio + 0x00064f10, 0x00b8030c); - write32(mmio + 0x00064f14, 0x0b78830c); - write32(mmio + 0x00064f18, 0x0ff8d3cf); - write32(mmio + 0x00064f1c, 0x01e8030c); - write32(mmio + 0x00064f20, 0x0ff863cf); - write32(mmio + 0x00064f24, 0x0ff803cf); - write32(mmio + 0x000c4030, 0x00001000); - read32(mmio + 0x00044000); // = 0x00000000 - write32(mmio + 0x00044030, 0x00001000); - read32(mmio + 0x00061150); // = 0x0000001c - write32(mmio + 0x00061150, 0x0000089c); - write32(mmio + 0x000fcc00, 0x01986f00); - write32(mmio + 0x000fcc0c, 0x01986f00); - write32(mmio + 0x000fcc18, 0x01986f00); - write32(mmio + 0x000fcc24, 0x01986f00); - read32(mmio + 0x00044000); // = 0x00000000 - read32(mmio + LVDS); // = 0x40000002 -} - static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { @@ -150,8 +96,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); - power_port(mmio); - intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128); decode_edid(edid_data, sizeof(edid_data), &edid); @@ -277,28 +221,32 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + | LVDS_ENABLE_DITHER + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_PIPE(0)); mdelay(1); write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(mmio + FP0(0), ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); + | ((pixel_m1 - 2) << 8) | (pixel_m2 - 2)); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | DPLL_VGA_MODE_DIS | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); + | (6 << PLL_LOAD_PULSE_PHASE_SHIFT)); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | DPLL_VGA_MODE_DIS | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); + | (6 << PLL_LOAD_PULSE_PHASE_SHIFT)); /* Re-lock the registers. */ write32(mmio + PP_CONTROL, (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); @@ -307,7 +255,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_ENABLE_DITHER + | LVDS_PIPE(0)); write32(mmio + HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) @@ -324,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1)); write32(mmio + VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) | (vactive + bottom_border + vfront_porch - 1)); write32(mmio + PIPECONF(0), PIPECONF_DISABLE); @@ -335,7 +285,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | (vactive - 1)); write32(mmio + PF_CTL(0), 0); write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PFIT_CONTROL, 0x20000000); + write32(mmio + PFIT_CONTROL, 0); } else { write32(mmio + PIPESRC(0), (639 << 16) | 399); write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); @@ -362,7 +312,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { - write32(mmio + VGACNTRL, 0xc4008e | VGA_DISP_DISABLE); + write32(mmio + VGACNTRL, VGA_DISP_DISABLE); write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); mdelay(1); @@ -370,37 +320,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + VGACNTRL, 0xc4008e); } - write32(mmio + TRANS_HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + TRANS_HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + TRANS_HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + TRANS_VTOTAL(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + TRANS_VBLANK(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + TRANS_VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + 0x00060100, 0xb01c4000); - write32(mmio + 0x000f000c, 0xb01a2050); - mdelay(1); - write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC - ); - write32(mmio + LVDS, - LVDS_PORT_ENABLE + write32(mmio + LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_ENABLE_DITHER + | LVDS_PIPE(0)); write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);

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Patch set updated for coreboot: gm45/gma.c: use screen on vga connector if connected
by Arthur Heymans 29 Aug '16

29 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16295 -gerrit commit e250fa33291fd69c7b9ee2bc0beb041dc88193ed Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Aug 22 17:58:46 2016 +0200 gm45/gma.c: use screen on vga connector if connected The intel x4x native graphic init works on gm45 to use the vga screen instead of the integrated lvds screen. This patch integrates it in gm45 in a way that the behavior is similar to vbios: If no vga display is connected the internal lvds screen is used. If an external screen is detected on the vga port it will be used instead. Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 155 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 152 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index d5f6471..b520963 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -static void intel_gma_init(const struct northbridge_intel_gm45_config *info, +static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { @@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, } } +static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + u8 *mmio) +{ + + int i; + u32 hactive, vactive; + + vga_gr_write(0x18, 0); + + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); + write32(mmio + DPLL_MD(1), 0x3); + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = 640; + vactive = 400; + + mdelay(1); + write32(mmio + FP0(0), 0x31108); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + HTOTAL(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HSYNC(0), + ((hactive - 1) << 16) + | (hactive - 1)); + + write32(mmio + VTOTAL(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VSYNC(0), + ((vactive - 1) << 16) + | (vactive - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); + + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + + mdelay(1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + write32(mmio + VGACNTRL, 0x0); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + vga_textmode_init(); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); +} + +/* compare the header of the vga edid header + if vga is not connected it should not have a correct header */ +static u8 vga_connected(u8 *mmio) +{ + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_SPEW, "VGA not connected. Using LVDS display\n"); + return 0; + } + } + printk(BIOS_SPEW, "VGA display connected\n"); + return 1; +} + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) + gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); } /* Linux relies on VBT for panel info. */

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New patch to review for coreboot: fsp_broadwell_de: Refactor code for SPI debug messages
by Werner Zeh 29 Aug '16

29 Aug '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16347 -gerrit commit 8649c4b9535d072743420e1a47a6420d349273cf Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Aug 29 08:00:50 2016 +0200 fsp_broadwell_de: Refactor code for SPI debug messages Currently boards based on fsp_broadwell_de fail to compile if the config switch CONFIG_DEBUG_SPI_FLASH is selected. The error is caused by the usage of const for the address pointer in the functions writeb_, writew_ and writel_. The reason why it stayed hidden for so long is the fact that the switch is used with the preprocessor and nobody really selects it until there is a bug one want to find in this area. This patch fixes the parameter type definition which solves the error. In addition the config switch is not used on preprocessor level anymore but instead on compiler level. This ensures that at least the code syntax is checked on build time even if the config option is not selected. Change-Id: I3514b0d4c08bf5a4740f2632641e09af1b3aaf3a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_broadwell_de/spi.c | 56 ++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index f98ab97..57f7951 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -1,6 +1,7 @@ /* * Copyright (c) 2013 Google Inc. * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2016 Siemens AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -158,64 +159,63 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) - static u8 readb_(const void *addr) { u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + } return v; } static u16 readw_(const void *addr) { u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + } return v; } static u32 readl_(const void *addr) { u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + } return v; } -static void writeb_(u8 b, const void *addr) +static void writeb_(u8 b, void *addr) { write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); + } } -static void writew_(u16 b, const void *addr) +static void writew_(u16 b, void *addr) { write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); + } } -static void writel_(u32 b, const void *addr) +static void writel_(u32 b, void *addr) { write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); + } } -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - static void write_reg(const void *value, void *dest, uint32_t size) { const uint8_t *bvalue = value;

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Patch set updated for coreboot: soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK.
by HAOUAS Elyes 28 Aug '16

28 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16343 -gerrit commit 26011b600c55a12a65e655dcbab4d2cfb50a6bf3 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 28 19:18:38 2016 +0200 soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK. Change-Id: I5b69a8429eb2f7add08bc134d5d2366a1afe6a4f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/soc/broadcom/cygnus/ddr_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index 7fa2a56..7488750 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -317,14 +317,14 @@ int cygnus_phy_powerup(void) if(reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0) { - /* Step 1: POWRON */ + /* Step 1: POWER ON */ data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL); data |= 0x8;// assert power ON reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data); __udelay(2); - /* Step 2: POWROK */ + /* Step 2: POWER OK */ data |= 0x10;// assert power OK reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);

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New patch to review for coreboot: soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and OK.
by HAOUAS Elyes 28 Aug '16

28 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16343 -gerrit commit af29b0d4f2ab269d26b68131cdae5e8835886b4a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 28 19:18:38 2016 +0200 soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and OK. Change-Id: I5b69a8429eb2f7add08bc134d5d2366a1afe6a4f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/soc/broadcom/cygnus/ddr_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index 7fa2a56..7488750 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -317,14 +317,14 @@ int cygnus_phy_powerup(void) if(reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0) { - /* Step 1: POWRON */ + /* Step 1: POWER ON */ data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL); data |= 0x8;// assert power ON reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data); __udelay(2); - /* Step 2: POWROK */ + /* Step 2: POWER OK */ data |= 0x10;// assert power OK reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);

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Patch merged into coreboot/master: src/arch: Add required space before opening parenthesis '('
by gerrit＠coreboot.org 28 Aug '16

28 Aug '16

the following patch was just integrated into master: commit dbf30678ee658fedca68a75277cd5c005d9833ef Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 17:37:15 2016 +0200 src/arch: Add required space before opening parenthesis '(' Change-Id: I8a44a58506d7cf5ebc9fe7ac4f2b46f9544ba61a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16287 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16287 for details. -gerrit

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